diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing')
4 files changed, 0 insertions, 1980 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index 1d1d7a36d..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2 -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index e0bca4e4e..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index 03b7f79ab..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28058 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 684199968000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index 6249c394a..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,1119 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.684200 # Number of seconds simulated -sim_ticks 684199968000 # Number of ticks simulated -final_tick 684199968000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 295566 # Simulator instruction rate (inst/s) -host_op_rate 295566 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116486932 # Simulator tick rate (ticks/s) -host_mem_usage 257340 # Number of bytes of host memory used -host_seconds 5873.62 # Real time elapsed on the host -sim_insts 1736043781 # Number of instructions simulated -sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126674880 # Number of bytes read from this memory -system.physmem.bytes_read::total 126735616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66206592 # Number of bytes written to this memory -system.physmem.bytes_written::total 66206592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1979295 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1980244 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1034478 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1034478 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 88769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 185143066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 185231836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 88769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 88769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96764974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96764974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96764974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 88769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 185143066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 281996809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1980244 # Number of read requests accepted -system.physmem.writeReqs 1034478 # Number of write requests accepted -system.physmem.readBursts 1980244 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1034478 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 126652288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83328 # Total number of bytes read from write queue -system.physmem.bytesWritten 66205120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126735616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66206592 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1302 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119682 # Per bank write bursts -system.physmem.perBankRdBursts::1 115093 # Per bank write bursts -system.physmem.perBankRdBursts::2 117079 # Per bank write bursts -system.physmem.perBankRdBursts::3 118658 # Per bank write bursts -system.physmem.perBankRdBursts::4 118799 # Per bank write bursts -system.physmem.perBankRdBursts::5 118596 # Per bank write bursts -system.physmem.perBankRdBursts::6 121104 # Per bank write bursts -system.physmem.perBankRdBursts::7 126057 # Per bank write bursts -system.physmem.perBankRdBursts::8 128556 # Per bank write bursts -system.physmem.perBankRdBursts::9 131368 # Per bank write bursts -system.physmem.perBankRdBursts::10 130043 # Per bank write bursts -system.physmem.perBankRdBursts::11 131744 # Per bank write bursts -system.physmem.perBankRdBursts::12 127398 # Per bank write bursts -system.physmem.perBankRdBursts::13 126519 # Per bank write bursts -system.physmem.perBankRdBursts::14 123764 # Per bank write bursts -system.physmem.perBankRdBursts::15 124482 # Per bank write bursts -system.physmem.perBankWrBursts::0 62070 # Per bank write bursts -system.physmem.perBankWrBursts::1 62408 # Per bank write bursts -system.physmem.perBankWrBursts::2 61409 # Per bank write bursts -system.physmem.perBankWrBursts::3 62103 # Per bank write bursts -system.physmem.perBankWrBursts::4 62566 # Per bank write bursts -system.physmem.perBankWrBursts::5 64096 # Per bank write bursts -system.physmem.perBankWrBursts::6 65160 # Per bank write bursts -system.physmem.perBankWrBursts::7 66609 # Per bank write bursts -system.physmem.perBankWrBursts::8 66404 # Per bank write bursts -system.physmem.perBankWrBursts::9 66820 # Per bank write bursts -system.physmem.perBankWrBursts::10 66475 # Per bank write bursts -system.physmem.perBankWrBursts::11 66816 # Per bank write bursts -system.physmem.perBankWrBursts::12 65322 # Per bank write bursts -system.physmem.perBankWrBursts::13 65320 # Per bank write bursts -system.physmem.perBankWrBursts::14 65711 # Per bank write bursts -system.physmem.perBankWrBursts::15 65166 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 684199865500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1980244 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1034478 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1615224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 253124 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 51175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 58148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61668 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1786108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.975625 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.936522 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 138.228671 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1386417 77.62% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 276583 15.49% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52891 2.96% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20920 1.17% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12358 0.69% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6524 0.37% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5164 0.29% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3751 0.21% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21500 1.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1786108 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61165 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.352277 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 22.914892 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 140.448273 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 60991 99.72% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 137 0.22% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 7 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 4 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 5 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 3 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 4 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61165 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61165 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.912532 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.877578 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.101156 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 34708 56.74% 56.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1369 2.24% 58.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 21665 35.42% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2721 4.45% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 576 0.94% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 109 0.18% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61165 # Writes before turning the bus around for reads -system.physmem.totQLat 56581400750 # Total ticks spent queuing -system.physmem.totMemAccLat 93686563250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9894710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28591.74 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47341.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 185.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 96.76 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 185.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.76 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.20 # Data bus utilization in percentage -system.physmem.busUtilRead 1.45 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing -system.physmem.readRowHits 796002 # Number of row buffer hits during reads -system.physmem.writeRowHits 431282 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.69 # Row buffer hit rate for writes -system.physmem.avgGap 226952.89 # Average gap between requests -system.physmem.pageHitRate 40.73 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6177735060 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3283540260 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6819185520 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2643517620 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 44816475600.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 37044798750 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1443275040 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 170396037690 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 31359460320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 36616359660 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 340610162070 # Total energy per rank (pJ) -system.physmem_0.averagePower 497.822532 # Core power per rank (mW) -system.physmem_0.totalIdleTime 599184631500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1534958250 # Time in different power states -system.physmem_0.memoryStateTime::REF 18981984000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 143840379000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 81664935250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 64497738500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 373679973000 # Time in different power states -system.physmem_1.actEnergy 6575111760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3494739600 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7310460360 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2756337480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 45376412640.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 37526229300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1410684000 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 175219175340 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 30265452000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 34407180735 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 344356241235 # Total energy per rank (pJ) -system.physmem_1.averagePower 503.297652 # Core power per rank (mW) -system.physmem_1.totalIdleTime 598199672750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1433387500 # Time in different power states -system.physmem_1.memoryStateTime::REF 19217296000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 135130926250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 78815070250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 65349556500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 384253731500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 409436754 # Number of BP lookups -system.cpu.branchPred.condPredicted 318234486 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15963820 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 282367334 # Number of BTB lookups -system.cpu.branchPred.BTBHits 278623697 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.674196 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26172484 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 47 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 12628 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1002 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 11626 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 76 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 645003218 # DTB read hits -system.cpu.dtb.read_misses 12159343 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 657162561 # DTB read accesses -system.cpu.dtb.write_hits 218108239 # DTB write hits -system.cpu.dtb.write_misses 7507876 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225616115 # DTB write accesses -system.cpu.dtb.data_hits 863111457 # DTB hits -system.cpu.dtb.data_misses 19667219 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 882778676 # DTB accesses -system.cpu.itb.fetch_hits 420694791 # ITB hits -system.cpu.itb.fetch_misses 37 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 420694828 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1368399937 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 431834940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3410573803 # Number of instructions fetch has processed -system.cpu.fetch.Branches 409436754 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 304797183 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 913784247 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45380414 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1708 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 420694791 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8284167 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1368311169 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.492543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.138689 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 743223403 54.32% 54.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47685517 3.48% 57.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24183643 1.77% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45097399 3.30% 62.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142825430 10.44% 73.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 65953370 4.82% 78.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43585313 3.19% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29408397 2.15% 83.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226348697 16.54% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1368311169 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.299208 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.492381 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 353769261 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 432754726 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 524267891 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34829792 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22689499 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62032551 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3256358950 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22689499 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 372017301 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 224454621 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9976 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 537214927 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 211924845 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3173979679 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1947204 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21862090 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 161736150 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 34961727 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2371970000 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4117940809 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4117804241 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 136567 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 995767037 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 144 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 143 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99713027 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 717292360 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272467386 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90468830 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58360421 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2884387847 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 125 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2620166340 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1550282 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1148344190 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 502911540 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 96 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1368311169 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.914891 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.143845 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 564702258 41.27% 41.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169734991 12.40% 53.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158008570 11.55% 65.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149164272 10.90% 76.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126054849 9.21% 85.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84104604 6.15% 91.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68048276 4.97% 96.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34057471 2.49% 98.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14435878 1.06% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1368311169 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13157745 35.86% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18955559 51.65% 87.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4574949 12.47% 99.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 21 0.00% 99.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 8342 0.02% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1716973131 65.53% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 895059 0.03% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 21 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 671606942 25.63% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230625627 8.80% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 214 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 65011 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2620166340 # Type of FU issued -system.cpu.iq.rate 1.914766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36696616 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014005 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6644950011 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4031627633 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2518705843 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1940736 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1246935 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 885827 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2655894066 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 968890 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69399237 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 272696697 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 372755 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 144718 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 111738884 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 276 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6347426 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22689499 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 153700665 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24607409 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3035418130 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6594075 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 717292360 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272467386 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 125 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 793020 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 24069505 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 144718 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10634250 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8701065 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19335315 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2575033857 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 657162570 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45132483 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151030158 # number of nop insts executed -system.cpu.iew.exec_refs 882778753 # number of memory reference insts executed -system.cpu.iew.exec_branches 315511040 # Number of branches executed -system.cpu.iew.exec_stores 225616183 # Number of stores executed -system.cpu.iew.exec_rate 1.881785 # Inst execution rate -system.cpu.iew.wb_sent 2549403036 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2519591670 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1487461563 # num instructions producing a value -system.cpu.iew.wb_consumers 1918503373 # num instructions consuming a value -system.cpu.iew.wb_rate 1.841268 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775324 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 998993468 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15963112 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1230277663 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.479162 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.528603 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 741569515 60.28% 60.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159647987 12.98% 73.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79500884 6.46% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52016561 4.23% 83.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28471103 2.31% 86.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19445294 1.58% 87.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19999560 1.63% 89.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23041626 1.87% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106585133 8.66% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1230277663 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1819780126 # Number of instructions committed -system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 605324165 # Number of memory references committed -system.cpu.commit.loads 444595663 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 214632552 # Number of branches committed -system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. -system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 444595584 24.43% 91.17% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 160728448 8.83% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 79 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 54 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106585133 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3856686924 # The number of ROB reads -system.cpu.rob.rob_writes 5775715040 # The number of ROB writes -system.cpu.timesIdled 709 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 88768 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1736043781 # Number of Instructions Simulated -system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.788229 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.788229 # CPI: Total CPI of All Threads -system.cpu.ipc 1.268667 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.268667 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3463738117 # number of integer regfile reads -system.cpu.int_regfile_writes 2019389646 # number of integer regfile writes -system.cpu.fp_regfile_reads 39803 # number of floating regfile reads -system.cpu.fp_regfile_writes 598 # number of floating regfile writes -system.cpu.misc_regfile_reads 25 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9207265 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.531672 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 712311191 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9211361 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.329636 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5174346500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.531672 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997933 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997933 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 666 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2980 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1470218079 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1470218079 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 556814159 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 556814159 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155497028 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155497028 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 712311187 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 712311187 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 712311187 # number of overall hits -system.cpu.dcache.overall_hits::total 712311187 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12960693 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12960693 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5231474 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5231474 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 18192167 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 18192167 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 18192167 # number of overall misses -system.cpu.dcache.overall_misses::total 18192167 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 452018170000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 452018170000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 345871511780 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 345871511780 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 79500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 79500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 797889681780 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 797889681780 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 797889681780 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 797889681780 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 569774852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 569774852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 730503354 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 730503354 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 730503354 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 730503354 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022747 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022747 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032549 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032549 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024904 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024904 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024904 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024904 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34876.080315 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34876.080315 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66113.587066 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66113.587066 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 79500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 79500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 43858.968631 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 43858.968631 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 43858.968631 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 43858.968631 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16718017 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10716708 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1109373 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 69036 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.069789 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 155.233617 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3713171 # number of writebacks -system.cpu.dcache.writebacks::total 3713171 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5628505 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5628505 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3352302 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3352302 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8980807 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8980807 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8980807 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8980807 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332188 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7332188 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879172 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879172 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9211360 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9211360 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9211360 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9211360 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194855974500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 194855974500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91510360097 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91510360097 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 78500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 78500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286366334597 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 286366334597 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286366334597 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 286366334597 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26575.419847 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26575.419847 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48697.170933 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48697.170933 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 78500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 78500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31088.388099 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31088.388099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31088.388099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31088.388099 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 753.632230 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 420693280 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 949 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 443301.664910 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 753.632230 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.367984 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.367984 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 948 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 882 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 841390531 # Number of tag accesses -system.cpu.icache.tags.data_accesses 841390531 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 420693280 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 420693280 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 420693280 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 420693280 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 420693280 # number of overall hits -system.cpu.icache.overall_hits::total 420693280 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1511 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1511 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1511 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1511 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1511 # number of overall misses -system.cpu.icache.overall_misses::total 1511 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 138965499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 138965499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 138965499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 138965499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 138965499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 138965499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 420694791 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 420694791 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 420694791 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 420694791 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 420694791 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 420694791 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91969.225017 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 91969.225017 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 91969.225017 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 91969.225017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 91969.225017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 91969.225017 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 347 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 115.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 562 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 562 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 562 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 562 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 562 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 562 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 949 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 949 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 949 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 949 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 93919999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 93919999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 93919999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 93919999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 93919999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 93919999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98967.332982 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98967.332982 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98967.332982 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 98967.332982 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98967.332982 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 98967.332982 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1947802 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32040.149631 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16438766 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1980570 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.300018 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28106474000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8.660797 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.112733 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32006.376101 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000264 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000766 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.976757 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.977788 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3407 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 643 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13986 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 14548 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149337178 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149337178 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3713171 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3713171 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095576 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095576 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6136490 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6136490 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7232066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7232066 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7232066 # number of overall hits -system.cpu.l2cache.overall_hits::total 7232066 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 783612 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 783612 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 949 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 949 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1195683 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1195683 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 949 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1979295 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1980244 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 949 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1979295 # number of overall misses -system.cpu.l2cache.overall_misses::total 1980244 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76631269000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 76631269000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 92491000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 92491000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 118466842500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 118466842500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 92491000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 195098111500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 195190602500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 92491000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 195098111500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 195190602500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3713171 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3713171 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879188 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1879188 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 949 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 949 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7332173 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7332173 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 949 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9211361 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9212310 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 949 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9211361 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9212310 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.416995 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.416995 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.163073 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.163073 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214875 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214956 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214875 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214956 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97792.362802 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97792.362802 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 97461.538462 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 97461.538462 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99078.804750 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99078.804750 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 97461.538462 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98569.496462 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98568.965491 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 97461.538462 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98569.496462 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98568.965491 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1034478 # number of writebacks -system.cpu.l2cache.writebacks::total 1034478 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 240 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 783612 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 783612 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 949 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 949 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1195683 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1195683 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1979295 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1980244 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1979295 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1980244 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68795149000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68795149000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 83001000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 83001000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 106510012500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 106510012500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 83001000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 175305161500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 175388162500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 83001000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 175305161500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 175388162500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.416995 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.416995 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.163073 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.163073 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214875 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214956 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214875 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214956 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87792.362802 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87792.362802 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 87461.538462 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 87461.538462 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89078.804750 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89078.804750 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 87461.538462 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88569.496462 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88568.965491 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 87461.538462 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88569.496462 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88568.965491 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18419576 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207266 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1448 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1448 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7333122 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4747649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6407418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 949 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332173 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27631886 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827170048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827230848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1947802 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66206592 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11160112 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011390 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11158664 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1448 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11160112 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12922960000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1423500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13817041500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3926838 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1946594 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1196632 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1034478 # Transaction distribution -system.membus.trans_dist::CleanEvict 912116 # Transaction distribution -system.membus.trans_dist::ReadExReq 783612 # Transaction distribution -system.membus.trans_dist::ReadExResp 783612 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1196632 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5907082 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5907082 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192942208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192942208 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1980244 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1980244 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1980244 # Request fanout histogram -system.membus.reqLayer0.occupancy 8533086500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 10770167500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |