diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing')
3 files changed, 721 insertions, 697 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 2f4837fe9..fb395fc71 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 3e5b31249..78436c89b 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 10:10:10 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:41:35 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 621254733000 because target called exit() +Exiting @ tick 655919824500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 4dfb5e529..c867780d0 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.676099 # Number of seconds simulated -sim_ticks 676099363500 # Number of ticks simulated -final_tick 676099363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.655920 # Number of seconds simulated +sim_ticks 655919824500 # Number of ticks simulated +final_tick 655919824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178127 # Simulator instruction rate (inst/s) -host_op_rate 178127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69371375 # Simulator tick rate (ticks/s) -host_mem_usage 459324 # Number of bytes of host memory used -host_seconds 9746.09 # Real time elapsed on the host +host_inst_rate 137989 # Simulator instruction rate (inst/s) +host_op_rate 137989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52135439 # Simulator tick rate (ticks/s) +host_mem_usage 496344 # Number of bytes of host memory used +host_seconds 12581.07 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125805120 # Number of bytes read from this memory -system.physmem.bytes_read::total 125866688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65265216 # Number of bytes written to this memory -system.physmem.bytes_written::total 65265216 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965705 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966667 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019769 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019769 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 91064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 186074898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 186165961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91064 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91064 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96531989 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96531989 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96531989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 186074898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 282697950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966667 # Total number of read requests seen -system.physmem.writeReqs 1019769 # Total number of write requests seen -system.physmem.cpureqs 2986436 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125866688 # Total number of bytes read from memory -system.physmem.bytesWritten 65265216 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125866688 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65265216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 625 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125796416 # Number of bytes read from this memory +system.physmem.bytes_read::total 125857920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65262592 # Number of bytes written to this memory +system.physmem.bytes_written::total 65262592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965569 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966530 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019728 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019728 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 191786269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 191880037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 99497819 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 99497819 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 99497819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 191786269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 291377856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966530 # Total number of read requests seen +system.physmem.writeReqs 1019728 # Total number of write requests seen +system.physmem.cpureqs 2986258 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125857920 # Total number of bytes read from memory +system.physmem.bytesWritten 65262592 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125857920 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65262592 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 571 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 123034 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 123551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 123227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 121682 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123042 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122572 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 124906 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 123907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121965 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 123012 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 120476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 120832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 122358 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 124956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123644 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 63494 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63931 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63515 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 63255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 62796 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63501 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63537 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 62612 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63480 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 64069 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 63419 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64057 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64815 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 123004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 123537 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 123239 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 121669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 124908 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 123890 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122835 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 123027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 120429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 120849 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 122324 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 124974 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123664 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63268 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 63478 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63945 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63503 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 63256 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 62809 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63505 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63532 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 62611 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63461 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 64078 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 63409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64056 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64812 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 65441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64562 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64564 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 676099295000 # Total gap between requests +system.physmem.totGap 655919756000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966667 # Categorize read packet sizes +system.physmem.readPktSize::6 1966530 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1019769 # categorize write packet sizes +system.physmem.writePktSize::6 1019728 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,13 +105,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1634338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 235140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 26277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1634092 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 26268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 43349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44312 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 20663639504 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 85829737504 # Sum of mem lat for all requests -system.physmem.totBusLat 7864168000 # Total cycles spent in databus access -system.physmem.totBankLat 57301930000 # Total cycles spent in bank access -system.physmem.avgQLat 10510.27 # Average queueing delay per request -system.physmem.avgBankLat 29145.83 # Average bank access latency per request +system.physmem.totQLat 20705208242 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 85868216242 # Sum of mem lat for all requests +system.physmem.totBusLat 7863836000 # Total cycles spent in databus access +system.physmem.totBankLat 57299172000 # Total cycles spent in bank access +system.physmem.avgQLat 10531.86 # Average queueing delay per request +system.physmem.avgBankLat 29145.66 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43656.11 # Average memory access latency -system.physmem.avgRdBW 186.17 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 96.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 186.17 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 96.53 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 43677.52 # Average memory access latency +system.physmem.avgRdBW 191.88 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 99.50 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 191.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 99.50 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.77 # Data bus utilization in percentage +system.physmem.busUtil 1.82 # Data bus utilization in percentage system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 11.69 # Average write queue length over time -system.physmem.readRowHits 840809 # Number of row buffer hits during reads -system.physmem.writeRowHits 193935 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.55 # Average write queue length over time +system.physmem.readRowHits 840760 # Number of row buffer hits during reads +system.physmem.writeRowHits 193886 # Number of row buffer hits during writes system.physmem.readRowHitRate 42.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 19.02 # Row buffer hit rate for writes -system.physmem.avgGap 226390.02 # Average gap between requests +system.physmem.writeRowHitRate 19.01 # Row buffer hit rate for writes +system.physmem.avgGap 219646.04 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 623300287 # DTB read hits -system.cpu.dtb.read_misses 11248161 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 634548448 # DTB read accesses -system.cpu.dtb.write_hits 212126260 # DTB write hits -system.cpu.dtb.write_misses 7156273 # DTB write misses +system.cpu.dtb.read_hits 613741491 # DTB read hits +system.cpu.dtb.read_misses 11247891 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 624989382 # DTB read accesses +system.cpu.dtb.write_hits 212247245 # DTB write hits +system.cpu.dtb.write_misses 7144332 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219282533 # DTB write accesses -system.cpu.dtb.data_hits 835426547 # DTB hits -system.cpu.dtb.data_misses 18404434 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 853830981 # DTB accesses -system.cpu.itb.fetch_hits 409165317 # ITB hits -system.cpu.itb.fetch_misses 53 # ITB misses +system.cpu.dtb.write_accesses 219391577 # DTB write accesses +system.cpu.dtb.data_hits 825988736 # DTB hits +system.cpu.dtb.data_misses 18392223 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 844380959 # DTB accesses +system.cpu.itb.fetch_hits 390708850 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 409165370 # ITB accesses +system.cpu.itb.fetch_accesses 390708888 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,246 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1352198728 # number of cpu cycles simulated +system.cpu.numCycles 1311839650 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 392126599 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 302845458 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19199722 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 274650283 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 270818962 # Number of BTB hits +system.cpu.BPredUnit.lookups 381024003 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 296029232 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16079219 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 261934224 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 259237388 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25776268 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6145 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421462775 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3238747115 # Number of instructions fetch has processed -system.cpu.fetch.Branches 392126599 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 296595230 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 591261083 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 148936596 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 163448952 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1316 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 409165317 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10196267 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1298229870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494741 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.143526 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 24703724 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3041 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 402148068 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3157560086 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381024003 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 283941112 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 573880213 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140086808 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 165153102 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1285 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 390708850 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8061624 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1257505437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.510971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.156516 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 706968787 54.46% 54.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 44358932 3.42% 57.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22743833 1.75% 59.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 41944085 3.23% 62.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 132056857 10.17% 73.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 64435006 4.96% 77.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41239075 3.18% 81.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30635006 2.36% 83.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 213848289 16.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 683625224 54.36% 54.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42619367 3.39% 57.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21744894 1.73% 59.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39684878 3.16% 62.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129121337 10.27% 72.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61516601 4.89% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38545793 3.07% 80.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28125558 2.24% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212521785 16.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1298229870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.289992 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.395171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 455239490 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 145264666 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 557656082 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18015537 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 122054095 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 61382914 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1012 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3154733525 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2110 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 122054095 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 478678718 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 92924622 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7988 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 549590922 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 54973525 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3070816575 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 560752 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1743859 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 49056518 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2295520192 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3973370931 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3971968228 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1402703 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1257505437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.290450 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.406971 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433733980 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 146719588 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542274905 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18455051 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116321913 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58305735 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 954 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3085307728 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2035 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116321913 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456557347 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 93252503 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5104 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535232007 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56136563 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3003562340 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 560555 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1735251 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 50037437 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2245657329 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3895152131 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3893909248 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1242883 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 919317229 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 211 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 118384405 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 691487195 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 258255800 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68719353 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37210437 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2756294295 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 187 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2536632821 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3950694 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1007358741 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 432150244 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 158 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1298229870 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.953917 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.961710 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 869454366 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 190 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 189 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 120669951 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679225578 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255273844 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68130212 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37368209 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2722510883 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 144 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2508555980 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3078936 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 977267031 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 413974741 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 115 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1257505437 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.994867 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.973352 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 442263739 34.07% 34.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 208903385 16.09% 50.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 191557841 14.76% 64.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 152463661 11.74% 76.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 137672348 10.60% 87.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81203098 6.25% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 63863451 4.92% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15081593 1.16% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5220754 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 417762073 33.22% 33.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201459942 16.02% 49.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185268981 14.73% 63.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153261704 12.19% 76.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133079768 10.58% 86.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81048988 6.45% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65262511 5.19% 98.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15257874 1.21% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5103596 0.41% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1298229870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1257505437 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2156518 11.37% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12254343 64.62% 76.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4551680 24.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2150864 11.67% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11870466 64.42% 76.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4405017 23.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1658475044 65.38% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 273 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 652209568 25.71% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 225947593 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643219876 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 253 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 157 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 26 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641326950 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224008572 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2536632821 # Type of FU issued -system.cpu.iq.rate 1.875932 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18962541 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007475 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6392425036 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3762406457 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2431792022 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1983711 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1351957 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 870252 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2554620629 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 974733 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62690136 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2508555980 # Type of FU issued +system.cpu.iq.rate 1.912243 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18426347 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007345 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6294223850 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3698666551 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2412312770 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1898830 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1217307 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 851008 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2526043830 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 938497 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62613731 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 246891532 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263108 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 106999 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 97527298 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234629915 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 264851 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107543 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94545342 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 177 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1449625 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 100 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1452143 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 122054095 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 42236040 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1169448 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2901607263 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 18449890 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 691487195 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 258255800 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 187 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 295034 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19978 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 106999 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13433299 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8961049 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22394348 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2485079596 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 634549945 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 51553225 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116321913 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 41870148 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1143259 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2864507060 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8845706 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679225578 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255273844 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 144 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 295805 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17199 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107543 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10354551 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8556122 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18910673 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2461271813 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 624989902 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47284167 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 145312781 # number of nop insts executed -system.cpu.iew.exec_refs 853832523 # number of memory reference insts executed -system.cpu.iew.exec_branches 304694140 # Number of branches executed -system.cpu.iew.exec_stores 219282578 # Number of stores executed -system.cpu.iew.exec_rate 1.837806 # Inst execution rate -system.cpu.iew.wb_sent 2461943508 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2432662274 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1394848463 # num instructions producing a value -system.cpu.iew.wb_consumers 1766930878 # num instructions consuming a value +system.cpu.iew.exec_nop 141996033 # number of nop insts executed +system.cpu.iew.exec_refs 844381512 # number of memory reference insts executed +system.cpu.iew.exec_branches 300766985 # Number of branches executed +system.cpu.iew.exec_stores 219391610 # Number of stores executed +system.cpu.iew.exec_rate 1.876199 # Inst execution rate +system.cpu.iew.wb_sent 2441119325 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413163778 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388569148 # num instructions producing a value +system.cpu.iew.wb_consumers 1764314853 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.799042 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789419 # average fanout of values written-back +system.cpu.iew.wb_rate 1.839526 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.787030 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 860868467 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 823556826 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19198826 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1176175775 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.547201 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.484504 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16078403 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1141183524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.594643 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.519930 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 658247718 55.97% 55.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 175915600 14.96% 70.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90578875 7.70% 78.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53177308 4.52% 83.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35329719 3.00% 86.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23851430 2.03% 88.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 23326017 1.98% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23350140 1.99% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 92398968 7.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 628040121 55.03% 55.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174132211 15.26% 70.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86354537 7.57% 77.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53988637 4.73% 82.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34269513 3.00% 85.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24750272 2.17% 87.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22050678 1.93% 89.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22940990 2.01% 91.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94656565 8.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1176175775 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1141183524 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,317 +475,189 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 92398968 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94656565 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3678646200 # The number of ROB reads -system.cpu.rob.rob_writes 5483460601 # The number of ROB writes -system.cpu.timesIdled 829567 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53968858 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3604084711 # The number of ROB reads +system.cpu.rob.rob_writes 5403096067 # The number of ROB writes +system.cpu.timesIdled 804666 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 54334213 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.778897 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.778897 # CPI: Total CPI of All Threads -system.cpu.ipc 1.283867 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.283867 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3341460388 # number of integer regfile reads -system.cpu.int_regfile_writes 1950187380 # number of integer regfile writes -system.cpu.fp_regfile_reads 51936 # number of floating regfile reads -system.cpu.fp_regfile_writes 538 # number of floating regfile writes +system.cpu.cpi 0.755649 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.755649 # CPI: Total CPI of All Threads +system.cpu.ipc 1.323366 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.323366 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3316903206 # number of integer regfile reads +system.cpu.int_regfile_writes 1931453212 # number of integer regfile writes +system.cpu.fp_regfile_reads 30791 # number of floating regfile reads +system.cpu.fp_regfile_writes 509 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 771.801258 # Cycle average of tags in use -system.cpu.icache.total_refs 409163812 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 962 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 425326.207900 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 768.875728 # Cycle average of tags in use +system.cpu.icache.total_refs 390707378 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 406563.348595 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 771.801258 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.376856 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.376856 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 409163812 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 409163812 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 409163812 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 409163812 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 409163812 # number of overall hits -system.cpu.icache.overall_hits::total 409163812 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1504 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1504 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1504 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1504 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1504 # number of overall misses -system.cpu.icache.overall_misses::total 1504 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 80548999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 80548999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 80548999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 80548999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 80548999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 80548999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 409165316 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 409165316 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 409165316 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 409165316 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 409165316 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 409165316 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 768.875728 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.375428 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.375428 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 390707378 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 390707378 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 390707378 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 390707378 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 390707378 # number of overall hits +system.cpu.icache.overall_hits::total 390707378 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1472 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1472 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1472 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1472 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1472 # number of overall misses +system.cpu.icache.overall_misses::total 1472 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 78332000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 78332000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 78332000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 78332000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 78332000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 78332000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 390708850 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 390708850 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 390708850 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 390708850 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 390708850 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 390708850 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53556.515293 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53556.515293 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53556.515293 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53556.515293 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53556.515293 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53556.515293 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1029 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53214.673913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53214.673913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53214.673913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53214.673913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53214.673913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53214.673913 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 147 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 542 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 542 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 542 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 542 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 542 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 542 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 962 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 962 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 962 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57069999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 57069999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57069999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 57069999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57069999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 57069999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 511 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 511 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 511 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 511 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 511 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 961 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 961 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 961 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56098500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 56098500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56098500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 56098500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56098500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 56098500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59324.323285 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59324.323285 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59324.323285 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59324.323285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59324.323285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59324.323285 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58375.130073 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58375.130073 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58375.130073 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 58375.130073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58375.130073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 58375.130073 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9177397 # number of replacements -system.cpu.dcache.tagsinuse 4086.580271 # Cycle average of tags in use -system.cpu.dcache.total_refs 703801568 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9181493 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.654371 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5761373000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.580271 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997700 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997700 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 548148518 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 548148518 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155653046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155653046 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 703801564 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 703801564 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 703801564 # number of overall hits -system.cpu.dcache.overall_hits::total 703801564 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11295128 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11295128 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5075456 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5075456 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16370584 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16370584 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16370584 # number of overall misses -system.cpu.dcache.overall_misses::total 16370584 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 280321207500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 280321207500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 216815235389 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 216815235389 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 51500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 51500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 497136442889 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 497136442889 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 497136442889 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 497136442889 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 559443646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 559443646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 720172148 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 720172148 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 42150717127 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 42150717127 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43023532 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107448508053 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 107491531585 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43023532 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107448508053 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 107491531585 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163141 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163251 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411497 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411497 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163144 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163255 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411546 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411546 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214094 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214111 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54640.642369 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54636.283063 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45728.683992 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54640.642369 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54636.283063 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214193 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44769.544225 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54853.793252 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54845.658868 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54375.954146 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54375.954146 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44769.544225 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54665.345278 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54660.509418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44769.544225 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54665.345278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54660.509418 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9176047 # number of replacements +system.cpu.dcache.tagsinuse 4087.418525 # Cycle average of tags in use +system.cpu.dcache.total_refs 694335392 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180143 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.634485 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5062814000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.418525 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997905 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997905 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538685115 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538685115 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155650275 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155650275 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 694335390 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694335390 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694335390 # number of overall hits +system.cpu.dcache.overall_hits::total 694335390 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11273608 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11273608 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5078227 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5078227 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 16351835 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16351835 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 497066209033 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 549958723 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 549958723 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710687225 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710687225 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710687225 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710687225 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020499 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020499 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031595 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031595 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023008 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023008 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023008 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023008 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24839.581348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24839.581348 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42738.244280 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42738.244280 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30398.191337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30398.191337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30398.191337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30398.191337 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10428893 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5642690 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 733632 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.215428 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 86.632020 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3724933 # number of writebacks +system.cpu.dcache.writebacks::total 3724933 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3977017 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3977017 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3194676 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3194676 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7171693 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7171693 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7171693 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7171693 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296591 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296591 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883551 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883551 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 149546401000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 149546401000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65349746897 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 65349746897 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 46500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 46500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214896147897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 214896147897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214896147897 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 214896147897 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20495.379418 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20495.379418 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34694.970774 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34694.970774 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 46500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 46500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23408.804341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23408.804341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23408.804341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23408.804341 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |