summaryrefslogtreecommitdiff
path: root/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
diff options
context:
space:
mode:
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt')
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt18
1 files changed, 11 insertions, 7 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index 5f8a25a7f..9f7e15391 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu
sim_ticks 913189263000 # Number of ticks simulated
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1729437 # Simulator instruction rate (inst/s)
-host_op_rate 1729437 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 867853739 # Simulator tick rate (ticks/s)
-host_mem_usage 243124 # Number of bytes of host memory used
-host_seconds 1052.24 # Real time elapsed on the host
+host_inst_rate 3052391 # Simulator instruction rate (inst/s)
+host_op_rate 3052390 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1531729085 # Simulator tick rate (ticks/s)
+host_mem_usage 242484 # Number of bytes of host memory used
+host_seconds 596.18 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -103,7 +103,9 @@ system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Cl
system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
+system.cpu.op_class::FloatMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction
+system.cpu.op_class::FloatMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction
@@ -125,8 +127,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction
-system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction
-system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 449492662 24.61% 91.11% # Class of executed instruction
+system.cpu.op_class::MemWrite 162429751 8.89% 100.00% # Class of executed instruction
+system.cpu.op_class::FloatMemRead 79 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::FloatMemWrite 55 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1826378509 # Class of executed instruction