diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt | 518 |
1 files changed, 262 insertions, 256 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 6bd6eda32..622e92943 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.636720 # Number of seconds simulated -sim_ticks 2636719559500 # Number of ticks simulated -final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.639614 # Number of seconds simulated +sim_ticks 2639613874500 # Number of ticks simulated +final_tick 2639613874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1223384 # Simulator instruction rate (inst/s) -host_op_rate 1223384 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1772587765 # Simulator tick rate (ticks/s) -host_mem_usage 249508 # Number of bytes of host memory used -host_seconds 1487.50 # Real time elapsed on the host +host_inst_rate 1111155 # Simulator instruction rate (inst/s) +host_op_rate 1111155 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1611744129 # Simulator tick rate (ticks/s) +host_mem_usage 254908 # Number of bytes of host memory used +host_seconds 1637.74 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory -system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126106432 # Number of bytes read from this memory +system.physmem.bytes_read::total 126157760 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65405568 # Number of bytes written to this memory -system.physmem.bytes_written::total 65405568 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 66087296 # Number of bytes written to this memory +system.physmem.bytes_written::total 66087296 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951440 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47366494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47385960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24805660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24805660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24805660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 1970413 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1971215 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1032614 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1032614 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47774575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47794021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19445 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19445 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 25036729 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25036729 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 25036729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47774575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72830749 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -72,8 +72,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2636719559500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5273439119 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 2639613874500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5279227749 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -92,7 +92,7 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5273439119 # Number of busy cycles +system.cpu.num_busy_cycles 5279227749 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched @@ -131,26 +131,26 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4079.303630 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41036287500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.293901 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995921 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995921 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 41048093500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.303630 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995924 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1191 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2646 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -167,14 +167,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151181633000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151181633000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62898029000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62898029000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 214079662000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 214079662000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 214079662000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 214079662000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 152711735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 152711735000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64261460000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64261460000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 216973195000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 216973195000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 216973195000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 216973195000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -191,22 +191,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20932.285660 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20932.285660 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33291.358266 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33291.358266 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23494.942017 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23494.942017 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21144.140311 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21144.140311 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34013.009972 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34013.009972 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23812.503196 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23812.503196 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3679426 # number of writebacks -system.cpu.dcache.writebacks::total 3679426 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3664823 # number of writebacks +system.cpu.dcache.writebacks::total 3664823 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses @@ -215,14 +215,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143959219000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 143959219000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61008709000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61008709000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204967928000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 204967928000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204967928000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 204967928000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145489321000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 145489321000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62372140000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 62372140000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207861461000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 207861461000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207861461000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 207861461000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -231,24 +231,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19932.285660 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19932.285660 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32291.358266 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32291.358266 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20144.140311 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20144.140311 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33013.009972 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33013.009972 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 612.633318 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.605858 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.299124 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.299124 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 612.633318 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.299137 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.299137 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id @@ -256,7 +256,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 730 system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -269,12 +269,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 49759500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 49759500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 49759500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 49759500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 49759500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 49759500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50541500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50541500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50541500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50541500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50541500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50541500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -287,12 +287,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62044.264339 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62044.264339 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62044.264339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62044.264339 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63019.326683 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63019.326683 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63019.326683 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63019.326683 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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number of writebacks -system.cpu.l2cache.writebacks::total 1021962 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1032614 # number of writebacks +system.cpu.l2cache.writebacks::total 1032614 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782385 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782385 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 794006 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 794006 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 802 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1169055 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1169055 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176407 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176407 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1951440 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1952242 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1970413 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1971215 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1951440 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1952242 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38728061500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38728061500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39726500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39726500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57874778500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57874778500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39726500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96602840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 96642566500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39726500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96602840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 96642566500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1970413 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1971215 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40097303000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40097303000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40509000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40509000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59408556500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59408556500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40509000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99505859500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 99546368500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40509000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99505859500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 99546368500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414109 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414109 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420260 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420260 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161865 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161865 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162883 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162883 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214237 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216319 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214237 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.005113 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.005113 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49534.289277 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49534.289277 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.607948 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.607948 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.216319 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50509.975062 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50509.975062 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.002550 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.002550 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1292 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1292 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4697437 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6348968 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution @@ -504,53 +504,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818685632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919525 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65405568 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11032061 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000102 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010084 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 817699648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 817751040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1938767 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66087296 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11051303 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000117 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010812 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11030939 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11050011 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1292 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11032061 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12789514500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11051303 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12774911500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1169857 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution -system.membus.trans_dist::CleanEvict 896683 # Transaction distribution -system.membus.trans_dist::ReadExReq 782385 # Transaction distribution -system.membus.trans_dist::ReadExResp 782385 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1169857 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5823129 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5823129 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 3908932 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1937717 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1177209 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1032614 # Transaction distribution +system.membus.trans_dist::CleanEvict 905103 # Transaction distribution +system.membus.trans_dist::ReadExReq 794006 # Transaction distribution +system.membus.trans_dist::ReadExResp 794006 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1177209 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5880147 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5880147 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192245056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192245056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3870887 # Request fanout histogram +system.membus.snoop_fanout::samples 1971215 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3870887 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1971215 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3870887 # Request fanout histogram -system.membus.reqLayer0.occupancy 7958742500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1971215 # Request fanout histogram +system.membus.reqLayer0.occupancy 8039396000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9761210000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9856075000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |