diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64')
9 files changed, 1027 insertions, 1027 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 1fcd4f24c..4a4e79f41 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index 0482efbeb..74ab835bf 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:44:37 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:25:40 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1009998808500 because target called exit() +Exiting @ tick 991340143500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 0ddfc2b1c..35d38838f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.009999 # Number of seconds simulated -sim_ticks 1009998808500 # Number of ticks simulated -final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.991340 # Number of seconds simulated +sim_ticks 991340143500 # Number of ticks simulated +final_tick 991340143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98665 # Simulator instruction rate (inst/s) -host_op_rate 98665 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54760444 # Simulator tick rate (ticks/s) -host_mem_usage 215204 # Number of bytes of host memory used -host_seconds 18443.95 # Real time elapsed on the host +host_inst_rate 147354 # Simulator instruction rate (inst/s) +host_op_rate 147354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 80272080 # Simulator tick rate (ticks/s) +host_mem_usage 218972 # Number of bytes of host memory used +host_seconds 12349.75 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 172563072 # Number of bytes read from this memory -system.physmem.bytes_read::total 172618048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137579712 # Number of bytes read from this memory +system.physmem.bytes_read::total 137634688 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74938304 # Number of bytes written to this memory -system.physmem.bytes_written::total 74938304 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory +system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2696298 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2697157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1170911 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1170911 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 170854728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 170909160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 74196428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 74196428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 74196428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 170854728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 245105588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 2149683 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2150542 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 138781540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138836996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 67691285 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 67691285 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 67691285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 138781540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 206528281 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444614444 # DTB read hits +system.cpu.dtb.read_hits 444614343 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449511522 # DTB read accesses -system.cpu.dtb.write_hits 160920906 # DTB write hits +system.cpu.dtb.read_accesses 449511421 # DTB read accesses +system.cpu.dtb.write_hits 160920087 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162622210 # DTB write accesses -system.cpu.dtb.data_hits 605535350 # DTB hits +system.cpu.dtb.write_accesses 162621391 # DTB write accesses +system.cpu.dtb.data_hits 605534430 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612133732 # DTB accesses -system.cpu.itb.fetch_hits 231980230 # ITB hits +system.cpu.dtb.data_accesses 612132812 # DTB accesses +system.cpu.itb.fetch_hits 232194533 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231980252 # ITB accesses +system.cpu.itb.fetch_accesses 232194555 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2019997618 # number of cpu cycles simulated +system.cpu.numCycles 1982680288 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328891112 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253883187 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140042357 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 232477361 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138151285 # Number of BTB hits +system.cpu.branch_predictor.lookups 328915928 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253819011 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140072488 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 231593889 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138169193 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.425694 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175108073 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153783039 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669728742 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.660120 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175201939 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153713989 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669764044 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045931359 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3045966661 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651109695 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617989652 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121368305 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12075594 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133443899 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81756170 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.009227 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139611303 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651015392 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617989806 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121318277 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12155753 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133474030 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81726039 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.023228 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139614733 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746428176 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746574278 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7533729 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 443112454 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576885164 # Number of cycles cpu stages are processed. -system.cpu.activity 78.063714 # Percentage of cycles cpu is active +system.cpu.timesIdled 7486032 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 405569141 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1577111147 # Number of cycles cpu stages are processed. +system.cpu.activity 79.544400 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.110023 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.089516 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.110023 # CPI: Total CPI of All Threads -system.cpu.ipc 0.900882 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.089516 # CPI: Total CPI of All Threads +system.cpu.ipc 0.917838 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.900882 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 829317091 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190680527 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.944650 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1087591326 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932406292 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.158782 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1046003601 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973994017 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.217582 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1610294122 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409703496 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.282375 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 997062989 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022934629 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.640388 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.917838 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 791779407 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190900881 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.065200 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1050371352 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932308936 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 47.022656 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1008674680 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 974005608 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.125702 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1572973951 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409706337 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.664266 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 959730175 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022950113 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.594305 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 666.311000 # Cycle average of tags in use -system.cpu.icache.total_refs 231979155 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 666.725255 # Cycle average of tags in use +system.cpu.icache.total_refs 232193463 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270057.223516 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270306.708964 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 666.311000 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325347 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325347 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231979155 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231979155 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231979155 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231979155 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231979155 # number of overall hits -system.cpu.icache.overall_hits::total 231979155 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses -system.cpu.icache.overall_misses::total 1072 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58539000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58539000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58539000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58539000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58539000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58539000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231980227 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231980227 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231980227 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231980227 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231980227 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231980227 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 666.725255 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325549 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325549 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232193463 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232193463 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232193463 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232193463 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232193463 # number of overall hits +system.cpu.icache.overall_hits::total 232193463 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1067 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1067 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1067 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1067 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1067 # number of overall misses +system.cpu.icache.overall_misses::total 1067 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58495000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58495000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58495000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58495000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58495000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58495000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232194530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232194530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232194530 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232194530 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232194530 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232194530 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54607.276119 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54607.276119 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54607.276119 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54607.276119 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54821.930647 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54821.930647 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54821.930647 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54821.930647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54821.930647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54821.930647 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 125500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 85000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 31375 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 28333.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 213 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 213 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 213 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 208 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 208 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 208 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45935000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45935000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45935000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53467.986030 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53467.986030 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53467.986030 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53467.986030 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53474.970896 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53474.970896 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53474.970896 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53474.970896 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53474.970896 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53474.970896 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107352 # number of replacements -system.cpu.dcache.tagsinuse 4082.536815 # Cycle average of tags in use -system.cpu.dcache.total_refs 595069970 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310143 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12672189000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.536815 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996713 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996713 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271423 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271423 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157798547 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157798547 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595069970 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595069970 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595069970 # number of overall hits -system.cpu.dcache.overall_hits::total 595069970 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324240 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324240 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2929955 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2929955 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10254195 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10254195 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10254195 # number of overall misses -system.cpu.dcache.overall_misses::total 10254195 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 180897499500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 180897499500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110294932000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110294932000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 291192431500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 291192431500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 291192431500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 291192431500 # number of overall miss cycles +system.cpu.dcache.replacements 9107366 # number of replacements +system.cpu.dcache.tagsinuse 4082.290547 # Cycle average of tags in use +system.cpu.dcache.total_refs 595076211 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111462 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.310727 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12667784000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.290547 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996653 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996653 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437271439 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271439 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157804772 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157804772 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595076211 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595076211 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595076211 # number of overall hits +system.cpu.dcache.overall_hits::total 595076211 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7324224 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7324224 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2923730 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2923730 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10247954 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10247954 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10247954 # number of overall misses +system.cpu.dcache.overall_misses::total 10247954 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 162150578000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 162150578000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 105068682500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 105068682500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 267219260500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 267219260500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 267219260500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 267219260500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -262,54 +262,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018229 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.018229 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016940 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016940 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016940 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24698.466940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24698.466940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.899650 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37643.899650 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28397.395554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28397.395554 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11000000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8092150500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2762 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 209020 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3982.621289 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 38714.718687 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018190 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018190 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016930 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016930 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016930 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016930 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22138.943047 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22138.943047 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35936.520301 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35936.520301 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26075.376656 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26075.376656 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26075.376656 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26075.376656 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10790500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7928721000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2625 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 208163 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4110.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 38089.002368 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3058572 # number of writebacks -system.cpu.dcache.writebacks::total 3058572 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101958 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101958 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040789 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1040789 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1142747 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1142747 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1142747 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1142747 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889166 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889166 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156091594000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 156091594000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191446500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191446500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215283040500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215283040500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215283040500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215283040500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3389687 # number of writebacks +system.cpu.dcache.writebacks::total 3389687 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101944 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101944 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1034548 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1034548 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1136492 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1136492 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1136492 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1136492 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111462 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111462 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111462 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111462 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137265020500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 137265020500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54890953000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 54890953000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192155973500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 192155973500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 192155973500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 192155973500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -318,95 +318,95 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # 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average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.773869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.773869 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29055.407579 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29055.407579 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21089.477572 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21089.477572 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21089.477572 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21089.477572 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2686301 # 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mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.295991 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.279395 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.540678 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.597095 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.619831 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40112.619831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.861467 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40024.167616 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.241229 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40086.156385 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40086.156385 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.861467 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40046.914592 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40046.952117 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.861467 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40046.914592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40046.952117 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index b6ae8cce3..b3f63cedd 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 3e17983a4..41442f622 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:48:46 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:26:23 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 614317285000 because target called exit() +Exiting @ tick 607216877500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index ad65e54b6..66e8bd283 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.614317 # Number of seconds simulated -sim_ticks 614317285000 # Number of ticks simulated -final_tick 614317285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.607217 # Number of seconds simulated +sim_ticks 607216877500 # Number of ticks simulated +final_tick 607216877500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134863 # Simulator instruction rate (inst/s) -host_op_rate 134863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47722573 # Simulator tick rate (ticks/s) -host_mem_usage 216172 # Number of bytes of host memory used -host_seconds 12872.68 # Real time elapsed on the host +host_inst_rate 209626 # Simulator instruction rate (inst/s) +host_op_rate 209626 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73321119 # Simulator tick rate (ticks/s) +host_mem_usage 219996 # Number of bytes of host memory used +host_seconds 8281.61 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 62784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 173186944 # Number of bytes read from this memory -system.physmem.bytes_read::total 173249728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75020608 # Number of bytes written to this memory -system.physmem.bytes_written::total 75020608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 981 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2706046 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2707027 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1172197 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1172197 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 102201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 281917745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 282019947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 102201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 102201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122120295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122120295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122120295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 102201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 281917745 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 404140242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138164352 # Number of bytes read from this memory +system.physmem.bytes_read::total 138226304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67205952 # Number of bytes written to this memory +system.physmem.bytes_written::total 67205952 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2158818 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2159786 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050093 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050093 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 102026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 227537075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 227639101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 102026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 102026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 110678663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 110678663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 110678663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 102026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 227537075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 338317764 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613430411 # DTB read hits -system.cpu.dtb.read_misses 10984160 # DTB read misses +system.cpu.dtb.read_hits 612238035 # DTB read hits +system.cpu.dtb.read_misses 10898868 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 624414571 # DTB read accesses -system.cpu.dtb.write_hits 208466528 # DTB write hits -system.cpu.dtb.write_misses 6835381 # DTB write misses +system.cpu.dtb.read_accesses 623136903 # DTB read accesses +system.cpu.dtb.write_hits 208056215 # DTB write hits +system.cpu.dtb.write_misses 6766994 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 215301909 # DTB write accesses -system.cpu.dtb.data_hits 821896939 # DTB hits -system.cpu.dtb.data_misses 17819541 # DTB misses +system.cpu.dtb.write_accesses 214823209 # DTB write accesses +system.cpu.dtb.data_hits 820294250 # DTB hits +system.cpu.dtb.data_misses 17665862 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 839716480 # DTB accesses -system.cpu.itb.fetch_hits 401793450 # ITB hits -system.cpu.itb.fetch_misses 51 # ITB misses +system.cpu.dtb.data_accesses 837960112 # DTB accesses +system.cpu.itb.fetch_hits 401011528 # ITB hits +system.cpu.itb.fetch_misses 57 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 401793501 # ITB accesses +system.cpu.itb.fetch_accesses 401011585 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,146 +67,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1228634571 # number of cpu cycles simulated +system.cpu.numCycles 1214433756 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 381761173 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 293769294 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18987814 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 267293652 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 262906896 # Number of BTB hits +system.cpu.BPredUnit.lookups 380951023 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 293099658 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18933784 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 266477220 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 262392566 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25187123 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6338 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 413237757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3162516337 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381761173 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 288094019 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 577364277 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 136217023 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 121997880 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 25151704 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6168 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 412376649 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3157323952 # Number of instructions fetch has processed +system.cpu.fetch.Branches 380951023 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 287544270 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 576306152 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 134891835 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 111419989 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1099 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 401793450 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10461001 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1223060627 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.585740 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.163188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1063 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 401011528 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10506825 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1209281794 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.610908 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.168401 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 645696350 52.79% 52.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43491890 3.56% 56.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22343235 1.83% 58.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40947227 3.35% 61.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127434510 10.42% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63845944 5.22% 77.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40777509 3.33% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30328214 2.48% 82.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 208195748 17.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 632975642 52.34% 52.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43351030 3.58% 55.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22268396 1.84% 57.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40872577 3.38% 61.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127179039 10.52% 71.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63789232 5.27% 76.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40665333 3.36% 80.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30280275 2.50% 82.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 207900270 17.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1223060627 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310720 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.574009 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 442798352 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 107558051 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 546235232 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16010373 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 110458619 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60401844 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1104 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3083471433 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2212 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 110458619 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 464144259 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 59142722 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6290 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 539650759 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49657978 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3001214428 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 543640 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1796675 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 45123611 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2245055787 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3876991628 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3875592361 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1399267 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1209281794 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.313686 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.599832 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 441212287 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97730865 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 545630156 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15531465 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 109177021 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60290905 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1025 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3078047382 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2151 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 109177021 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 462067522 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 51929068 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5163 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 539154184 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46948836 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2995870549 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 446955 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1708785 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42808765 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2241183009 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3870137990 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3868740839 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1397151 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 868852824 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 246 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 246 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105587598 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 677972013 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 251679590 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 61268278 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 33927488 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2695905085 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 208 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2494910980 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3371495 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 947658243 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 400911726 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1223060627 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.039892 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.968690 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 864980046 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 207 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 206 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 100505126 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 676579077 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 251278116 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 61563067 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34698773 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2690247704 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 183 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2489728191 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3267337 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 942739143 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 400071480 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 154 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1209281794 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.058849 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971213 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 388423198 31.76% 31.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 198296660 16.21% 47.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 183821950 15.03% 63.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153332369 12.54% 75.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 135876340 11.11% 86.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79653803 6.51% 93.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 63718799 5.21% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14613920 1.19% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5323588 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 378679312 31.31% 31.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 195809975 16.19% 47.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 182681515 15.11% 62.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 152412696 12.60% 75.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 135959135 11.24% 86.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80206603 6.63% 93.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 63601344 5.26% 98.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14610233 1.21% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5320981 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1223060627 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1209281794 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2019639 10.76% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12227310 65.14% 75.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4524424 24.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1977743 10.56% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12229984 65.27% 75.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4528924 24.17% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1630534588 65.35% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1627060855 65.35% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 100 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 292 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 176 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 286 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 14 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 171 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued @@ -228,86 +228,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 642000765 25.73% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 222374992 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 640749326 25.74% 91.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 221917384 8.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2494910980 # Type of FU issued -system.cpu.iq.rate 2.030637 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18771373 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007524 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6233033546 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3642313752 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2391820907 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1991909 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1355027 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 871735 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2512703438 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 978915 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57347014 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2489728191 # Type of FU issued +system.cpu.iq.rate 2.050114 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18736651 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007526 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6208757898 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3631737993 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2386612184 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1984266 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1351861 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 870224 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2507489711 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 975131 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57077193 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 233376350 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 247116 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107150 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 90951088 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 231983414 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 247523 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 104727 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 90549614 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 227 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162717 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 172 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 177103 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 110458619 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22362549 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1121439 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2838563958 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17898504 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 677972013 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 251679590 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 208 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 216005 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15651 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107150 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13325619 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8884381 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22210000 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2442758638 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 624415478 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 52152342 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 109177021 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 19521566 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 973961 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2832586299 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17875212 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 676579077 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 251278116 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 183 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 178484 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13307 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 104727 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13292243 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8865054 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22157297 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2437364251 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 623138442 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 52363940 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142658665 # number of nop insts executed -system.cpu.iew.exec_refs 839717432 # number of memory reference insts executed -system.cpu.iew.exec_branches 299305457 # Number of branches executed -system.cpu.iew.exec_stores 215301954 # Number of stores executed -system.cpu.iew.exec_rate 1.988190 # Inst execution rate -system.cpu.iew.wb_sent 2421432535 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2392692642 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1370537618 # num instructions producing a value -system.cpu.iew.wb_consumers 1736169101 # num instructions consuming a value +system.cpu.iew.exec_nop 142338412 # number of nop insts executed +system.cpu.iew.exec_refs 837961692 # number of memory reference insts executed +system.cpu.iew.exec_branches 298501873 # Number of branches executed +system.cpu.iew.exec_stores 214823250 # Number of stores executed +system.cpu.iew.exec_rate 2.006996 # Inst execution rate +system.cpu.iew.wb_sent 2416135407 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2387482408 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1367770503 # num instructions producing a value +system.cpu.iew.wb_consumers 1732591741 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.947440 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789403 # average fanout of values written-back +system.cpu.iew.wb_rate 1.965922 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789436 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitCommittedOps 1819780126 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 782630603 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 773736355 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18986848 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1112602008 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.635607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.507788 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 18932893 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1100104773 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.654188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.513944 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 589258835 52.96% 52.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 179628091 16.14% 69.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90469983 8.13% 77.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53793341 4.83% 82.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36407733 3.27% 85.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27937238 2.51% 87.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22627047 2.03% 89.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23085278 2.07% 91.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 89394462 8.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 575678608 52.33% 52.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 180745216 16.43% 68.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90628498 8.24% 77.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53598095 4.87% 81.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36474012 3.32% 85.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28175112 2.56% 87.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22568883 2.05% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23092069 2.10% 91.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89144280 8.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1112602008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1100104773 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 89394462 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89144280 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3539839075 # The number of ROB reads -system.cpu.rob.rob_writes 5315403238 # The number of ROB writes -system.cpu.timesIdled 405378 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5573944 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3518697774 # The number of ROB reads +system.cpu.rob.rob_writes 5296336807 # The number of ROB writes +system.cpu.timesIdled 353272 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5151962 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.707721 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.707721 # CPI: Total CPI of All Threads -system.cpu.ipc 1.412986 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.412986 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3284485483 # number of integer regfile reads -system.cpu.int_regfile_writes 1919152187 # number of integer regfile writes -system.cpu.fp_regfile_reads 52475 # number of floating regfile reads -system.cpu.fp_regfile_writes 577 # number of floating regfile writes +system.cpu.cpi 0.699541 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.699541 # CPI: Total CPI of All Threads +system.cpu.ipc 1.429509 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.429509 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3277031179 # number of integer regfile reads +system.cpu.int_regfile_writes 1915203405 # number of integer regfile writes +system.cpu.fp_regfile_reads 51821 # number of floating regfile reads +system.cpu.fp_regfile_writes 555 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 800.240430 # Cycle average of tags in use -system.cpu.icache.total_refs 401791975 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 981 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 409573.878695 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 769.354058 # Cycle average of tags in use +system.cpu.icache.total_refs 401010025 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 968 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 414266.554752 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 800.240430 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.390742 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.390742 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 401791975 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 401791975 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 401791975 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 401791975 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 401791975 # number of overall hits -system.cpu.icache.overall_hits::total 401791975 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1475 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1475 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1475 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1475 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1475 # number of overall misses -system.cpu.icache.overall_misses::total 1475 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50482500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50482500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50482500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50482500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50482500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50482500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 401793450 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 401793450 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 401793450 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 401793450 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 401793450 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 401793450 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 769.354058 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.375661 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.375661 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 401010025 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 401010025 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 401010025 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 401010025 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 401010025 # number of overall hits +system.cpu.icache.overall_hits::total 401010025 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1503 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1503 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1503 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1503 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1503 # number of overall misses +system.cpu.icache.overall_misses::total 1503 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50592000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50592000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50592000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50592000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50592000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50592000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 401011528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 401011528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 401011528 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 401011528 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 401011528 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 401011528 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34225.423729 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34225.423729 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34225.423729 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34225.423729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34225.423729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34225.423729 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33660.678643 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33660.678643 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33660.678643 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33660.678643 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33660.678643 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33660.678643 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,301 +390,301 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 494 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 494 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 494 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 494 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 494 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 494 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34897000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 34897000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34897000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 34897000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34897000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34897000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 535 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 535 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 535 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 535 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 535 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 535 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 968 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34430500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 34430500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34430500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 34430500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34430500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34430500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35572.884811 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35572.884811 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35572.884811 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35572.884811 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35572.884811 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35572.884811 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35568.698347 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35568.698347 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35568.698347 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35568.698347 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35568.698347 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35568.698347 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176629 # number of replacements -system.cpu.dcache.tagsinuse 4086.046414 # Cycle average of tags in use -system.cpu.dcache.total_refs 701329771 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180725 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.391545 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5690384000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.046414 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997570 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997570 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 545515438 # 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number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 545002306 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155817990 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155817990 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 701329766 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 701329766 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 701329766 # number of overall hits -system.cpu.dcache.overall_hits::total 701329766 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10490369 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10490369 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4914174 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4914174 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 700820296 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 700820296 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 700820296 # number of overall hits +system.cpu.dcache.overall_hits::total 700820296 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10067033 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10067033 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4910512 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4910512 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15404543 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15404543 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15404543 # number of overall misses -system.cpu.dcache.overall_misses::total 15404543 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 175047680000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 175047680000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 137439947293 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 137439947293 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 47000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 47000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 312487627293 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 312487627293 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 312487627293 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 312487627293 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 556005807 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 556005807 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 14977545 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 14977545 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 14977545 # number of overall misses +system.cpu.dcache.overall_misses::total 14977545 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 147978050000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 147978050000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 133621980034 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 133621980034 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 49500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 49500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 281600030034 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 281600030034 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 281600030034 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 281600030034 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 555069339 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 555069339 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 716734309 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 716734309 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 716734309 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 716734309 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018867 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.018867 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030574 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.030574 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 715797841 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 715797841 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 715797841 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 715797841 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018137 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.018137 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030552 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030552 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.285714 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.285714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021493 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021493 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021493 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021493 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16686.513125 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16686.513125 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27968.066921 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27968.066921 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 23500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 23500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20285.420171 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20285.420171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20285.420171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20285.420171 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 118562765 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2148382500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 37554 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.020924 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.020924 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.020924 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.020924 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14699.271374 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14699.271374 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27211.415028 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27211.415028 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 24750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 24750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18801.481153 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18801.481153 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18801.481153 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18801.481153 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 94480762 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2148368000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 33098 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65117 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3157.127470 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 32992.651688 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2854.576168 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 32992.429012 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3083289 # number of writebacks -system.cpu.dcache.writebacks::total 3083289 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3193376 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3193376 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3030443 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3030443 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3416687 # number of writebacks +system.cpu.dcache.writebacks::total 3416687 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2770476 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2770476 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3026700 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3026700 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6223819 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6223819 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6223819 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6223819 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296993 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296993 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883731 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883731 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 5797176 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5797176 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5797176 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5797176 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296557 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296557 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883812 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883812 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180724 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180724 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180724 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180724 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 81348046000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 81348046000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38571686956 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 38571686956 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180369 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180369 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180369 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180369 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 66994974500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 66994974500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 35740755693 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 35740755693 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 119919732956 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 119919732956 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119919732956 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 119919732956 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013124 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013124 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 102735730193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 102735730193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 102735730193 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 102735730193 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013145 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013145 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.142857 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.142857 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012809 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012809 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012809 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012809 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11148.160071 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11148.160071 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20476.218184 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20476.218184 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012825 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012825 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012825 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012825 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9181.724271 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9181.724271 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 18972.570348 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 18972.570348 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13062.121566 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13062.121566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13062.121566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13062.121566 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11190.806186 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11190.806186 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11190.806186 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11190.806186 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2696556 # number of replacements -system.cpu.l2cache.tagsinuse 26644.209628 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7654288 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2721176 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.812860 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 130971058500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10796.913806 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 24.565729 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15822.730093 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.329496 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000750 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.482871 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.813117 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5472701 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5472701 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3083289 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3083289 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1001978 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1001978 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6474679 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6474679 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6474679 # number of overall hits -system.cpu.l2cache.overall_hits::total 6474679 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 981 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1824281 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1825262 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 881765 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 881765 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 981 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2706046 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2707027 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 981 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2706046 # number of overall misses -system.cpu.l2cache.overall_misses::total 2707027 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 33718000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62643106000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 62676824000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 30390866500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 30390866500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 33718000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 93033972500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 93067690500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 33718000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 93033972500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 93067690500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 981 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296982 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297963 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3083289 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3083289 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883743 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883743 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 981 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180725 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181706 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 981 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180725 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181706 # number of overall (read+write) accesses +system.cpu.l2cache.replacements 2143360 # number of replacements +system.cpu.l2cache.tagsinuse 30894.943744 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8540612 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2173057 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.930229 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 106966841000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14416.601656 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 30.433263 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16447.908826 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.439960 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000929 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.501950 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.942839 # 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average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10325.420376 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1172197 # number of writebacks -system.cpu.l2cache.writebacks::total 1172197 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 981 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1824281 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1825262 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 881765 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 881765 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 981 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 24429166000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30173000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67327024500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 67357197500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30173000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67327024500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 67357197500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250005 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250106 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.468092 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.468092 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188625 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188732 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415383 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415383 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.294828 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235156 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.235237 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.294828 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31160.040775 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31161.925712 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31161.924699 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31273.347207 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31273.347207 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31198.218562 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31198.218562 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235156 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.235237 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31170.454545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31168.792523 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31168.793691 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31218.982505 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31218.982505 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31170.454545 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31186.984961 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31186.977552 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31170.454545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31186.984961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31186.977552 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index f89f54e31..51c5aee6c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout index 267941dc1..80ad9dac8 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:46 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:33:25 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2663443716000 because target called exit() +Exiting @ tick 2640486390000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 3da64d83e..02104b02f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.663444 # Number of seconds simulated -sim_ticks 2663443716000 # Number of ticks simulated -final_tick 2663443716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.640486 # Number of seconds simulated +sim_ticks 2640486390000 # Number of ticks simulated +final_tick 2640486390000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1479188 # Simulator instruction rate (inst/s) -host_op_rate 1479188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2164950496 # Simulator tick rate (ticks/s) -host_mem_usage 214896 # Number of bytes of host memory used -host_seconds 1230.26 # Real time elapsed on the host +host_inst_rate 2162683 # Simulator instruction rate (inst/s) +host_op_rate 2162683 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3138035754 # Simulator tick rate (ticks/s) +host_mem_usage 218976 # Number of bytes of host memory used +host_seconds 841.45 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 172562880 # Number of bytes read from this memory -system.physmem.bytes_read::total 172614208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137580288 # Number of bytes read from this memory +system.physmem.bytes_read::total 137631616 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74939072 # Number of bytes written to this memory -system.physmem.bytes_written::total 74939072 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67105600 # Number of bytes written to this memory +system.physmem.bytes_written::total 67105600 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2696295 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2697097 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1170923 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1170923 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 64789385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64808656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 28136158 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 28136158 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 28136158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 64789385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 92944814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 2149692 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2150494 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048525 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048525 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52104146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52123585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19439 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19439 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 25414106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25414106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 25414106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52104146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77537690 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5326887432 # number of cpu cycles simulated +system.cpu.numCycles 5280972780 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5326887432 # Number of busy cycles +system.cpu.num_busy_cycles 5280972780 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 612.356766 # Cycle average of tags in use +system.cpu.icache.tagsinuse 612.518964 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 612.356766 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.299002 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.299002 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 612.518964 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.299082 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.299082 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -168,14 +168,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.363452 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4079.504248 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995973 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995973 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 40985601000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4079.363452 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995938 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995938 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 177010400000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177010400000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 63798266000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 63798266000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 240808666000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 240808666000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 240808666000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 240808666000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 158270882000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 158270882000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59580458000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59580458000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 217851340000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 217851340000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 217851340000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 217851340000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24508.481513 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24508.481513 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33767.845574 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33767.845574 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26428.412638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26428.412638 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21913.847918 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21913.847918 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31535.397921 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31535.397921 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23908.878376 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23908.878376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23908.878376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23908.878376 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3058802 # number of writebacks -system.cpu.dcache.writebacks::total 3058802 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3389919 # number of writebacks +system.cpu.dcache.writebacks::total 3389919 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155343158000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 155343158000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58130306000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 58130306000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213473464000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 213473464000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213473464000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 213473464000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136603640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 136603640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53912498000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53912498000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190516138000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 190516138000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190516138000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 190516138000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -258,65 +258,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21508.481513 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21508.481513 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30767.845574 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30767.845574 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23428.412638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23428.412638 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18913.847918 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18913.847918 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28535.397921 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.397921 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20908.878376 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20908.878376 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20908.878376 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20908.878376 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2686269 # number of replacements -system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7565346 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2710912 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.790701 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 582065656000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10727.578894 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 29.806952 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15282.701350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.327380 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000910 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.466391 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.794680 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5415352 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5415352 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3058802 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3058802 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1000087 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1000087 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6415439 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6415439 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6415439 # number of overall hits -system.cpu.l2cache.overall_hits::total 6415439 # number of overall hits +system.cpu.l2cache.replacements 2133721 # number of replacements +system.cpu.l2cache.tagsinuse 30166.064442 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8449191 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2163414 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.905490 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 498208075000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14372.212156 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 37.660543 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15756.191744 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.438605 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001149 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.480841 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.920595 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5861531 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5861531 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3389919 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3389919 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1100511 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1100511 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6962042 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6962042 # 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