diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64')
4 files changed, 57 insertions, 20 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index a81e64eec..e74f79662 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.208778 # Nu sim_ticks 1208777694500 # Number of ticks simulated final_tick 1208777694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239767 # Simulator instruction rate (inst/s) -host_op_rate 239767 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158688267 # Simulator tick rate (ticks/s) -host_mem_usage 248760 # Number of bytes of host memory used -host_seconds 7617.31 # Real time elapsed on the host +host_inst_rate 530685 # Simulator instruction rate (inst/s) +host_op_rate 530685 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 351230785 # Simulator tick rate (ticks/s) +host_mem_usage 297332 # Number of bytes of host memory used +host_seconds 3441.55 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124970112 # Number of bytes read from this memory system.physmem.bytes_read::total 125031424 # Number of bytes read from this memory @@ -293,6 +294,7 @@ system.physmem_1.memoryStateTime::REF 40363700000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 587184084000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 246097965 # Number of BP lookups system.cpu.branchPred.condPredicted 186356162 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15588061 # Number of conditional branches incorrect @@ -340,6 +342,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2417555389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -386,6 +389,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 1826378509 # Class of committed instruction system.cpu.tickCycles 2075251932 # Number of cycles that the object actually ticked system.cpu.idleCycles 342303457 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9121974 # number of replacements system.cpu.dcache.tags.tagsinuse 4080.726355 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 601538856 # Total number of references to valid blocks. @@ -403,6 +407,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1231275880 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1231275880 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 443056865 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 443056865 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158481991 # number of WriteReq hits @@ -499,6 +504,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194 system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3 # number of replacements system.cpu.icache.tags.tagsinuse 750.173547 # Cycle average of tags in use system.cpu.icache.tags.total_refs 597988654 # Total number of references to valid blocks. @@ -514,6 +520,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 874 system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1195980182 # Number of tag accesses system.cpu.icache.tags.data_accesses 1195980182 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 597988654 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 597988654 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 597988654 # number of demand (read+write) hits @@ -582,6 +589,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916 system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1920891 # number of replacements system.cpu.l2cache.tags.tagsinuse 30765.315888 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14409692 # Total number of references to valid blocks. @@ -604,6 +612,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15532 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149830076 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149830076 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3686603 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3686603 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits @@ -746,6 +755,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1268 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7239688 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4708742 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution @@ -778,6 +788,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1437000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13689105000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1173106 # Transaction distribution system.membus.trans_dist::WritebackDirty 1022139 # Transaction distribution system.membus.trans_dist::CleanEvict 897726 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 12610c445..6c06e7b34 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.669588 # Nu sim_ticks 669587683000 # Number of ticks simulated final_tick 669587683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147374 # Simulator instruction rate (inst/s) -host_op_rate 147374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56841738 # Simulator tick rate (ticks/s) -host_mem_usage 250296 # Number of bytes of host memory used -host_seconds 11779.86 # Real time elapsed on the host +host_inst_rate 268815 # Simulator instruction rate (inst/s) +host_op_rate 268815 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103681118 # Simulator tick rate (ticks/s) +host_mem_usage 297332 # Number of bytes of host memory used +host_seconds 6458.15 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125489536 # Number of bytes read from this memory system.physmem.bytes_read::total 125550272 # Number of bytes read from this memory @@ -308,6 +309,7 @@ system.physmem_1.memoryStateTime::REF 22358960000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 434911888500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 409349783 # Number of BP lookups system.cpu.branchPred.condPredicted 318159413 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15962959 # Number of conditional branches incorrect @@ -355,6 +357,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 669587683000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1339175367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -647,6 +650,7 @@ system.cpu.fp_regfile_reads 39668 # nu system.cpu.fp_regfile_writes 612 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9207202 # number of replacements system.cpu.dcache.tags.tagsinuse 4087.451175 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 712346624 # Total number of references to valid blocks. @@ -664,6 +668,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1470154674 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1470154674 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 556848448 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 556848448 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 155498172 # number of WriteReq hits @@ -780,6 +785,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 753.790798 # Cycle average of tags in use system.cpu.icache.tags.total_refs 420611422 # Total number of references to valid blocks. @@ -796,6 +802,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 882 system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 841226771 # Number of tag accesses system.cpu.icache.tags.data_accesses 841226771 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 420611422 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 420611422 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 420611422 # number of demand (read+write) hits @@ -870,6 +877,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782 system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1929018 # number of replacements system.cpu.l2cache.tags.tagsinuse 31408.626842 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14580161 # Total number of references to valid blocks. @@ -892,6 +900,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10488 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909027 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 151193610 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 151193610 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3727750 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3727750 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits @@ -1034,6 +1043,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1275 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1275 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7333042 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4752054 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution @@ -1066,6 +1076,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1423999 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13816947000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1189304 # Transaction distribution system.membus.trans_dist::WritebackDirty 1024304 # Transaction distribution system.membus.trans_dist::CleanEvict 903679 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 01aa62af6..1bae4420d 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1469307 # Simulator instruction rate (inst/s) -host_op_rate 1469307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 737317476 # Simulator tick rate (ticks/s) -host_mem_usage 238516 # Number of bytes of host memory used -host_seconds 1238.53 # Real time elapsed on the host +host_inst_rate 3169811 # Simulator instruction rate (inst/s) +host_op_rate 3169811 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1590652371 # Simulator tick rate (ticks/s) +host_mem_usage 285272 # Number of bytes of host memory used +host_seconds 574.10 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 906468506 # Wr system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 913189263000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1826378527 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution system.membus.trans_dist::WriteReq 160728502 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index e31f2fa37..d98d61e9c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.636720 # Nu sim_ticks 2636719559500 # Number of ticks simulated final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 874013 # Simulator instruction rate (inst/s) -host_op_rate 874013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1266376533 # Simulator tick rate (ticks/s) -host_mem_usage 247480 # Number of bytes of host memory used -host_seconds 2082.10 # Real time elapsed on the host +host_inst_rate 1821657 # Simulator instruction rate (inst/s) +host_op_rate 1821657 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2639438336 # Simulator tick rate (ticks/s) +host_mem_usage 295280 # Number of bytes of host memory used +host_seconds 998.97 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory @@ -36,6 +37,7 @@ system.physmem.bw_total::writebacks 24805660 # To system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,6 +72,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5273439119 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -128,6 +131,7 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9107638 # number of replacements system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. @@ -146,6 +150,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -234,6 +239,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. @@ -250,6 +256,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 730 system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -318,6 +325,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1919525 # number of replacements system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks. @@ -340,6 +348,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27302 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits @@ -482,6 +491,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution @@ -514,6 +524,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1203000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1169857 # Transaction distribution system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution system.membus.trans_dist::CleanEvict 896683 # Transaction distribution |