diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha')
4 files changed, 1100 insertions, 1005 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 49239c031..cd7da392b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -127,11 +134,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +149,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -162,17 +172,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -181,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -203,12 +218,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -218,6 +235,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -227,7 +245,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -241,11 +260,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -265,6 +286,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -276,17 +298,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index e22bfa1d8..864d4a591 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.009838 # Nu sim_ticks 1009838214500 # Number of ticks simulated final_tick 1009838214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108402 # Simulator instruction rate (inst/s) -host_op_rate 108402 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60154913 # Simulator tick rate (ticks/s) -host_mem_usage 256492 # Number of bytes of host memory used -host_seconds 16787.29 # Real time elapsed on the host +host_inst_rate 87394 # Simulator instruction rate (inst/s) +host_op_rate 87394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48496748 # Simulator tick rate (ticks/s) +host_mem_usage 275936 # Number of bytes of host memory used +host_seconds 20822.81 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -95,10 +95,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1018055 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1662262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 204907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1662258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 204908 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21384 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -128,27 +128,27 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 45504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 45757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 45756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45699 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 45701 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 45665 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 45697 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 45681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 45686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45671 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 45688 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 45723 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 45729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45986 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 46199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 46504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 46502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47567 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 47005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 48930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47073 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 1504 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 185 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see @@ -159,19 +159,19 @@ system.physmem.wrQLenPdf::28 1 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1862401 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 102.289945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.389421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 186.671108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1500565 80.57% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 201454 10.82% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 59784 3.21% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 29274 1.57% 96.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16603 0.89% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10401 0.56% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7224 0.39% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6892 0.37% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4048 0.22% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1862398 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 102.290110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.389553 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 186.671437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1500560 80.57% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 201450 10.82% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 59792 3.21% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 29273 1.57% 96.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16605 0.89% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10399 0.56% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7221 0.39% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6896 0.37% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4046 0.22% 98.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-641 3343 0.18% 98.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::704-705 3041 0.16% 98.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-769 2820 0.15% 99.09% # Bytes accessed per row activation @@ -180,10 +180,10 @@ system.physmem.bytesPerActivate::896-897 1539 0.08% 99.26% # By system.physmem.bytesPerActivate::960-961 1515 0.08% 99.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1025 1490 0.08% 99.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088-1089 1330 0.07% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1308 0.07% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 968 0.05% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1341 0.07% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 595 0.03% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1307 0.07% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 969 0.05% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1340 0.07% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 596 0.03% 99.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::1408-1409 2192 0.12% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::1472-1473 189 0.01% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536-1537 700 0.04% 99.88% # Bytes accessed per row activation @@ -283,15 +283,15 @@ system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 154 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1862401 # Bytes accessed per row activation -system.physmem.totQLat 23049370500 # Total ticks spent queuing -system.physmem.totMemAccLat 84969994250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::total 1862398 # Bytes accessed per row activation +system.physmem.totQLat 23048924250 # Total ticks spent queuing +system.physmem.totMemAccLat 84969451750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 9795680000 # Total ticks spent in databus transfers -system.physmem.totBankLat 52124943750 # Total ticks spent accessing banks -system.physmem.avgQLat 11765.07 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26606.09 # Average bank access latency per DRAM burst +system.physmem.totBankLat 52124847500 # Total ticks spent accessing banks +system.physmem.avgQLat 11764.84 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26606.04 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43371.16 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 43370.88 # Average memory access latency per DRAM burst system.physmem.avgRdBW 124.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 64.52 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 124.20 # Average system read bandwidth in MiByte/s @@ -302,8 +302,8 @@ system.physmem.busUtilRead 0.97 # Da system.physmem.busUtilWrite 0.50 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.08 # Average read queue length when enqueuing system.physmem.avgWrQLen 10.29 # Average write queue length when enqueuing -system.physmem.readRowHits 771404 # Number of row buffer hits during reads -system.physmem.writeRowHits 343365 # Number of row buffer hits during writes +system.physmem.readRowHits 771409 # Number of row buffer hits during reads +system.physmem.writeRowHits 343363 # Number of row buffer hits during writes system.physmem.readRowHitRate 39.37 # Row buffer hit rate for reads system.physmem.writeRowHitRate 33.73 # Row buffer hit rate for writes system.physmem.avgGap 339128.71 # Average gap between requests @@ -321,39 +321,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1 system.membus.tot_pkt_size::total 190575552 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 190575552 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11787413500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11785228500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 18365913000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18364778000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu.branchPred.lookups 326538195 # Number of BP lookups -system.cpu.branchPred.condPredicted 252572806 # Number of conditional branches predicted +system.cpu.branchPred.lookups 326538257 # Number of BP lookups +system.cpu.branchPred.condPredicted 252572868 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 138234365 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 220428693 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135446272 # Number of BTB hits +system.cpu.branchPred.BTBLookups 220428800 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135446379 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.446752 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.446771 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444831815 # DTB read hits +system.cpu.dtb.read_hits 444831817 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449728893 # DTB read accesses +system.cpu.dtb.read_accesses 449728895 # DTB read accesses system.cpu.dtb.write_hits 160846718 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 162548022 # DTB write accesses -system.cpu.dtb.data_hits 605678533 # DTB hits +system.cpu.dtb.data_hits 605678535 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612276915 # DTB accesses -system.cpu.itb.fetch_hits 231928866 # ITB hits +system.cpu.dtb.data_accesses 612276917 # DTB accesses +system.cpu.itb.fetch_hits 231928870 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231928888 # ITB accesses +system.cpu.itb.fetch_accesses 231928892 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -370,8 +370,8 @@ system.cpu.workload.num_syscalls 29 # Nu system.cpu.numCycles 2019676430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172263192 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154275003 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 172263299 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154274958 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 1667627607 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 3043830224 # Total Accesses (Read+Write) to the Int. Register File @@ -389,12 +389,12 @@ system.cpu.execution_unit.executions 1139356886 # Nu system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1742059065 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742060649 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7515569 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 447943127 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571733303 # Number of cycles cpu stages are processed. -system.cpu.activity 77.821045 # Percentage of cycles cpu is active +system.cpu.timesIdled 7515544 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 447943086 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571733344 # Number of cycles cpu stages are processed. +system.cpu.activity 77.821047 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -412,66 +412,66 @@ system.cpu.cpi_total 1.109846 # CP system.cpu.ipc 0.901026 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.901026 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 833031471 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186644959 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.754211 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1085876245 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933800185 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.235138 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1047285366 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972391064 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.idleCycles 833031386 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186645044 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.754216 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1085876271 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933800159 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.235137 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1047285367 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972391063 # Number of cycles 1+ instructions are processed. system.cpu.stage2.utilization 48.145884 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1610051905 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409624525 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.idleCycles 1610051904 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409624526 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 20.281691 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 998329603 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021346827 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.idleCycles 998329594 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021346836 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 50.569825 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 668.332859 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 231927727 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 231927731 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 269997.353900 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 269997.358556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 668.332859 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.326334 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.326334 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231927727 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231927727 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231927727 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231927727 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231927727 # number of overall hits -system.cpu.icache.overall_hits::total 231927727 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 231927731 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231927731 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231927731 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231927731 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231927731 # number of overall hits +system.cpu.icache.overall_hits::total 231927731 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses system.cpu.icache.overall_misses::total 1139 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82717000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82717000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82717000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82717000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82717000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82717000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231928866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231928866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231928866 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231928866 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231928866 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231928866 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 82716500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 82716500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 82716500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 82716500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 82716500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 82716500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231928870 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231928870 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231928870 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231928870 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231928870 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231928870 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.475856 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72622.475856 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.475856 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72622.475856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.475856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72622.475856 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.036874 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72622.036874 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.036874 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72622.036874 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.036874 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72622.036874 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -492,24 +492,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 859 system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65136750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 65136750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65136750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 65136750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65136750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 65136750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65136250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 65136250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65136250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 65136250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65136250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 65136250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75828.579744 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75828.579744 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75828.579744 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75828.579744 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75828.579744 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75828.579744 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75827.997672 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75827.997672 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75827.997672 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75827.997672 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75827.997672 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75827.997672 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 811573074 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7222683 # Transaction distribution @@ -529,17 +529,17 @@ system.cpu.toL2Bus.reqLayer0.occupancy 10096073000 # La system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1445250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13991720500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13991718500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.l2cache.tags.replacements 1926957 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30919.698652 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30919.698369 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8958682 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1956750 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.578348 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 67892812750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14931.952178 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 14931.951876 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.659960 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15953.086514 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15953.086532 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.455687 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.486850 # Average percentage of cache occupancy @@ -565,17 +565,17 @@ system.cpu.l2cache.demand_misses::total 1959688 # nu system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64273750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98167461500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 98231735250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71142206750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 71142206750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 64273750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 169309668250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 169373942000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 64273750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 169309668250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 169373942000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64273250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98166669000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98230942250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71141350250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 71141350250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 64273250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 169308019250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 169372292500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 64273250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 169308019250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 169372292500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7221824 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7222683 # number of ReadReq accesses(hits+misses) @@ -600,17 +600,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215060 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214986 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215060 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74823.923166 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83367.057654 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 83360.830055 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91056.663224 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91056.663224 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74823.923166 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86434.123780 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86429.034622 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74823.923166 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86434.123780 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86429.034622 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74823.341094 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83366.384636 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83360.157104 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91055.566968 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91055.566968 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74823.341094 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86433.281951 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86428.192906 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74823.341094 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86433.281951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86428.192906 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -632,17 +632,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1959688 system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53492750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83392423000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83445915750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61355655750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61355655750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53492750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144748078750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 144801571500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53492750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144748078750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 144801571500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53491750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83391618000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83445109750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61355946750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61355946750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53491750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144747564750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 144801056500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53491750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144747564750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 144801056500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses @@ -654,21 +654,21 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215060 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215060 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62273.282887 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70819.605905 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70813.375982 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78530.615477 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78530.615477 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62273.282887 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73895.209204 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73890.114906 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62273.282887 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73895.209204 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73890.114906 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62272.118743 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70818.922272 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70812.691999 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78530.987935 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78530.987935 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62272.118743 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73894.946802 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73889.852109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62272.118743 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73894.946802 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73889.852109 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 9107351 # number of replacements system.cpu.dcache.tags.tagsinuse 4082.357931 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 593283203 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 593283202 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9111447 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 65.114049 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 12709353000 # Cycle when the warmup percentage was hit. @@ -677,28 +677,28 @@ system.cpu.dcache.tags.occ_percent::cpu.data 0.996669 system.cpu.dcache.tags.occ_percent::total 0.996669 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437268777 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437268777 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156014426 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156014426 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593283203 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593283203 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593283203 # number of overall hits -system.cpu.dcache.overall_hits::total 593283203 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 156014425 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156014425 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593283202 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593283202 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593283202 # number of overall hits +system.cpu.dcache.overall_hits::total 593283202 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7326886 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7326886 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4714076 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4714076 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 12040962 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12040962 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12040962 # number of overall misses -system.cpu.dcache.overall_misses::total 12040962 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066802000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183066802000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 258282974250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 258282974250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 441349776250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 441349776250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 441349776250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 441349776250 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 4714077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4714077 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 12040963 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12040963 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12040963 # number of overall misses +system.cpu.dcache.overall_misses::total 12040963 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066004000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183066004000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 258278135000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 258278135000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 441344139000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 441344139000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 441344139000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 441344139000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -715,19 +715,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.019892 system.cpu.dcache.demand_miss_rate::total 0.019892 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.019892 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.019892 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.621723 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.621723 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54789.734881 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54789.734881 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36654.029491 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36654.029491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36654.029491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36654.029491 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12098438 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.512809 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.512809 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54788.696706 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54788.696706 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36653.558274 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36653.558274 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36653.558274 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36653.558274 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12098433 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 7855784 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 422645 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 422647 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 73423 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.625532 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.625385 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 106.993503 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -735,12 +735,12 @@ system.cpu.dcache.writebacks::writebacks 3693280 # nu system.cpu.dcache.writebacks::total 3693280 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104620 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 104620 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2824895 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2824895 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2929515 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2929515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2929515 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2929515 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2824896 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2824896 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2929516 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2929516 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2929516 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2929516 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222266 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222266 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889181 # number of WriteReq MSHR misses @@ -749,14 +749,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111447 system.cpu.dcache.demand_mshr_misses::total 9111447 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111447 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111447 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165960748500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 165960748500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84277565500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84277565500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250238314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 250238314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250238314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 250238314000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165959957500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 165959957500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84276720000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84276720000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250236677500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 250236677500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250236677500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 250236677500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -765,14 +765,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22979.041273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22979.041273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.635773 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.635773 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27464.168315 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27464.168315 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27464.168315 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27464.168315 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22978.931751 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22978.931751 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.188224 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.188224 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27463.988706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27463.988706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27463.988706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27463.988706 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 898bd1404..3e178e75c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index fbdbcc030..29e4de429 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.685488 # Number of seconds simulated -sim_ticks 685488076000 # Number of ticks simulated -final_tick 685488076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.685387 # Number of seconds simulated +sim_ticks 685386545000 # Number of ticks simulated +final_tick 685386545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134484 # Simulator instruction rate (inst/s) -host_op_rate 134484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53101916 # Simulator tick rate (ticks/s) -host_mem_usage 257516 # Number of bytes of host memory used -host_seconds 12908.91 # Real time elapsed on the host +host_inst_rate 111182 # Simulator instruction rate (inst/s) +host_op_rate 111182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43894428 # Simulator tick rate (ticks/s) +host_mem_usage 276060 # Number of bytes of host memory used +host_seconds 15614.43 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125793664 # Number of bytes read from this memory -system.physmem.bytes_read::total 125855616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65265536 # Number of bytes written to this memory -system.physmem.bytes_written::total 65265536 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965526 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966494 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019774 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019774 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 183509631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 183600008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 95210316 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 95210316 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 95210316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 183509631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 278810323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966494 # Number of read requests accepted -system.physmem.writeReqs 1019774 # Number of write requests accepted -system.physmem.readBursts 1966494 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1019774 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125820608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35008 # Total number of bytes read from write queue -system.physmem.bytesWritten 65264256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125855616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65265536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 547 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125792064 # Number of bytes read from this memory +system.physmem.bytes_read::total 125853824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65263104 # Number of bytes written to this memory +system.physmem.bytes_written::total 65263104 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965501 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966466 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019736 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019736 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 90110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 183534481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 183624591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90110 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90110 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95220871 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95220871 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95220871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 183534481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 278845462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966466 # Number of read requests accepted +system.physmem.writeReqs 1019736 # Number of write requests accepted +system.physmem.readBursts 1966466 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1019736 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125817344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 36480 # Total number of bytes read from write queue +system.physmem.bytesWritten 65263104 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125853824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65263104 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 570 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119024 # Per bank write bursts -system.physmem.perBankRdBursts::1 114431 # Per bank write bursts -system.physmem.perBankRdBursts::2 116551 # Per bank write bursts -system.physmem.perBankRdBursts::3 118044 # Per bank write bursts -system.physmem.perBankRdBursts::4 118169 # Per bank write bursts -system.physmem.perBankRdBursts::5 117821 # Per bank write bursts -system.physmem.perBankRdBursts::6 120193 # Per bank write bursts -system.physmem.perBankRdBursts::7 124929 # Per bank write bursts -system.physmem.perBankRdBursts::8 127563 # Per bank write bursts -system.physmem.perBankRdBursts::9 130460 # Per bank write bursts -system.physmem.perBankRdBursts::10 129120 # Per bank write bursts -system.physmem.perBankRdBursts::11 130791 # Per bank write bursts -system.physmem.perBankRdBursts::12 126621 # Per bank write bursts -system.physmem.perBankRdBursts::13 125625 # Per bank write bursts -system.physmem.perBankRdBursts::14 122955 # Per bank write bursts -system.physmem.perBankRdBursts::15 123650 # Per bank write bursts -system.physmem.perBankWrBursts::0 61294 # Per bank write bursts -system.physmem.perBankWrBursts::1 61576 # Per bank write bursts -system.physmem.perBankWrBursts::2 60653 # Per bank write bursts -system.physmem.perBankWrBursts::3 61320 # Per bank write bursts -system.physmem.perBankWrBursts::4 61767 # Per bank write bursts -system.physmem.perBankWrBursts::5 63184 # Per bank write bursts -system.physmem.perBankWrBursts::6 64210 # Per bank write bursts -system.physmem.perBankWrBursts::7 65704 # Per bank write bursts -system.physmem.perBankWrBursts::8 65475 # Per bank write bursts -system.physmem.perBankWrBursts::9 65876 # Per bank write bursts -system.physmem.perBankWrBursts::10 65422 # Per bank write bursts -system.physmem.perBankWrBursts::11 65733 # Per bank write bursts -system.physmem.perBankWrBursts::12 64307 # Per bank write bursts -system.physmem.perBankWrBursts::13 64297 # Per bank write bursts -system.physmem.perBankWrBursts::14 64633 # Per bank write bursts -system.physmem.perBankWrBursts::15 64303 # Per bank write bursts +system.physmem.perBankRdBursts::0 119017 # Per bank write bursts +system.physmem.perBankRdBursts::1 114428 # Per bank write bursts +system.physmem.perBankRdBursts::2 116569 # Per bank write bursts +system.physmem.perBankRdBursts::3 118023 # Per bank write bursts +system.physmem.perBankRdBursts::4 118127 # Per bank write bursts +system.physmem.perBankRdBursts::5 117816 # Per bank write bursts +system.physmem.perBankRdBursts::6 120202 # Per bank write bursts +system.physmem.perBankRdBursts::7 124913 # Per bank write bursts +system.physmem.perBankRdBursts::8 127544 # Per bank write bursts +system.physmem.perBankRdBursts::9 130446 # Per bank write bursts +system.physmem.perBankRdBursts::10 129104 # Per bank write bursts +system.physmem.perBankRdBursts::11 130773 # Per bank write bursts +system.physmem.perBankRdBursts::12 126663 # Per bank write bursts +system.physmem.perBankRdBursts::13 125636 # Per bank write bursts +system.physmem.perBankRdBursts::14 122981 # Per bank write bursts +system.physmem.perBankRdBursts::15 123654 # Per bank write bursts +system.physmem.perBankWrBursts::0 61274 # Per bank write bursts +system.physmem.perBankWrBursts::1 61571 # Per bank write bursts +system.physmem.perBankWrBursts::2 60654 # Per bank write bursts +system.physmem.perBankWrBursts::3 61312 # Per bank write bursts +system.physmem.perBankWrBursts::4 61747 # Per bank write bursts +system.physmem.perBankWrBursts::5 63190 # Per bank write bursts +system.physmem.perBankWrBursts::6 64213 # Per bank write bursts +system.physmem.perBankWrBursts::7 65700 # Per bank write bursts +system.physmem.perBankWrBursts::8 65483 # Per bank write bursts +system.physmem.perBankWrBursts::9 65878 # Per bank write bursts +system.physmem.perBankWrBursts::10 65419 # Per bank write bursts +system.physmem.perBankWrBursts::11 65720 # Per bank write bursts +system.physmem.perBankWrBursts::12 64327 # Per bank write bursts +system.physmem.perBankWrBursts::13 64305 # Per bank write bursts +system.physmem.perBankWrBursts::14 64649 # Per bank write bursts +system.physmem.perBankWrBursts::15 64294 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 685487953500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 685386422500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1966494 # Read request sizes (log2) +system.physmem.readPktSize::6 1966466 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1019774 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1645141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 231582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019736 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1645035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 231982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 68923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -127,235 +127,234 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 45698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 45666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 45696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 45650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 45681 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 45674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 46118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 46280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 49534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 48711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 45697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 45706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 46127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 46326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 49473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 48655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1822247 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 104.837037 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.099826 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 197.854977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1460763 80.16% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 186024 10.21% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 72307 3.97% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 32393 1.78% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16822 0.92% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10551 0.58% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6953 0.38% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6800 0.37% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3880 0.21% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3184 0.17% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2717 0.15% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2015 0.11% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1651 0.09% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1492 0.08% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1271 0.07% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1102 0.06% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 982 0.05% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1041 0.06% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 864 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 817 0.04% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 719 0.04% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2906 0.16% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 391 0.02% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 753 0.04% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 249 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 220 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 185 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 207 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 171 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 149 0.01% 99.85% # Bytes accessed per row activation +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1821867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 104.857955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.098310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 197.882118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1460616 80.17% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 186071 10.21% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 71892 3.95% 94.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 32365 1.78% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16766 0.92% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10653 0.58% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7007 0.38% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6870 0.38% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3886 0.21% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3166 0.17% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2723 0.15% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1980 0.11% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1594 0.09% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1502 0.08% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1242 0.07% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1240 0.07% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1003 0.06% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1017 0.06% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 831 0.05% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 807 0.04% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 751 0.04% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2873 0.16% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 389 0.02% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 742 0.04% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 289 0.02% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 237 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 196 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 198 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 161 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 147 0.01% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984-1985 132 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 171 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 381 0.02% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 117 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 95 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 87 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 78 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 78 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 61 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 165 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 370 0.02% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 134 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 101 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 83 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 73 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 67 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 51 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::2560-2561 72 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 41 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 45 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 36 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 35 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 29 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 23 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 49 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 40 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 35 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 42 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 34 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 27 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 45 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 24 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 26 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 27 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 27 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 22 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 20 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 15 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 30 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 11 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 17 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 14 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 16 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 14 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 21 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 10 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 22 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 8 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 11 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 23 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 10 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 16 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 21 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 18 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 18 0.00% 99.97% # Bytes accessed per row activation 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0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 16 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 7 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 13 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 12 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 85 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 29 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 32 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 23 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 19 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 28 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.95% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::5440-5441 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 26 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 4 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 11 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 22 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 13 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 7 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 17 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 89 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 28 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 125 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1822247 # Bytes accessed per row activation -system.physmem.totQLat 24360796250 # Total ticks spent queuing -system.physmem.totMemAccLat 84735751250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9829735000 # Total ticks spent in databus transfers -system.physmem.totBankLat 50545220000 # Total ticks spent accessing banks -system.physmem.avgQLat 12391.38 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 25710.37 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::7936-7937 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 123 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1821867 # Bytes accessed per row activation +system.physmem.totQLat 24443368500 # Total ticks spent queuing +system.physmem.totMemAccLat 84807426000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9829480000 # Total ticks spent in databus transfers +system.physmem.totBankLat 50534577500 # Total ticks spent accessing banks +system.physmem.avgQLat 12433.70 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 25705.62 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43101.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 183.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 95.21 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 183.60 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 95.21 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43139.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 183.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.22 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 183.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.22 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.18 # Data bus utilization in percentage system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.63 # Average write queue length when enqueuing -system.physmem.readRowHits 818889 # Number of row buffer hits during reads -system.physmem.writeRowHits 344565 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.65 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.79 # Row buffer hit rate for writes -system.physmem.avgGap 229546.70 # Average gap between requests -system.physmem.pageHitRate 38.97 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 7.09 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 278810323 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191305 # Transaction distribution -system.membus.trans_dist::ReadResp 1191305 # Transaction distribution -system.membus.trans_dist::Writeback 1019774 # Transaction distribution -system.membus.trans_dist::ReadExReq 775189 # Transaction distribution -system.membus.trans_dist::ReadExResp 775189 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4952762 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191121152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191121152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191121152 # Total data (bytes) +system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing +system.physmem.readRowHits 819101 # Number of row buffer hits during reads +system.physmem.writeRowHits 344664 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes +system.physmem.avgGap 229517.77 # Average gap between requests +system.physmem.pageHitRate 38.98 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 7.14 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 278845462 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191273 # Transaction distribution +system.membus.trans_dist::ReadResp 1191273 # Transaction distribution +system.membus.trans_dist::Writeback 1019736 # Transaction distribution +system.membus.trans_dist::ReadExReq 775193 # Transaction distribution +system.membus.trans_dist::ReadExResp 775193 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4952668 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191116928 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191116928 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191116928 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11874044250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11873404000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18494220250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18493738500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu.branchPred.lookups 381678235 # Number of BP lookups -system.cpu.branchPred.condPredicted 296637110 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16088915 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262749250 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259783318 # Number of BTB hits +system.cpu.branchPred.lookups 381642976 # Number of BP lookups +system.cpu.branchPred.condPredicted 296606399 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16082111 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262443817 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259723367 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.871193 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24705471 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3030 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.963416 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24699577 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3003 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613987676 # DTB read hits -system.cpu.dtb.read_misses 11260420 # DTB read misses +system.cpu.dtb.read_hits 613972689 # DTB read hits +system.cpu.dtb.read_misses 11257711 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625248096 # DTB read accesses -system.cpu.dtb.write_hits 212348403 # DTB write hits -system.cpu.dtb.write_misses 7134109 # DTB write misses +system.cpu.dtb.read_accesses 625230400 # DTB read accesses +system.cpu.dtb.write_hits 212364531 # DTB write hits +system.cpu.dtb.write_misses 7123508 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219482512 # DTB write accesses -system.cpu.dtb.data_hits 826336079 # DTB hits -system.cpu.dtb.data_misses 18394529 # DTB misses +system.cpu.dtb.write_accesses 219488039 # DTB write accesses +system.cpu.dtb.data_hits 826337220 # DTB hits +system.cpu.dtb.data_misses 18381219 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844730608 # DTB accesses -system.cpu.itb.fetch_hits 391118478 # ITB hits -system.cpu.itb.fetch_misses 44 # ITB misses +system.cpu.dtb.data_accesses 844718439 # DTB accesses +system.cpu.itb.fetch_hits 391054896 # ITB hits +system.cpu.itb.fetch_misses 42 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391118522 # ITB accesses +system.cpu.itb.fetch_accesses 391054938 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -369,138 +368,137 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1370976153 # number of cpu cycles simulated +system.cpu.numCycles 1370773091 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402585457 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3161328538 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381678235 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284488789 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574592396 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140681937 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 190961804 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1466 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 391118478 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8069239 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1284965558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.460244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.144346 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402523002 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3161115412 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381642976 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284422944 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574525052 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140645567 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 190952168 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1444 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 391054896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8064214 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1284797805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.460399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.144459 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 710373162 55.28% 55.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42677954 3.32% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21796461 1.70% 60.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39706509 3.09% 63.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129357441 10.07% 73.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61547596 4.79% 78.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38577258 3.00% 81.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28126573 2.19% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212802604 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 710272753 55.28% 55.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42667609 3.32% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21782496 1.70% 60.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39699327 3.09% 63.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129330544 10.07% 73.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61540269 4.79% 78.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38580495 3.00% 81.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28116157 2.19% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212808155 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1284965558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.278399 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.305896 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434593706 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 172173126 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542518914 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18856302 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116823510 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58351123 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 876 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3088655283 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2048 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116823510 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457554918 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116845929 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6766 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535622730 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 58111705 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3006575354 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 610156 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1852925 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51779132 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2247748999 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3899198212 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3899055356 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 142855 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1284797805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.278414 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.306082 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434521910 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 172167391 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542471492 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18841651 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116795361 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58349498 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 879 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3088463521 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116795361 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457475867 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116907635 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7798 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535572514 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 58038630 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3006337354 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 608843 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1808950 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51752219 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2247576032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3898866654 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3898722180 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 144473 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 871546036 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 162 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 160 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123661161 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679705832 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255482967 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67737746 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37011786 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2724988246 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509612209 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3204133 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 979747229 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 416253397 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1284965558 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.953058 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971218 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 871373069 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 157 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 156 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123546719 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679659315 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255464076 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67507479 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36716823 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2724801247 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509489521 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3207288 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 979575578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 416138423 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1284797805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.953217 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971436 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 442955350 34.47% 34.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203613373 15.85% 50.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185757734 14.46% 64.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153374382 11.94% 76.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133013671 10.35% 87.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80752885 6.28% 93.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65067569 5.06% 98.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15309053 1.19% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5121541 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 442944970 34.48% 34.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203642722 15.85% 50.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185470521 14.44% 64.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153370563 11.94% 76.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133097213 10.36% 87.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80758631 6.29% 93.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65098641 5.07% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15296137 1.19% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5118407 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1284965558 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1284797805 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2189478 11.81% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11923612 64.31% 76.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4426862 23.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2193136 11.83% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11923525 64.32% 76.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4420966 23.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643894908 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 110 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643778581 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 256 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 159 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 160 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 33 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued @@ -523,84 +521,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641620248 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224096461 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641602507 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224107818 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509612209 # Type of FU issued -system.cpu.iq.rate 1.830529 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18539952 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007388 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6324036158 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3703625637 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413191204 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1897903 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1215976 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 850771 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527214134 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 938027 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62593572 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509489521 # Type of FU issued +system.cpu.iq.rate 1.830711 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18537627 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007387 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6323623582 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3703265011 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413078875 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1898180 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1217876 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 850894 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527088869 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 938279 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62595515 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235110169 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263246 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107760 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94754465 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235063652 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 262733 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107683 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94735574 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 95 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1543010 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 113 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1541249 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116823510 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 56431673 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1297935 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2867161807 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8942583 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679705832 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255482967 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 282108 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18553 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107760 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10367292 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8554999 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18922291 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462270338 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625248683 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47341871 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116795361 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 56591518 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1298088 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2866959659 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8943399 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679659315 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255464076 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 282702 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18018 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107683 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10360004 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8558145 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18918149 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462143246 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625230973 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47346275 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142173439 # number of nop insts executed -system.cpu.iew.exec_refs 844731223 # number of memory reference insts executed -system.cpu.iew.exec_branches 300901770 # Number of branches executed -system.cpu.iew.exec_stores 219482540 # Number of stores executed -system.cpu.iew.exec_rate 1.795998 # Inst execution rate -system.cpu.iew.wb_sent 2441991151 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2414041975 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388322535 # num instructions producing a value -system.cpu.iew.wb_consumers 1764247998 # num instructions consuming a value +system.cpu.iew.exec_nop 142158292 # number of nop insts executed +system.cpu.iew.exec_refs 844719037 # number of memory reference insts executed +system.cpu.iew.exec_branches 300873221 # Number of branches executed +system.cpu.iew.exec_stores 219488064 # Number of stores executed +system.cpu.iew.exec_rate 1.796171 # Inst execution rate +system.cpu.iew.wb_sent 2441862108 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413929769 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388272639 # num instructions producing a value +system.cpu.iew.wb_consumers 1764258225 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.760820 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786920 # average fanout of values written-back +system.cpu.iew.wb_rate 1.760999 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786887 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 826708029 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 826504574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16088134 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1168142048 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.557841 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.499033 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16081360 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1168002444 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.558028 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.499439 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 654070645 55.99% 55.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174984637 14.98% 70.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86150926 7.38% 78.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53558629 4.58% 82.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34734385 2.97% 85.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26071538 2.23% 88.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21585678 1.85% 89.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22876428 1.96% 91.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94109182 8.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 654033697 56.00% 56.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174911016 14.98% 70.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86140681 7.38% 78.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53576194 4.59% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34697975 2.97% 85.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25994339 2.23% 88.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21604457 1.85% 89.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22883851 1.96% 91.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94160234 8.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1168142048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1168002444 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -611,95 +609,95 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94109182 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94160234 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3634741821 # The number of ROB reads -system.cpu.rob.rob_writes 5409898345 # The number of ROB writes -system.cpu.timesIdled 948322 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 86010595 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3634347710 # The number of ROB reads +system.cpu.rob.rob_writes 5409463480 # The number of ROB writes +system.cpu.timesIdled 947782 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 85975286 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.789713 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.789713 # CPI: Total CPI of All Threads -system.cpu.ipc 1.266283 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.266283 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3318184796 # number of integer regfile reads -system.cpu.int_regfile_writes 1932088897 # number of integer regfile writes -system.cpu.fp_regfile_reads 30223 # number of floating regfile reads -system.cpu.fp_regfile_writes 511 # number of floating regfile writes +system.cpu.cpi 0.789596 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.789596 # CPI: Total CPI of All Threads +system.cpu.ipc 1.266471 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.266471 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318031256 # number of integer regfile reads +system.cpu.int_regfile_writes 1931984794 # number of integer regfile writes +system.cpu.fp_regfile_reads 30556 # number of floating regfile reads +system.cpu.fp_regfile_writes 536 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1204982897 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3725040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1883606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1883606 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085568 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22087504 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825939456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 826001408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 826001408 # Total data (bytes) +system.cpu.toL2Bus.throughput 1205179048 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3725230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1883628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1883628 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1930 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085762 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22087692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825951744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 826013504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 826013504 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10178244432 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10178550909 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1610000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14084473000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14084464250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 776.507603 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 391116973 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 968 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 404046.459711 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 773.100738 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391053395 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 965 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 405236.678756 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 776.507603 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.379154 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.379154 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 391116973 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391116973 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391116973 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391116973 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391116973 # number of overall hits -system.cpu.icache.overall_hits::total 391116973 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1504 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1504 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1504 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1504 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1504 # number of overall misses -system.cpu.icache.overall_misses::total 1504 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 108221250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 108221250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 108221250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 108221250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 108221250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 108221250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391118477 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391118477 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391118477 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391118477 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391118477 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391118477 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 773.100738 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377491 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377491 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 391053395 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391053395 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391053395 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391053395 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391053395 # number of overall hits +system.cpu.icache.overall_hits::total 391053395 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1501 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1501 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1501 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1501 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1501 # number of overall misses +system.cpu.icache.overall_misses::total 1501 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108152500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108152500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108152500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108152500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108152500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108152500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391054896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391054896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391054896 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391054896 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391054896 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391054896 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71955.618351 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71955.618351 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71955.618351 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71955.618351 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71955.618351 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71955.618351 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 344 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72053.630913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72053.630913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72053.630913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72053.630913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72053.630913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72053.630913 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 156 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 114.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 78 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -709,111 +707,111 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 536 system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 968 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75754750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75754750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75754750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75754750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75754750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75754750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75095000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75095000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75095000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75095000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75095000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75095000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78259.039256 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78259.039256 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78259.039256 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78259.039256 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78259.039256 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78259.039256 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77818.652850 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77818.652850 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77818.652850 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77818.652850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77818.652850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77818.652850 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1933792 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31423.528987 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9058568 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1963567 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.613323 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1933762 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31423.393947 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9058762 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1963540 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.613485 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 28354220250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14586.952110 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.526107 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16810.050770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.445158 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000810 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14586.517425 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.834239 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16810.042284 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.445145 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.513002 # Average percentage of cache occupancy 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number of replacements -system.cpu.dcache.tags.tagsinuse 4087.562922 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694279443 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9180264 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 75.627394 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9176170 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.561673 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694256138 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9180266 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 75.624839 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5178034250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.562922 # Average occupied blocks per requestor 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-system.cpu.dcache.overall_hits::total 694279440 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11387381 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11387381 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5188573 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5188573 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 538716411 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538716411 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155539725 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155539725 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 694256136 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694256136 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694256136 # number of overall hits +system.cpu.dcache.overall_hits::total 694256136 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11395033 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11395033 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5188777 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5188777 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16575954 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16575954 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16575954 # number of overall misses -system.cpu.dcache.overall_misses::total 16575954 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 342766302500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 342766302500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 296010973410 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 296010973410 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 274500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 274500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 638777275910 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 638777275910 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 638777275910 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 638777275910 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550126892 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550126892 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16583810 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16583810 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16583810 # number of overall misses +system.cpu.dcache.overall_misses::total 16583810 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 343354515500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 343354515500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 296317441834 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 296317441834 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 639671957334 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 639671957334 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 639671957334 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 639671957334 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550111444 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550111444 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710855394 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710855394 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710855394 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710855394 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020700 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020700 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032282 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032282 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023318 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023318 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023318 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023318 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30100.538702 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30100.538702 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57050.555791 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57050.555791 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 274500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 274500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38536.380827 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38536.380827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38536.380827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38536.380827 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12380978 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8648655 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 745505 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.607505 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132.782495 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710839946 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710839946 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710839946 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710839946 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020714 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020714 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032283 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032283 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023330 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023330 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30131.945691 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30131.945691 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57107.376523 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57107.376523 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38572.074652 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38572.074652 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38572.074652 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38572.074652 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12375504 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8646342 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 745563 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.598871 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 132.744945 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725040 # number of writebacks -system.cpu.dcache.writebacks::total 3725040 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4090717 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4090717 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3304974 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3304974 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7395691 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7395691 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7395691 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7395691 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296664 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296664 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883599 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883599 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725230 # number of writebacks +system.cpu.dcache.writebacks::total 3725230 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4098384 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4098384 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3305161 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3305161 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7403545 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7403545 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7403545 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7403545 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296649 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296649 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883616 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883616 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180263 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180263 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180263 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180263 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171778792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171778792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80694684874 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 80694684874 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 272500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 272500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252473477374 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 252473477374 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252473477374 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 252473477374 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180265 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180265 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180265 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180265 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171833895250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171833895250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80710616128 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 80710616128 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 89750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 89750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252544511378 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 252544511378 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252544511378 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 252544511378 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012914 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012914 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23542.099855 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23542.099855 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42840.692140 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42840.692140 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 272500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 272500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.769543 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.769543 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27501.769543 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27501.769543 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23549.700040 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23549.700040 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42848.763298 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42848.763298 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 89750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 89750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27509.501237 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27509.501237 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27509.501237 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27509.501237 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |