diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha')
6 files changed, 1502 insertions, 1456 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini index 10131fd38..0a31f5d4d 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout index cd35cd53a..871055fe1 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4307 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28067 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second @@ -26,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1219570622500 because target called exit() +Exiting @ tick 1241902335500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index d8a41d287..5d202194f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.222275 # Number of seconds simulated -sim_ticks 1222274983500 # Number of ticks simulated -final_tick 1222274983500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.241902 # Number of seconds simulated +sim_ticks 1241902335500 # Number of ticks simulated +final_tick 1241902335500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 407632 # Simulator instruction rate (inst/s) -host_op_rate 407632 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272801132 # Simulator tick rate (ticks/s) -host_mem_usage 256700 # Number of bytes of host memory used -host_seconds 4480.46 # Real time elapsed on the host +host_inst_rate 311711 # Simulator instruction rate (inst/s) +host_op_rate 311711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 211957790 # Simulator tick rate (ticks/s) +host_mem_usage 254092 # Number of bytes of host memory used +host_seconds 5859.20 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 61440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126177664 # Number of bytes read from this memory -system.physmem.bytes_read::total 126239104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61440 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66092544 # Number of bytes written to this memory -system.physmem.bytes_written::total 66092544 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 960 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1971526 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1972486 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1032696 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1032696 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 50267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 103231814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 103282081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 50267 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 50267 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54073384 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54073384 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54073384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 50267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 103231814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 157355465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1972486 # Number of read requests accepted -system.physmem.writeReqs 1032696 # Number of write requests accepted -system.physmem.readBursts 1972486 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1032696 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 126156992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82112 # Total number of bytes read from write queue -system.physmem.bytesWritten 66090816 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126239104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66092544 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1283 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126178240 # Number of bytes read from this memory +system.physmem.bytes_read::total 126239872 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66092288 # Number of bytes written to this memory +system.physmem.bytes_written::total 66092288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1971535 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1972498 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1032692 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1032692 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 49627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 101600775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 101650402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 49627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 49627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 53218587 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 53218587 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 53218587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 49627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 101600775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 154868990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1972498 # Number of read requests accepted +system.physmem.writeReqs 1032692 # Number of write requests accepted +system.physmem.readBursts 1972498 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1032692 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 126161536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 78336 # Total number of bytes read from write queue +system.physmem.bytesWritten 66090880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126239872 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66092288 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1224 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119355 # Per bank write bursts -system.physmem.perBankRdBursts::1 114736 # Per bank write bursts -system.physmem.perBankRdBursts::2 116711 # Per bank write bursts -system.physmem.perBankRdBursts::3 118315 # Per bank write bursts -system.physmem.perBankRdBursts::4 118360 # Per bank write bursts -system.physmem.perBankRdBursts::5 118227 # Per bank write bursts -system.physmem.perBankRdBursts::6 120694 # Per bank write bursts -system.physmem.perBankRdBursts::7 125539 # Per bank write bursts -system.physmem.perBankRdBursts::8 127875 # Per bank write bursts -system.physmem.perBankRdBursts::9 130856 # Per bank write bursts -system.physmem.perBankRdBursts::10 129453 # Per bank write bursts -system.physmem.perBankRdBursts::11 131175 # Per bank write bursts -system.physmem.perBankRdBursts::12 126741 # Per bank write bursts -system.physmem.perBankRdBursts::13 125953 # Per bank write bursts -system.physmem.perBankRdBursts::14 123325 # Per bank write bursts -system.physmem.perBankRdBursts::15 123888 # Per bank write bursts +system.physmem.perBankRdBursts::0 119357 # Per bank write bursts +system.physmem.perBankRdBursts::1 114729 # Per bank write bursts +system.physmem.perBankRdBursts::2 116715 # Per bank write bursts +system.physmem.perBankRdBursts::3 118322 # Per bank write bursts +system.physmem.perBankRdBursts::4 118352 # Per bank write bursts +system.physmem.perBankRdBursts::5 118237 # Per bank write bursts +system.physmem.perBankRdBursts::6 120696 # Per bank write bursts +system.physmem.perBankRdBursts::7 125562 # Per bank write bursts +system.physmem.perBankRdBursts::8 127868 # Per bank write bursts +system.physmem.perBankRdBursts::9 130858 # Per bank write bursts +system.physmem.perBankRdBursts::10 129451 # Per bank write bursts +system.physmem.perBankRdBursts::11 131187 # Per bank write bursts +system.physmem.perBankRdBursts::12 126743 # Per bank write bursts +system.physmem.perBankRdBursts::13 125956 # Per bank write bursts +system.physmem.perBankRdBursts::14 123338 # Per bank write bursts +system.physmem.perBankRdBursts::15 123903 # Per bank write bursts system.physmem.perBankWrBursts::0 62004 # Per bank write bursts -system.physmem.perBankWrBursts::1 62322 # Per bank write bursts -system.physmem.perBankWrBursts::2 61319 # Per bank write bursts -system.physmem.perBankWrBursts::3 62011 # Per bank write bursts -system.physmem.perBankWrBursts::4 62436 # Per bank write bursts -system.physmem.perBankWrBursts::5 63988 # Per bank write bursts -system.physmem.perBankWrBursts::6 65064 # Per bank write bursts -system.physmem.perBankWrBursts::7 66489 # Per bank write bursts -system.physmem.perBankWrBursts::8 66234 # Per bank write bursts -system.physmem.perBankWrBursts::9 66705 # Per bank write bursts -system.physmem.perBankWrBursts::10 66339 # Per bank write bursts -system.physmem.perBankWrBursts::11 66709 # Per bank write bursts -system.physmem.perBankWrBursts::12 65174 # Per bank write bursts -system.physmem.perBankWrBursts::13 65212 # Per bank write bursts -system.physmem.perBankWrBursts::14 65629 # Per bank write bursts -system.physmem.perBankWrBursts::15 65034 # Per bank write bursts +system.physmem.perBankWrBursts::1 62324 # Per bank write bursts +system.physmem.perBankWrBursts::2 61320 # Per bank write bursts +system.physmem.perBankWrBursts::3 62012 # Per bank write bursts +system.physmem.perBankWrBursts::4 62437 # Per bank write bursts +system.physmem.perBankWrBursts::5 63989 # Per bank write bursts +system.physmem.perBankWrBursts::6 65066 # Per bank write bursts +system.physmem.perBankWrBursts::7 66492 # Per bank write bursts +system.physmem.perBankWrBursts::8 66230 # Per bank write bursts +system.physmem.perBankWrBursts::9 66701 # Per bank write bursts +system.physmem.perBankWrBursts::10 66337 # Per bank write bursts +system.physmem.perBankWrBursts::11 66707 # Per bank write bursts +system.physmem.perBankWrBursts::12 65162 # Per bank write bursts +system.physmem.perBankWrBursts::13 65226 # Per bank write bursts +system.physmem.perBankWrBursts::14 65630 # Per bank write bursts +system.physmem.perBankWrBursts::15 65033 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1222274866500 # Total gap between requests +system.physmem.totGap 1241902212500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1972486 # Read request sizes (log2) +system.physmem.readPktSize::6 1972498 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1032696 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1847755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123438 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1032692 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1834002 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 137262 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 61067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 60715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 28680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 29758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 61200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,137 +194,147 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1846311 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 104.123632 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.172382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 131.523418 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1463397 79.26% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 266113 14.41% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48771 2.64% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20101 1.09% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12770 0.69% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7489 0.41% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5280 0.29% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4734 0.26% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 17656 0.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1846311 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.510131 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.099317 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 136.122575 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 60389 99.72% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 130 0.21% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 8 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1848577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.999494 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.158472 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.975371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1464855 79.24% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 267102 14.45% 93.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48426 2.62% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20608 1.11% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12613 0.68% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7404 0.40% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5582 0.30% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4649 0.25% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17338 0.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1848577 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60747 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.448697 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.033030 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 139.766082 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 60580 99.73% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 126 0.21% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 11 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 5 0.01% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-2559 4 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 1 0.00% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 4 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 3 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-4607 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60557 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60557 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.052843 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.021089 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.041900 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29161 48.15% 48.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1164 1.92% 50.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28160 46.50% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2021 3.34% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 45 0.07% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60557 # Writes before turning the bus around for reads -system.physmem.totQLat 36942736250 # Total ticks spent queuing -system.physmem.totMemAccLat 73902792500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9856015000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18741.21 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60747 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60747 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.999523 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.968024 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.037878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 30790 50.69% 50.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1097 1.81% 52.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26995 44.44% 96.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1834 3.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 26 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60747 # Writes before turning the bus around for reads +system.physmem.totQLat 58523135000 # Total ticks spent queuing +system.physmem.totMemAccLat 95484522500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9856370000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29687.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37491.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 103.21 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 54.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 103.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 54.07 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48437.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 101.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 53.22 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 101.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 53.22 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.23 # Data bus utilization in percentage -system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.21 # Data bus utilization in percentage +system.physmem.busUtilRead 0.79 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing -system.physmem.readRowHits 727606 # Number of row buffer hits during reads -system.physmem.writeRowHits 429946 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.91 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.63 # Row buffer hit rate for writes -system.physmem.avgGap 406722.41 # Average gap between requests -system.physmem.pageHitRate 38.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6766986240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3692304000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7425061800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3276501840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 79832731680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 416045775330 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 368409693000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 885449053890 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.429872 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 610096075500 # Time in different power states -system.physmem_0.memoryStateTime::REF 40814280000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 571360638500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7191102240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3923716500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7949838000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3415193280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 79832731680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 427319070030 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 358520838000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 888152489730 # Total energy per rank (pJ) -system.physmem_1.averagePower 726.641687 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 593574305750 # Time in different power states -system.physmem_1.memoryStateTime::REF 40814280000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 587881640500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 246953326 # Number of BP lookups -system.cpu.branchPred.condPredicted 186908369 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15587365 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 168276583 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165592346 # Number of BTB hits +system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing +system.physmem.readRowHits 727297 # Number of row buffer hits during reads +system.physmem.writeRowHits 428065 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.45 # Row buffer hit rate for writes +system.physmem.avgGap 413252.48 # Average gap between requests +system.physmem.pageHitRate 38.46 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6395269440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3399162525 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6797065800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2639461680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 75004519200.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 46893448560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2685169920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 246120093660 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 85384513440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 94763106600 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 570117979365 # Total energy per rank (pJ) +system.physmem_0.averagePower 459.068285 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1131989083250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3611832250 # Time in different power states +system.physmem_0.memoryStateTime::REF 31797904000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 369900280750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 222356311250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 74502708250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 539733299000 # Time in different power states +system.physmem_1.actEnergy 6803606040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3616187190 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7277830560 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2751075720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 76383156720.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47598512910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2658705600 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 254833635780 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 85755552000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 89279622225 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 576994094775 # Total energy per rank (pJ) +system.physmem_1.averagePower 464.605041 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1130512338500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3468880500 # Time in different power states +system.physmem_1.memoryStateTime::REF 32377406000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 348347909000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 223320346000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 75543655250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 558844138750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 246965199 # Number of BP lookups +system.cpu.branchPred.condPredicted 186917374 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15586746 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 168139701 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165606683 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.404866 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18556185 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 105918 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 315 # Number of indirect predictor lookups. +system.cpu.branchPred.BTBHitPct 98.493504 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18556232 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 106082 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 314 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 63 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 252 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 453405484 # DTB read hits -system.cpu.dtb.read_misses 5001335 # DTB read misses +system.cpu.dtb.read_hits 453404968 # DTB read hits +system.cpu.dtb.read_misses 5001226 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 458406819 # DTB read accesses -system.cpu.dtb.write_hits 161377349 # DTB write hits -system.cpu.dtb.write_misses 1709149 # DTB write misses +system.cpu.dtb.read_accesses 458406194 # DTB read accesses +system.cpu.dtb.write_hits 161377184 # DTB write hits +system.cpu.dtb.write_misses 1709229 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163086498 # DTB write accesses -system.cpu.dtb.data_hits 614782833 # DTB hits -system.cpu.dtb.data_misses 6710484 # DTB misses +system.cpu.dtb.write_accesses 163086413 # DTB write accesses +system.cpu.dtb.data_hits 614782152 # DTB hits +system.cpu.dtb.data_misses 6710455 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 621493317 # DTB accesses -system.cpu.itb.fetch_hits 600105517 # ITB hits +system.cpu.dtb.data_accesses 621492607 # DTB accesses +system.cpu.itb.fetch_hits 600133421 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 600105536 # ITB accesses +system.cpu.itb.fetch_accesses 600133440 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -338,16 +348,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1222274983500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2444549967 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1241902335500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2483804671 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 55126564 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 55133015 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.338468 # CPI: cycles per instruction -system.cpu.ipc 0.747123 # IPC: instructions per cycle +system.cpu.cpi 1.359962 # CPI: cycles per instruction +system.cpu.ipc 0.735315 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction @@ -383,107 +393,107 @@ system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1826378509 # Class of committed instruction -system.cpu.tickCycles 2082292947 # Number of cycles that the object actually ticked -system.cpu.idleCycles 362257020 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9121995 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.838657 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 602779955 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126091 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 66.050180 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16887433500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.838657 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996299 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996299 # Average percentage of cache occupancy +system.cpu.tickCycles 2082494897 # Number of cycles that the object actually ticked +system.cpu.idleCycles 401309774 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9121955 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.932596 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 602775567 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126051 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 66.049989 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 17009517500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.932596 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996321 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996321 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1547 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2420 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1466 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2515 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1233656307 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1233656307 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 444297476 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 444297476 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158482479 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158482479 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 602779955 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 602779955 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 602779955 # number of overall hits -system.cpu.dcache.overall_hits::total 602779955 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7239130 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7239130 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2246023 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2246023 # number of WriteReq misses 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overall miss cycles -system.cpu.dcache.overall_miss_latency::total 296441795000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 451536606 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 451536606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1233653477 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1233653477 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 444296125 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 444296125 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158479442 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158479442 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 602775567 # number of demand (read+write) hits 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+system.cpu.dcache.ReadReq_miss_latency::total 201399177000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119572112000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119572112000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 320971289000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 320971289000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 320971289000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 320971289000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 451535211 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 451535211 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 612265108 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 612265108 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 612265108 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 612265108 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 612263713 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 612263713 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 612263713 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 612263713 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016032 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013974 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013974 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015492 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015492 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015492 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015492 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25664.878722 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25664.878722 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49265.034908 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49265.034908 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31253.243358 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31253.243358 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31253.243358 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31253.243358 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013993 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013993 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015497 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015497 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015497 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015497 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27821.078103 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27821.078103 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53165.372200 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53165.372200 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33828.662523 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33828.662523 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33828.662523 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33828.662523 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3671998 # number of writebacks -system.cpu.dcache.writebacks::total 3671998 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 362 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 362 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 358700 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 358700 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 359062 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 359062 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 359062 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 359062 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238768 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238768 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887323 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126091 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126091 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126091 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126091 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 178546113500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 178546113500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85195528000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85195528000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263741641500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 263741641500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263741641500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 263741641500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3671979 # number of writebacks +system.cpu.dcache.writebacks::total 3671979 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 365 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 361730 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 361730 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 362095 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 362095 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 362095 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 362095 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238721 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238721 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887330 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887330 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126051 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126051 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126051 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126051 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194152625000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 194152625000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91149337000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 91149337000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 285301962000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 285301962000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 285301962000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 285301962000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016031 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016031 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses @@ -492,67 +502,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014905 system.cpu.dcache.demand_mshr_miss_rate::total 0.014905 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014905 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014905 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24665.262583 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24665.262583 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45140.936660 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45140.936660 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28899.738289 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28899.738289 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28899.738289 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28899.738289 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26821.399112 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26821.399112 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48295.389254 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48295.389254 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31262.367699 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31262.367699 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31262.367699 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31262.367699 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 752.723923 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 600104557 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 960 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 625108.913542 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 754.212981 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 600132458 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 623190.506750 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 752.723923 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.367541 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.367541 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 957 # Occupied blocks per task id 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-system.cpu.icache.ReadReq_hits::total 600104557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 600104557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 600104557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 600104557 # number of overall hits -system.cpu.icache.overall_hits::total 600104557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 960 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 960 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 960 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 960 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 960 # number of overall misses -system.cpu.icache.overall_misses::total 960 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 77923500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 77923500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 77923500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 77923500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 77923500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 77923500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 600105517 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 600105517 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 600105517 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 600105517 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 600105517 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 600105517 # number of overall (read+write) accesses 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88684.566676 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 88679.691516 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.216034 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.216116 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96899.894452 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96899.894452 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 94549.325026 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 94549.325026 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101448.860765 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 101448.860765 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 94549.325026 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99621.325515 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 99618.849297 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 94549.325026 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99621.325515 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 99618.849297 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1032696 # number of writebacks -system.cpu.l2cache.writebacks::total 1032696 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1032692 # number of writebacks +system.cpu.l2cache.writebacks::total 1032692 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 792050 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 792050 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 960 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 960 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 792059 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 792059 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 963 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 963 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1179476 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1179476 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 960 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1971526 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1972486 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 960 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1971526 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1972486 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62873970500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62873970500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65921000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65921000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 92254698500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 92254698500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65921000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 155128669000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 155194590000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65921000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 155128669000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 155194590000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1971535 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1972498 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1971535 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1972498 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68829843500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68829843500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 81421000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 81421000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 107861736500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 107861736500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 81421000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 176691580000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 176773001000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 81421000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 176691580000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 176773001000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419668 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419668 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419672 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419672 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162939 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162939 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162940 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162940 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216032 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216114 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216034 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216116 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216032 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.216114 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79381.314942 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79381.314942 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68667.708333 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68667.708333 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78216.681391 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78216.681391 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68667.708333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78684.566676 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78679.691516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68667.708333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78684.566676 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78679.691516 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18249049 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121998 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216034 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.216116 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86899.894452 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86899.894452 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 84549.325026 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 84549.325026 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 91448.860765 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 91448.860765 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84549.325026 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89621.325515 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89618.849297 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84549.325026 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89621.325515 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89618.849297 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18248972 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121958 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1439 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1442 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1442 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7239728 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4704694 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7239684 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4704671 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6357340 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 960 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238768 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1923 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374177 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27376100 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819077696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 819139328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1940039 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66092544 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11067090 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::CleanEvict 6357335 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887330 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887330 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 963 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238721 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1929 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374057 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27375986 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819073920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 819135744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1940051 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66092288 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11067065 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011402 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011414 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11065651 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1439 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11065623 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1442 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11067090 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12796525500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11067065 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12796468000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1440000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1444500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13689136500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13689076500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3911328 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1938842 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 3911349 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1938851 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1180436 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1032696 # Transaction distribution -system.membus.trans_dist::CleanEvict 906146 # Transaction distribution -system.membus.trans_dist::ReadExReq 792050 # Transaction distribution -system.membus.trans_dist::ReadExResp 792050 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1180436 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5883814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5883814 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192331648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192331648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1180439 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1032692 # Transaction distribution +system.membus.trans_dist::CleanEvict 906159 # Transaction distribution +system.membus.trans_dist::ReadExReq 792059 # Transaction distribution +system.membus.trans_dist::ReadExResp 792059 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1180439 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5883847 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5883847 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192332160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192332160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1972486 # Request fanout histogram +system.membus.snoop_fanout::samples 1972498 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1972486 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1972498 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1972486 # Request fanout histogram -system.membus.reqLayer0.occupancy 8508050000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1972498 # Request fanout histogram +system.membus.reqLayer0.occupancy 8507556000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 10787775250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10783034500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index b191243cb..1d1d7a36d 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index e33a21652..03b7f79ab 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4309 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:44 +gem5 executing on e108600-lin, pid 28058 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -26,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 669587683000 because target called exit() +Exiting @ tick 684199968000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 7435ab9ce..d6615dc1b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.629948 # Number of seconds simulated -sim_ticks 629947889500 # Number of ticks simulated -final_tick 629947889500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.684200 # Number of seconds simulated +sim_ticks 684199968000 # Number of ticks simulated +final_tick 684199968000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 297749 # Simulator instruction rate (inst/s) -host_op_rate 297749 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111692471 # Simulator tick rate (ticks/s) -host_mem_usage 257464 # Number of bytes of host memory used -host_seconds 5640.02 # Real time elapsed on the host -sim_insts 1679312925 # Number of instructions simulated -sim_ops 1679312925 # Number of ops (including micro ops) simulated +host_inst_rate 209715 # Simulator instruction rate (inst/s) +host_op_rate 209715 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 82651888 # Simulator tick rate (ticks/s) +host_mem_usage 254604 # Number of bytes of host memory used +host_seconds 8278.09 # Real time elapsed on the host +sim_insts 1736043781 # Number of instructions simulated +sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 56512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 116052224 # Number of bytes read from this memory -system.physmem.bytes_read::total 116108736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 56512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 56512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65771840 # Number of bytes written to this memory -system.physmem.bytes_written::total 65771840 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 883 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1813316 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1814199 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1027685 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1027685 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89709 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 184225118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 184314827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89709 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89709 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 104408382 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 104408382 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 104408382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 184225118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 288723209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1814199 # Number of read requests accepted -system.physmem.writeReqs 1027685 # Number of write requests accepted -system.physmem.readBursts 1814199 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1027685 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 116025984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82752 # Total number of bytes read from write queue -system.physmem.bytesWritten 65770240 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 116108736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65771840 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1293 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126674880 # Number of bytes read from this memory +system.physmem.bytes_read::total 126735616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66206592 # Number of bytes written to this memory +system.physmem.bytes_written::total 66206592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 949 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1979295 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1980244 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1034478 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1034478 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 88769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 185143066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 185231836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 88769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 88769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96764974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96764974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96764974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 88769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 185143066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 281996809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1980244 # Number of read requests accepted +system.physmem.writeReqs 1034478 # Number of write requests accepted +system.physmem.readBursts 1980244 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1034478 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 126652288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83328 # Total number of bytes read from write queue +system.physmem.bytesWritten 66205120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126735616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66206592 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1302 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 109825 # Per bank write bursts -system.physmem.perBankRdBursts::1 106113 # Per bank write bursts -system.physmem.perBankRdBursts::2 107421 # Per bank write bursts -system.physmem.perBankRdBursts::3 108541 # Per bank write bursts -system.physmem.perBankRdBursts::4 108748 # Per bank write bursts -system.physmem.perBankRdBursts::5 108721 # Per bank write bursts -system.physmem.perBankRdBursts::6 111475 # Per bank write bursts -system.physmem.perBankRdBursts::7 116266 # Per bank write bursts -system.physmem.perBankRdBursts::8 117532 # Per bank write bursts -system.physmem.perBankRdBursts::9 120021 # Per bank write bursts -system.physmem.perBankRdBursts::10 119000 # Per bank write bursts -system.physmem.perBankRdBursts::11 120366 # Per bank write bursts -system.physmem.perBankRdBursts::12 116224 # Per bank write bursts -system.physmem.perBankRdBursts::13 115367 # Per bank write bursts -system.physmem.perBankRdBursts::14 113352 # Per bank write bursts -system.physmem.perBankRdBursts::15 113934 # Per bank write bursts -system.physmem.perBankWrBursts::0 61679 # Per bank write bursts -system.physmem.perBankWrBursts::1 62003 # Per bank write bursts -system.physmem.perBankWrBursts::2 61008 # Per bank write bursts -system.physmem.perBankWrBursts::3 61698 # Per bank write bursts -system.physmem.perBankWrBursts::4 62148 # Per bank write bursts -system.physmem.perBankWrBursts::5 63666 # Per bank write bursts -system.physmem.perBankWrBursts::6 64723 # Per bank write bursts -system.physmem.perBankWrBursts::7 66137 # Per bank write bursts -system.physmem.perBankWrBursts::8 65915 # Per bank write bursts -system.physmem.perBankWrBursts::9 66335 # Per bank write bursts -system.physmem.perBankWrBursts::10 66021 # Per bank write bursts -system.physmem.perBankWrBursts::11 66389 # Per bank write bursts -system.physmem.perBankWrBursts::12 64907 # Per bank write bursts -system.physmem.perBankWrBursts::13 64927 # Per bank write bursts -system.physmem.perBankWrBursts::14 65328 # Per bank write bursts -system.physmem.perBankWrBursts::15 64776 # Per bank write bursts +system.physmem.perBankRdBursts::0 119682 # Per bank write bursts +system.physmem.perBankRdBursts::1 115093 # Per bank write bursts +system.physmem.perBankRdBursts::2 117079 # Per bank write bursts +system.physmem.perBankRdBursts::3 118658 # Per bank write bursts +system.physmem.perBankRdBursts::4 118799 # Per bank write bursts +system.physmem.perBankRdBursts::5 118596 # Per bank write bursts +system.physmem.perBankRdBursts::6 121104 # Per bank write bursts +system.physmem.perBankRdBursts::7 126057 # Per bank write bursts +system.physmem.perBankRdBursts::8 128556 # Per bank write bursts +system.physmem.perBankRdBursts::9 131368 # Per bank write bursts +system.physmem.perBankRdBursts::10 130043 # Per bank write bursts +system.physmem.perBankRdBursts::11 131744 # Per bank write bursts +system.physmem.perBankRdBursts::12 127398 # Per bank write bursts +system.physmem.perBankRdBursts::13 126519 # Per bank write bursts +system.physmem.perBankRdBursts::14 123764 # Per bank write bursts +system.physmem.perBankRdBursts::15 124482 # Per bank write bursts +system.physmem.perBankWrBursts::0 62070 # Per bank write bursts +system.physmem.perBankWrBursts::1 62408 # Per bank write bursts +system.physmem.perBankWrBursts::2 61409 # Per bank write bursts +system.physmem.perBankWrBursts::3 62103 # Per bank write bursts +system.physmem.perBankWrBursts::4 62566 # Per bank write bursts +system.physmem.perBankWrBursts::5 64096 # Per bank write bursts +system.physmem.perBankWrBursts::6 65160 # Per bank write bursts +system.physmem.perBankWrBursts::7 66609 # Per bank write bursts +system.physmem.perBankWrBursts::8 66404 # Per bank write bursts +system.physmem.perBankWrBursts::9 66820 # Per bank write bursts +system.physmem.perBankWrBursts::10 66475 # Per bank write bursts +system.physmem.perBankWrBursts::11 66816 # Per bank write bursts +system.physmem.perBankWrBursts::12 65322 # Per bank write bursts +system.physmem.perBankWrBursts::13 65320 # Per bank write bursts +system.physmem.perBankWrBursts::14 65711 # Per bank write bursts +system.physmem.perBankWrBursts::15 65166 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 629947397500 # Total gap between requests +system.physmem.totGap 684199865500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1814199 # Read request sizes (log2) +system.physmem.readPktSize::6 1980244 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1027685 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1469096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 241446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1034478 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1615224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 253124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 75634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,34 +145,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 51064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 57932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 63157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 65572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 24649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 51175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 58148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 64398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 66372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -194,139 +194,149 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1631200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 111.449220 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 84.546651 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 143.577205 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1240852 76.07% 76.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 269138 16.50% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51923 3.18% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20333 1.25% 97.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12353 0.76% 97.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6354 0.39% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4947 0.30% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3735 0.23% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21565 1.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1631200 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60546 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.938741 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 22.568202 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 131.498063 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 60449 99.84% 99.84% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 61 0.10% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1786108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.975625 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.936522 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 138.228671 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1386417 77.62% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 276583 15.49% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52891 2.96% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20920 1.17% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12358 0.69% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6524 0.37% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5164 0.29% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3751 0.21% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21500 1.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1786108 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61165 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.352277 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 22.914892 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 140.448273 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 60991 99.72% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 137 0.22% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 7 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 2 0.00% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 4 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 5 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 3 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 3 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-5119 4 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60546 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60546 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.973210 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.937472 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.113084 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 32669 53.96% 53.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1474 2.43% 56.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 22634 37.38% 93.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3027 5.00% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 624 1.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 106 0.18% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60546 # Writes before turning the bus around for reads -system.physmem.totQLat 37088946500 # Total ticks spent queuing -system.physmem.totMemAccLat 71080934000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9064530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20458.28 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::15360-15871 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 61165 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61165 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.912532 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.877578 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.101156 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 34708 56.74% 56.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1369 2.24% 58.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 21665 35.42% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2721 4.45% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 576 0.94% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 109 0.18% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61165 # Writes before turning the bus around for reads +system.physmem.totQLat 56581400750 # Total ticks spent queuing +system.physmem.totMemAccLat 93686563250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9894710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28591.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39208.28 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 184.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 104.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 184.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 104.41 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47341.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 185.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 96.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 185.23 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 96.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.25 # Data bus utilization in percentage -system.physmem.busUtilRead 1.44 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.82 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.61 # Average write queue length when enqueuing -system.physmem.readRowHits 781743 # Number of row buffer hits during reads -system.physmem.writeRowHits 427619 # Number of row buffer hits during writes -system.physmem.readRowHitRate 43.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.61 # Row buffer hit rate for writes -system.physmem.avgGap 221665.42 # Average gap between requests -system.physmem.pageHitRate 42.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5990438160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3268592250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6841434600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3259841760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 41145046800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 279886127580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 132453942750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 472845423900 # Total energy per rank (pJ) -system.physmem_0.averagePower 750.611658 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 218497726500 # Time in different power states -system.physmem_0.memoryStateTime::REF 21035300000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 390413882500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6341433840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3460107750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7299201000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3399395040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 41145046800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 287961158835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 125370582000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 474976925265 # Total energy per rank (pJ) -system.physmem_1.averagePower 753.995279 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 206677750500 # Time in different power states -system.physmem_1.memoryStateTime::REF 21035300000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 402234088500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 393343738 # Number of BP lookups -system.cpu.branchPred.condPredicted 308206683 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15638618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 270406177 # Number of BTB lookups -system.cpu.branchPred.BTBHits 266678706 # Number of BTB hits +system.physmem.busUtil 2.20 # Data bus utilization in percentage +system.physmem.busUtilRead 1.45 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing +system.physmem.readRowHits 796002 # Number of row buffer hits during reads +system.physmem.writeRowHits 431282 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.69 # Row buffer hit rate for writes +system.physmem.avgGap 226952.89 # Average gap between requests +system.physmem.pageHitRate 40.73 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6177735060 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3283540260 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6819185520 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2643517620 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 44816475600.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 37044798750 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1443275040 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 170396037690 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 31359460320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 36616359660 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 340610162070 # Total energy per rank (pJ) +system.physmem_0.averagePower 497.822532 # Core power per rank (mW) +system.physmem_0.totalIdleTime 599184631500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1534958250 # Time in different power states +system.physmem_0.memoryStateTime::REF 18981984000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 143840379000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 81664935250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 64497738500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 373679973000 # Time in different power states +system.physmem_1.actEnergy 6575111760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3494739600 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7310460360 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2756337480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 45376412640.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 37526229300 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1410684000 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 175219175340 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 30265452000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 34407180735 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 344356241235 # Total energy per rank (pJ) +system.physmem_1.averagePower 503.297652 # Core power per rank (mW) +system.physmem_1.totalIdleTime 598199672750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1433387500 # Time in different power states +system.physmem_1.memoryStateTime::REF 19217296000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 135130926250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 78815070250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 65349556500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 384253731500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 409436754 # Number of BP lookups +system.cpu.branchPred.condPredicted 318234486 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15963820 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282367334 # Number of BTB lookups +system.cpu.branchPred.BTBHits 278623697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.621529 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24232356 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 43 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 11458 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 743 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 10715 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 54 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 98.674196 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26172484 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 47 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 12628 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1002 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 11626 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 76 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 615604408 # DTB read hits -system.cpu.dtb.read_misses 10829988 # DTB read misses +system.cpu.dtb.read_hits 645003218 # DTB read hits +system.cpu.dtb.read_misses 12159343 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 626434396 # DTB read accesses -system.cpu.dtb.write_hits 204678819 # DTB write hits -system.cpu.dtb.write_misses 7425838 # DTB write misses +system.cpu.dtb.read_accesses 657162561 # DTB read accesses +system.cpu.dtb.write_hits 218108239 # DTB write hits +system.cpu.dtb.write_misses 7507876 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 212104657 # DTB write accesses -system.cpu.dtb.data_hits 820283227 # DTB hits -system.cpu.dtb.data_misses 18255826 # DTB misses +system.cpu.dtb.write_accesses 225616115 # DTB write accesses +system.cpu.dtb.data_hits 863111457 # DTB hits +system.cpu.dtb.data_misses 19667219 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 838539053 # DTB accesses -system.cpu.itb.fetch_hits 399075166 # ITB hits +system.cpu.dtb.data_accesses 882778676 # DTB accesses +system.cpu.itb.fetch_hits 420694791 # ITB hits system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 399075203 # ITB accesses +system.cpu.itb.fetch_accesses 420694828 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -339,751 +349,759 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 23 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1259895780 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1368399937 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 409587649 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3241372877 # Number of instructions fetch has processed -system.cpu.fetch.Branches 393343738 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 290911805 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 828631431 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 43212526 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 431834940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3410573803 # Number of instructions fetch has processed +system.cpu.fetch.Branches 409436754 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 304797183 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 913784247 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45380414 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1670 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 399075166 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 7874466 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1259827144 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.572871 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.161590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1708 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 420694791 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8284167 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1368311169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.492543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.138689 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 668246093 53.04% 53.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43806893 3.48% 56.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 23751936 1.89% 58.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40823777 3.24% 61.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 134784051 10.70% 72.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61318653 4.87% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43063501 3.42% 80.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28777614 2.28% 82.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 215254626 17.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 743223403 54.32% 54.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47685517 3.48% 57.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24183643 1.77% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45097399 3.30% 62.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142825430 10.44% 73.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 65953370 4.82% 78.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43585313 3.19% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29408397 2.15% 83.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226348697 16.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1259827144 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.312203 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.572731 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 336809889 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 370413676 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 497881112 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 33116842 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21605625 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58265374 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3099960384 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1859 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21605625 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 354079753 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 199727925 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5296 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 510193154 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 174215391 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3021993285 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1813082 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19910474 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 129183664 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30561708 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2254247429 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3918399799 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3918272154 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 127644 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1331032194 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 923215197 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 126 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 124 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 94488821 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 681241316 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255797496 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 84438658 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55736283 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2741763403 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 107 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2499259906 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1517170 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1062450541 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 465504121 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 84 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1259827144 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.983812 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.153359 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1368311169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.299208 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.492381 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 353769261 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 432754726 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 524267891 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34829792 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22689499 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62032551 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3256358950 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22689499 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 372017301 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 224454621 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9976 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 537214927 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 211924845 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3173979679 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1947204 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21862090 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 161736150 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 34961727 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2371970000 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4117940809 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4117804241 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 136567 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 995767037 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 144 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 143 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99713027 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 717292360 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272467386 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90468830 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58360421 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2884387847 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 125 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2620166340 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1550282 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1148344190 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 502911540 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 96 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1368311169 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.914891 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.143845 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 494791866 39.27% 39.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 161324184 12.81% 52.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 149742004 11.89% 63.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141543893 11.24% 75.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 119990032 9.52% 84.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80369213 6.38% 91.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 66025796 5.24% 96.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 32462182 2.58% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13577974 1.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 564702258 41.27% 41.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169734991 12.40% 53.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158008570 11.55% 65.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149164272 10.90% 76.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126054849 9.21% 85.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84104604 6.15% 91.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68048276 4.97% 96.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34057471 2.49% 98.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14435878 1.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1259827144 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1368311169 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 12419183 35.12% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18417667 52.09% 87.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4521757 12.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13157745 35.86% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18955564 51.66% 87.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4577828 12.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1641003125 65.66% 65.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896111 0.04% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 23 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 164 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 640377775 25.62% 91.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 216982552 8.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1716973131 65.53% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 895059 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 21 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 671607156 25.63% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230690638 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2499259906 # Type of FU issued -system.cpu.iq.rate 1.983704 # Inst issue rate -system.cpu.iq.fu_busy_cnt 35358607 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014148 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6293293204 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3803117225 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2401572542 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1929523 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1233317 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 883284 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2533656719 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 961794 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60564498 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2620166340 # Type of FU issued +system.cpu.iq.rate 1.914766 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36691137 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014003 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6644947058 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4031627633 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2518705843 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1938210 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1246935 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 885827 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2655891113 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 966364 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69399237 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 251534222 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 355806 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 138747 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 101659209 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 272696697 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 372755 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 144718 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 111738884 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 256 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6319064 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 276 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6347426 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21605625 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 137066476 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 20199207 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2888644044 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6351774 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 681241316 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255797496 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 107 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 653480 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19719948 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 138747 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10434747 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8530204 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18964951 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2455710851 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 626434405 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 43549049 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22689499 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 153700665 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24607409 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3035418130 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6594075 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 717292360 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272467386 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 125 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 793020 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 24069505 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 144718 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10634250 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8701065 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19335315 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2575033857 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 657162570 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45132483 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 146880534 # number of nop insts executed -system.cpu.iew.exec_refs 838539129 # number of memory reference insts executed -system.cpu.iew.exec_branches 303173790 # Number of branches executed -system.cpu.iew.exec_stores 212104724 # Number of stores executed -system.cpu.iew.exec_rate 1.949138 # Inst execution rate -system.cpu.iew.wb_sent 2430569294 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2402455826 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1423499549 # num instructions producing a value -system.cpu.iew.wb_consumers 1834375042 # num instructions consuming a value -system.cpu.iew.wb_rate 1.906869 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.776013 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 934600585 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 23 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15637980 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1130658933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.557680 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.564025 # Number of insts commited each cycle +system.cpu.iew.exec_nop 151030158 # number of nop insts executed +system.cpu.iew.exec_refs 882778753 # number of memory reference insts executed +system.cpu.iew.exec_branches 315511040 # Number of branches executed +system.cpu.iew.exec_stores 225616183 # Number of stores executed +system.cpu.iew.exec_rate 1.881785 # Inst execution rate +system.cpu.iew.wb_sent 2549403036 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2519591670 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1487461563 # num instructions producing a value +system.cpu.iew.wb_consumers 1918503373 # num instructions consuming a value +system.cpu.iew.wb_rate 1.841268 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775324 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 998993468 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15963112 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1230277663 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.479162 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.528603 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 654603026 57.90% 57.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 156815138 13.87% 71.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 77634971 6.87% 78.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 50637990 4.48% 83.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28095009 2.48% 85.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18859448 1.67% 87.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19659708 1.74% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22259274 1.97% 90.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102094369 9.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 741569515 60.28% 60.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159647987 12.98% 73.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79500884 6.46% 79.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52016561 4.23% 83.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28471103 2.31% 86.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19445294 1.58% 87.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19999560 1.63% 89.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23041626 1.87% 91.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106585133 8.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1130658933 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1761204444 # Number of instructions committed -system.cpu.commit.committedOps 1761204444 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1230277663 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1819780126 # Number of instructions committed +system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 583845365 # Number of memory references committed -system.cpu.commit.loads 429707085 # Number of loads committed +system.cpu.commit.refs 605324165 # Number of memory references committed +system.cpu.commit.loads 444595663 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 208988363 # Number of branches committed -system.cpu.commit.fp_insts 805327 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1662744776 # Number of committed integer instructions. -system.cpu.commit.function_calls 16089601 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 81891519 4.65% 4.65% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1094662288 62.15% 66.80% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 66 0.00% 66.80% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.80% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 805058 0.05% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 429707085 24.40% 91.25% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 154138280 8.75% 100.00% # Class of committed instruction +system.cpu.commit.branches 214632552 # Number of branches committed +system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. +system.cpu.commit.function_calls 16767440 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1761204444 # Class of committed instruction -system.cpu.commit.bw_lim_events 102094369 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3648383709 # The number of ROB reads -system.cpu.rob.rob_writes 5520911290 # The number of ROB writes -system.cpu.timesIdled 650 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 68636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1679312925 # Number of Instructions Simulated -system.cpu.committedOps 1679312925 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.750245 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.750245 # CPI: Total CPI of All Threads -system.cpu.ipc 1.332898 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.332898 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3307128958 # number of integer regfile reads -system.cpu.int_regfile_writes 1925697564 # number of integer regfile writes -system.cpu.fp_regfile_reads 36300 # number of floating regfile reads -system.cpu.fp_regfile_writes 615 # number of floating regfile writes +system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction +system.cpu.commit.bw_lim_events 106585133 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3856686924 # The number of ROB reads +system.cpu.rob.rob_writes 5775715040 # The number of ROB writes +system.cpu.timesIdled 709 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 88768 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1736043781 # Number of Instructions Simulated +system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.788229 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.788229 # CPI: Total CPI of All Threads +system.cpu.ipc 1.268667 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.268667 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3463738117 # number of integer regfile reads +system.cpu.int_regfile_writes 2019389646 # number of integer regfile writes +system.cpu.fp_regfile_reads 39803 # number of floating regfile reads +system.cpu.fp_regfile_writes 598 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 8606834 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.896222 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 685926884 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 8610930 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.657701 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5135502500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.896222 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997777 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997777 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9207265 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.531672 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 712311191 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9211361 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.329636 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5174346500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.531672 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997933 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997933 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 950 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2966 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 666 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2980 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1415363302 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1415363302 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 536911304 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 536911304 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 149015576 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 149015576 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1470218079 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1470218079 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 556814159 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 556814159 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155497028 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155497028 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits 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cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 79500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 79500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 797889681780 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 797889681780 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 797889681780 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 797889681780 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 569774852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 569774852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 703376181 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 703376181 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 703376181 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 703376181 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022443 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022443 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.033234 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.033234 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 730503354 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 730503354 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 730503354 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 730503354 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022747 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022747 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032549 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032549 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024808 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024808 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024808 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024808 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32244.047607 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32244.047607 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61357.355228 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61357.355228 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 73500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 73500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40791.029369 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40791.029369 # average overall miss latency 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-system.cpu.dcache.ReadReq_mshr_hits::total 5571741 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3266630 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3266630 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8838371 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8838371 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8838371 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8838371 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 6754856 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 6754856 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1856074 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1856074 # number of WriteReq MSHR misses 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43858.968631 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 43858.968631 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 43858.968631 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 43858.968631 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16718017 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10716708 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1109373 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 69036 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.069789 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 155.233617 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 3713171 # number of writebacks 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number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879172 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8610930 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8610930 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8610930 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8610930 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 164940989000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 164940989000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84797281851 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84797281851 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 72500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 72500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 249738270851 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 249738270851 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 249738270851 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 249738270851 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012299 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012299 # mshr miss rate for ReadReq accesses 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0.011692 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012242 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012242 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012242 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012242 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24418.135487 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24418.135487 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45686.369105 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45686.369105 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 72500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 72500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29002.473699 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29002.473699 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29002.473699 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29002.473699 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 744.964371 # Cycle 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 420693280 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 949 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 443301.664910 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 744.964371 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.363752 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.363752 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 883 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 883 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.431152 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 798151215 # Number of tag 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latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77496.368192 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77496.368192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77496.368192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77496.368192 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 390 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 753.632230 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.367984 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.367984 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 948 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 882 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 841390531 # Number of tag accesses +system.cpu.icache.tags.data_accesses 841390531 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 420693280 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 420693280 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 420693280 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 420693280 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 420693280 # number of overall hits +system.cpu.icache.overall_hits::total 420693280 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1511 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1511 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1511 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1511 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1511 # number of overall misses +system.cpu.icache.overall_misses::total 1511 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 138965499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 138965499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 138965499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 138965499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 138965499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 138965499 # number of overall miss cycles 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-system.cpu.icache.demand_mshr_misses::cpu.inst 883 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 883 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 883 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 883 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75063499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75063499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75063499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75063499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75063499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75063499 # number of overall MSHR miss cycles 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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85009.625142 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85009.625142 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85009.625142 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 85009.625142 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85009.625142 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 85009.625142 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1781749 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31982.912242 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 15403967 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1814517 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.489293 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 27850464000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9.216492 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.928604 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31946.767147 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000281 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000822 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.974938 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.976041 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98967.332982 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98967.332982 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98967.332982 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 98967.332982 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98967.332982 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 98967.332982 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1947802 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32040.149631 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16438766 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1980570 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.300018 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 28106474000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8.660797 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.112733 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32006.376101 # Average occupied blocks per requestor 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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413097 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413097 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.416995 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.416995 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.154936 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.154936 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.163073 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.163073 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.210583 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.210664 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214875 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214956 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.210583 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.210664 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81318.006638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81318.006638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73501.698754 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73501.698754 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79770.039969 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79770.039969 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73501.698754 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80424.584297 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80421.214817 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73501.698754 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80424.584297 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80421.214817 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 17218648 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 8606834 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214875 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214956 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87792.362802 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87792.362802 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 87461.538462 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 87461.538462 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89078.804750 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89078.804750 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 87461.538462 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88569.496462 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88568.965491 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 87461.538462 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88569.496462 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88568.965491 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18419576 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207266 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1383 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1383 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1448 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1448 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 6755724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4623913 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5764670 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1856089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1856089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 883 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6754842 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1766 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 25828695 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 25830461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 781258112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 781314624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1781749 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65771840 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 10393563 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000133 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011535 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7333122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4747649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6407418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 949 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332173 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27631886 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827170048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827230848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1947802 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66206592 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11160112 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011390 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10392180 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1383 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11158664 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1448 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10393563 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12205552000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11160112 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12922960000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1324500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1423500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 12916395000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3594729 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1780530 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 13817041500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 3926838 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1946594 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1047454 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1027685 # Transaction distribution -system.membus.trans_dist::CleanEvict 752845 # Transaction distribution -system.membus.trans_dist::ReadExReq 766745 # Transaction distribution -system.membus.trans_dist::ReadExResp 766745 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1047454 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5408928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5408928 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 181880576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 181880576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1196632 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1034478 # Transaction distribution +system.membus.trans_dist::CleanEvict 912116 # Transaction distribution +system.membus.trans_dist::ReadExReq 783612 # Transaction distribution +system.membus.trans_dist::ReadExResp 783612 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1196632 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5907082 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5907082 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192942208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192942208 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1814199 # Request fanout histogram +system.membus.snoop_fanout::samples 1980244 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1814199 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1980244 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1814199 # Request fanout histogram -system.membus.reqLayer0.occupancy 8122837000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9853981000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1980244 # Request fanout histogram +system.membus.reqLayer0.occupancy 8533086500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 10770167500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- |