diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt | 1034 |
1 files changed, 518 insertions, 516 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 9172e88dd..b905eb22a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.096187 # Number of seconds simulated -sim_ticks 1096186990500 # Number of ticks simulated -final_tick 1096186990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.108945 # Number of seconds simulated +sim_ticks 1108944740000 # Number of ticks simulated +final_tick 1108944740000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 245276 # Simulator instruction rate (inst/s) -host_op_rate 264248 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174074375 # Simulator tick rate (ticks/s) -host_mem_usage 310916 # Number of bytes of host memory used -host_seconds 6297.23 # Real time elapsed on the host +host_inst_rate 239014 # Simulator instruction rate (inst/s) +host_op_rate 257501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171603826 # Simulator tick rate (ticks/s) +host_mem_usage 253696 # Number of bytes of host memory used +host_seconds 6462.24 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131551936 # Number of bytes read from this memory -system.physmem.bytes_read::total 131551936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66968384 # Number of bytes written to this memory -system.physmem.bytes_written::total 66968384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2055499 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2055499 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046381 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 120008664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 120008664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 46007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 46007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 61092117 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 61092117 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 61092117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 120008664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 181100781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2055499 # Number of read requests accepted -system.physmem.writeReqs 1046381 # Number of write requests accepted -system.physmem.readBursts 2055499 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046381 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131465088 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 86848 # Total number of bytes read from write queue -system.physmem.bytesWritten 66966784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131551936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66968384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1357 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 131625408 # Number of bytes read from this memory +system.physmem.bytes_read::total 131625408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66989632 # Number of bytes written to this memory +system.physmem.bytes_written::total 66989632 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2056647 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2056647 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046713 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046713 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 118694289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 118694289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60408449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60408449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60408449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 118694289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 179102739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2056647 # Number of read requests accepted +system.physmem.writeReqs 1046713 # Number of write requests accepted +system.physmem.readBursts 2056647 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046713 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131542016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83392 # Total number of bytes read from write queue +system.physmem.bytesWritten 66988032 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131625408 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66989632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1303 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127914 # Per bank write bursts -system.physmem.perBankRdBursts::1 125107 # Per bank write bursts -system.physmem.perBankRdBursts::2 122280 # Per bank write bursts -system.physmem.perBankRdBursts::3 124254 # Per bank write bursts -system.physmem.perBankRdBursts::4 123262 # Per bank write bursts +system.physmem.perBankRdBursts::0 128036 # Per bank write bursts +system.physmem.perBankRdBursts::1 125234 # Per bank write bursts +system.physmem.perBankRdBursts::2 122300 # Per bank write bursts +system.physmem.perBankRdBursts::3 124230 # Per bank write bursts +system.physmem.perBankRdBursts::4 123415 # Per bank write bursts system.physmem.perBankRdBursts::5 123345 # Per bank write bursts -system.physmem.perBankRdBursts::6 123865 # Per bank write bursts -system.physmem.perBankRdBursts::7 124190 # Per bank write bursts -system.physmem.perBankRdBursts::8 131999 # Per bank write bursts -system.physmem.perBankRdBursts::9 134064 # Per bank write bursts -system.physmem.perBankRdBursts::10 132428 # Per bank write bursts -system.physmem.perBankRdBursts::11 133673 # Per bank write bursts -system.physmem.perBankRdBursts::12 133725 # Per bank write bursts -system.physmem.perBankRdBursts::13 133862 # Per bank write bursts -system.physmem.perBankRdBursts::14 129895 # Per bank write bursts -system.physmem.perBankRdBursts::15 130279 # Per bank write bursts -system.physmem.perBankWrBursts::0 65789 # Per bank write bursts -system.physmem.perBankWrBursts::1 64087 # Per bank write bursts -system.physmem.perBankWrBursts::2 62403 # Per bank write bursts -system.physmem.perBankWrBursts::3 62885 # Per bank write bursts -system.physmem.perBankWrBursts::4 62820 # Per bank write bursts -system.physmem.perBankWrBursts::5 62979 # Per bank write bursts -system.physmem.perBankWrBursts::6 64285 # Per bank write bursts -system.physmem.perBankWrBursts::7 65232 # Per bank write bursts -system.physmem.perBankWrBursts::8 67082 # Per bank write bursts -system.physmem.perBankWrBursts::9 67588 # Per bank write bursts -system.physmem.perBankWrBursts::10 67303 # Per bank write bursts -system.physmem.perBankWrBursts::11 67613 # Per bank write bursts -system.physmem.perBankWrBursts::12 67020 # Per bank write bursts -system.physmem.perBankWrBursts::13 67468 # Per bank write bursts -system.physmem.perBankWrBursts::14 66169 # Per bank write bursts -system.physmem.perBankWrBursts::15 65633 # Per bank write bursts +system.physmem.perBankRdBursts::6 123964 # Per bank write bursts +system.physmem.perBankRdBursts::7 124409 # Per bank write bursts +system.physmem.perBankRdBursts::8 131872 # Per bank write bursts +system.physmem.perBankRdBursts::9 134140 # Per bank write bursts +system.physmem.perBankRdBursts::10 132473 # Per bank write bursts +system.physmem.perBankRdBursts::11 133756 # Per bank write bursts +system.physmem.perBankRdBursts::12 133901 # Per bank write bursts +system.physmem.perBankRdBursts::13 134102 # Per bank write bursts +system.physmem.perBankRdBursts::14 129958 # Per bank write bursts +system.physmem.perBankRdBursts::15 130209 # Per bank write bursts +system.physmem.perBankWrBursts::0 65849 # Per bank write bursts +system.physmem.perBankWrBursts::1 64131 # Per bank write bursts +system.physmem.perBankWrBursts::2 62381 # Per bank write bursts +system.physmem.perBankWrBursts::3 62840 # Per bank write bursts +system.physmem.perBankWrBursts::4 62871 # Per bank write bursts +system.physmem.perBankWrBursts::5 62990 # Per bank write bursts +system.physmem.perBankWrBursts::6 64312 # Per bank write bursts +system.physmem.perBankWrBursts::7 65310 # Per bank write bursts +system.physmem.perBankWrBursts::8 67027 # Per bank write bursts +system.physmem.perBankWrBursts::9 67624 # Per bank write bursts +system.physmem.perBankWrBursts::10 67292 # Per bank write bursts +system.physmem.perBankWrBursts::11 67645 # Per bank write bursts +system.physmem.perBankWrBursts::12 67063 # Per bank write bursts +system.physmem.perBankWrBursts::13 67560 # Per bank write bursts +system.physmem.perBankWrBursts::14 66200 # Per bank write bursts +system.physmem.perBankWrBursts::15 65593 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1096186902500 # Total gap between requests +system.physmem.totGap 1108944651500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2055499 # Read request sizes (log2) +system.physmem.readPktSize::6 2056647 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046381 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1922421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131703 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046713 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1923205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132121 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,30 +140,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 61936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -189,126 +189,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1916158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.556187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.764224 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.552714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1491113 77.82% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305811 15.96% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52727 2.75% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21051 1.10% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13077 0.68% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6875 0.36% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5570 0.29% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4107 0.21% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15827 0.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1916158 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61021 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.615247 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.737468 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60978 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 19 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1918209 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.496643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.775288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.095886 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1492147 77.79% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 306422 15.97% 93.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52965 2.76% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21185 1.10% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13242 0.69% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7471 0.39% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5204 0.27% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3914 0.20% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15659 0.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1918209 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61025 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.632724 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.189303 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60982 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61021 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61021 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.147474 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.112394 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.099372 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27727 45.44% 45.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1223 2.00% 47.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 27936 45.78% 93.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3708 6.08% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 355 0.58% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 59 0.10% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 10 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61021 # Writes before turning the bus around for reads -system.physmem.totQLat 38533876500 # Total ticks spent queuing -system.physmem.totMemAccLat 77049039000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10270710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18759.11 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 61025 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61025 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.151790 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.116821 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.097688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27581 45.20% 45.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1180 1.93% 47.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28172 46.16% 93.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3706 6.07% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 317 0.52% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 54 0.09% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61025 # Writes before turning the bus around for reads +system.physmem.totQLat 38537340500 # Total ticks spent queuing +system.physmem.totMemAccLat 77075040500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10276720000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18749.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37509.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 119.93 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 61.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 120.01 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 61.09 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37499.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 118.62 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 60.41 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 118.69 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.41 # Data bus utilization in percentage -system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.40 # Data bus utilization in percentage +system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing -system.physmem.readRowHits 777772 # Number of row buffer hits during reads -system.physmem.writeRowHits 406558 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes -system.physmem.avgGap 353394.36 # Average gap between requests -system.physmem.pageHitRate 38.20 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 306608104500 # Time in different power states -system.physmem.memoryStateTime::REF 36603840000 # Time in different power states +system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing +system.physmem.readRowHits 777039 # Number of row buffer hits during reads +system.physmem.writeRowHits 406774 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.86 # Row buffer hit rate for writes +system.physmem.avgGap 357336.77 # Average gap between requests +system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 313164826000 # Time in different power states +system.physmem.memoryStateTime::REF 37029980000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 752971887000 # Time in different power states +system.physmem.memoryStateTime::ACT 758746776000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 7068978000 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 7417161360 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3857081250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 4047062250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7754580600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 8267360400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3307910400 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3472476480 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 71597111040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 71597111040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 413628192720 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 422690389875 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 294876051750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 286926756000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 802089905760 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 804418317405 # Total energy per rank (pJ) -system.physmem.averagePower::0 731.713906 # Core power per rank (mW) -system.physmem.averagePower::1 733.838021 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 1255486 # Transaction distribution -system.membus.trans_dist::ReadResp 1255486 # Transaction distribution -system.membus.trans_dist::Writeback 1046381 # Transaction distribution -system.membus.trans_dist::ReadExReq 800013 # Transaction distribution -system.membus.trans_dist::ReadExResp 800013 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157379 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5157379 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198520320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198520320 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3101880 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3101880 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3101880 # Request fanout histogram -system.membus.reqLayer0.occupancy 12229457500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 19361348500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 239650352 # Number of BP lookups -system.cpu.branchPred.condPredicted 186306880 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14598405 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131764254 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121991524 # Number of BTB hits +system.physmem.actEnergy::0 7075638360 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 7426006560 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 3860715375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 4051888500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 7760165400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 8271151200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 3309232320 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 3473305920 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 72430640880 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 72430640880 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 416866648005 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 425333204280 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 299692308000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 292265504250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 810995348340 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 813251701590 # Total energy per rank (pJ) +system.physmem.averagePower::0 731.323936 # Core power per rank (mW) +system.physmem.averagePower::1 733.358627 # Core power per rank (mW) +system.cpu.branchPred.lookups 240152510 # Number of BP lookups +system.cpu.branchPred.condPredicted 186756179 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14598640 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 131763268 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122287171 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.583171 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15654227 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.808241 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15660181 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,69 +372,193 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2192373981 # number of cpu cycles simulated +system.cpu.numCycles 2217889480 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563087 # Number of instructions committed system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 42081657 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 40077128 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.419414 # CPI: cycles per instruction -system.cpu.ipc 0.704516 # IPC: instructions per cycle -system.cpu.tickCycles 1808241834 # Number of cycles that the object actually ticked -system.cpu.idleCycles 384132147 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.435933 # CPI: cycles per instruction +system.cpu.ipc 0.696411 # IPC: instructions per cycle +system.cpu.tickCycles 1838736315 # Number of cycles that the object actually ticked +system.cpu.idleCycles 379153165 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9224311 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.608602 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624084220 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9228407 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.626430 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.608602 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.997463 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1292 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2484 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1276551305 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276551305 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 453737568 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453737568 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 170346530 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170346530 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 624084098 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624084098 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 624084098 # number of overall hits +system.cpu.dcache.overall_hits::total 624084098 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7337712 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7337712 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2239517 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2239517 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9577229 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9577229 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9577229 # number of overall misses +system.cpu.dcache.overall_misses::total 9577229 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183598363496 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183598363496 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101566510500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 101566510500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 285164873996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 285164873996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 285164873996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 285164873996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 461075280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461075280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 633661327 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633661327 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 633661327 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633661327 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012976 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.015114 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015114 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.015114 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015114 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25021.200545 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25021.200545 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45351.971206 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45351.971206 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29775.300768 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29775.300768 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3700618 # number of writebacks +system.cpu.dcache.writebacks::total 3700618 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348609 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 348609 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 348822 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 348822 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 348822 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 348822 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7337499 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7337499 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890908 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890908 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9228407 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9228407 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9228407 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9228407 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168505826254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168505826254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77457723500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77457723500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245963549754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245963549754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245963549754 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245963549754 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015914 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015914 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014564 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014564 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014564 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014564 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22965.022040 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22965.022040 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40963.242791 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40963.242791 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26652.871915 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26652.871915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26652.871915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26652.871915 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.144399 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 464861353 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 661.026879 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466133968 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 566904.089024 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 568456.058537 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.144399 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322824 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322824 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 661.026879 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322767 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322767 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 929725166 # Number of tag accesses -system.cpu.icache.tags.data_accesses 929725166 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 464861353 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 464861353 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 464861353 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 464861353 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 464861353 # number of overall hits -system.cpu.icache.overall_hits::total 464861353 # number of overall hits +system.cpu.icache.tags.tag_accesses 932270396 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932270396 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 466133968 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466133968 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466133968 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466133968 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466133968 # number of overall hits +system.cpu.icache.overall_hits::total 466133968 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 820 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 464862173 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 464862173 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 464862173 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 464862173 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 464862173 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58416499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58416499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58416499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58416499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58416499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58416499 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71239.632927 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71239.632927 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -471,38 +573,159 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 820 system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57178251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 57178251 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57178251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 57178251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57178251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 57178251 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56453501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 56453501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56453501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 56453501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56453501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 56453501 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.574390 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.574390 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68845.732927 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68845.732927 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68845.732927 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68845.732927 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68845.732927 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68845.732927 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7336783 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7336783 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700640 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890869 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890869 # Transaction distribution +system.cpu.l2cache.tags.replacements 2023942 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31254.337993 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8984488 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2053718 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.374743 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 59502848750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14996.949277 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 16257.388715 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.457671 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496136 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.953807 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 107383386 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107383386 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 6081991 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6081991 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3700618 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700618 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090584 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1090584 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7172575 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7172575 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7172575 # number of overall hits +system.cpu.l2cache.overall_hits::total 7172575 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1256328 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1256328 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 800324 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 800324 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2056652 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2056652 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2056652 # number of overall misses +system.cpu.l2cache.overall_misses::total 2056652 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100398878250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 100398878250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64605165750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 64605165750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 165004044000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 165004044000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 165004044000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 165004044000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7338319 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7338319 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3700618 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3700618 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890908 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1890908 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9229227 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9229227 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9229227 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9229227 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171201 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.171201 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423249 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.423249 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222841 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.222841 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222841 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.222841 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79914.543216 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79914.543216 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80723.764063 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80723.764063 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80229.442803 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80229.442803 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80229.442803 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80229.442803 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 1046713 # number of writebacks +system.cpu.l2cache.writebacks::total 1046713 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1256323 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1256323 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800324 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 800324 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2056647 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2056647 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2056647 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2056647 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84521118250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84521118250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54527231750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54527231750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139048350000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 139048350000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139048350000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 139048350000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171200 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171200 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423249 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423249 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222841 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222841 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67276.582734 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67276.582734 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68131.446452 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68131.446452 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 7338319 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7338319 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890908 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22154304 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22155944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22157432 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22159072 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827358208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827410688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827457600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827510080 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12928292 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12929845 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -511,262 +734,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 12928292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 12929845 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12928292 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10164786000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12929845 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10165540500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1391749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1391499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14185031745 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14187091746 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 2022796 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31252.383158 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8984119 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2052571 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.377008 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14967.342328 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 16285.040830 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.456767 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496980 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.953747 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107369776 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107369776 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6081291 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6081291 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3700640 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700640 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090856 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1090856 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7172147 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7172147 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7172147 # number of overall hits -system.cpu.l2cache.overall_hits::total 7172147 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1255492 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1255492 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 800013 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 800013 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2055505 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2055505 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2055505 # number of overall misses -system.cpu.l2cache.overall_misses::total 2055505 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100333400500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 100333400500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64526294750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 64526294750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 164859695250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 164859695250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 164859695250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 164859695250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336783 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7336783 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3700640 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3700640 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890869 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1890869 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9227652 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9227652 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9227652 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9227652 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171123 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.171123 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423093 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.423093 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222755 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.222755 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222755 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.222755 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79915.603206 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79915.603206 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.557768 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.557768 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80203.986490 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80203.986490 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1046381 # number of writebacks -system.cpu.l2cache.writebacks::total 1046381 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255486 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1255486 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800013 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 800013 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055499 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2055499 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055499 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2055499 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84544683250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84544683250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54440940250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440940250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138985623500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138985623500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138985623500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138985623500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171122 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171122 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423093 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423093 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.222754 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.222754 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67340.203913 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67340.203913 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68050.069499 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68050.069499 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9222736 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.561884 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624006676 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9226832 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.629569 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9704965000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.561884 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997452 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997452 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 280 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1316 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2439 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276393554 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276393554 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 453661018 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453661018 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 170345536 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170345536 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 624006554 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624006554 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 624006554 # number of overall hits -system.cpu.dcache.overall_hits::total 624006554 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7336174 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7336174 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2240511 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2240511 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9576685 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9576685 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9576685 # number of overall misses -system.cpu.dcache.overall_misses::total 9576685 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183520141245 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183520141245 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101423015250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101423015250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 284943156495 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 284943156495 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 284943156495 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 284943156495 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 460997192 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 460997192 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 633583239 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633583239 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 633583239 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633583239 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012982 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012982 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015115 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015115 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015115 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015115 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25015.783601 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25015.783601 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45267.805090 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45267.805090 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29753.840342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29753.840342 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700640 # number of writebacks -system.cpu.dcache.writebacks::total 3700640 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349642 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 349642 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 349853 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 349853 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 349853 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 349853 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335963 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7335963 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890869 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890869 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9226832 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9226832 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9226832 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9226832 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168431190255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168431190255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77354259500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77354259500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245785449755 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245785449755 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245785449755 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245785449755 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22959.656456 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22959.656456 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40909.369978 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40909.369978 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 1256323 # Transaction distribution +system.membus.trans_dist::ReadResp 1256323 # Transaction distribution +system.membus.trans_dist::Writeback 1046713 # Transaction distribution +system.membus.trans_dist::ReadExReq 800324 # Transaction distribution +system.membus.trans_dist::ReadExResp 800324 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5160007 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5160007 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198615040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198615040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3103360 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3103360 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3103360 # Request fanout histogram +system.membus.reqLayer0.occupancy 12130659500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 19439818500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- |