diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt | 502 |
1 files changed, 251 insertions, 251 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 20e951f6a..c13f099b6 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.150226 # Number of seconds simulated -sim_ticks 1150225722500 # Number of ticks simulated -final_tick 1150225722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.150228 # Number of seconds simulated +sim_ticks 1150227786500 # Number of ticks simulated +final_tick 1150227786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 386915 # Simulator instruction rate (inst/s) -host_op_rate 416843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 288133243 # Simulator tick rate (ticks/s) -host_mem_usage 273608 # Number of bytes of host memory used -host_seconds 3991.99 # Real time elapsed on the host +host_inst_rate 394229 # Simulator instruction rate (inst/s) +host_op_rate 424722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 293579950 # Simulator tick rate (ticks/s) +host_mem_usage 273524 # Number of bytes of host memory used +host_seconds 3917.94 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory @@ -27,16 +27,16 @@ system.physmem.num_reads::total 2064767 # Nu system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 114842544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 114886222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 114842338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 114886016 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 58988408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 58988408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 58988408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 58988302 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 58988302 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 58988302 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 114842544 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 173874630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 114842338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 173874318 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 2064767 # Number of read requests accepted system.physmem.writeReqs 1060156 # Number of write requests accepted system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue @@ -61,10 +61,10 @@ system.physmem.perBankRdBursts::8 132488 # Pe system.physmem.perBankRdBursts::9 134781 # Per bank write bursts system.physmem.perBankRdBursts::10 133246 # Per bank write bursts system.physmem.perBankRdBursts::11 134508 # Per bank write bursts -system.physmem.perBankRdBursts::12 134524 # Per bank write bursts +system.physmem.perBankRdBursts::12 134523 # Per bank write bursts system.physmem.perBankRdBursts::13 134597 # Per bank write bursts system.physmem.perBankRdBursts::14 130537 # Per bank write bursts -system.physmem.perBankRdBursts::15 130646 # Per bank write bursts +system.physmem.perBankRdBursts::15 130647 # Per bank write bursts system.physmem.perBankWrBursts::0 66781 # Per bank write bursts system.physmem.perBankWrBursts::1 64940 # Per bank write bursts system.physmem.perBankWrBursts::2 63173 # Per bank write bursts @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 67159 # Pe system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1150225621500 # Total gap between requests +system.physmem.totGap 1150227685500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -98,8 +98,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1060156 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1919491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 143962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1919511 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143942 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 62506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 62502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 62571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62570 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62659 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62338 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,25 +194,25 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1927680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.704050 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.827428 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.877785 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1497957 77.71% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 310202 16.09% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52219 2.71% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20801 1.08% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13076 0.68% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7806 0.40% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5210 0.27% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5119 0.27% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15290 0.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1927680 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 62182 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.137773 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.854622 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 150.738788 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 62143 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1927678 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.704158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.827351 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.878363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1497959 77.71% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 310183 16.09% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52221 2.71% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20819 1.08% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7800 0.40% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5214 0.27% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5117 0.27% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15291 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1927678 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62183 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.137240 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.854238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 150.737609 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 62144 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes @@ -222,24 +222,24 @@ system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 62182 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 62182 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.048808 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.017651 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.031288 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29885 48.06% 48.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1078 1.73% 49.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 29552 47.53% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1636 2.63% 99.95% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 62183 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62183 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.048534 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.017369 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.031425 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29894 48.07% 48.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1086 1.75% 49.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29528 47.49% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1644 2.64% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 62182 # Writes before turning the bus around for reads -system.physmem.totQLat 59945214750 # Total ticks spent queuing -system.physmem.totMemAccLat 98635221000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrPerTurnAround::total 62183 # Writes before turning the bus around for reads +system.physmem.totQLat 59946131250 # Total ticks spent queuing +system.physmem.totMemAccLat 98636137500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29050.73 # Average queueing delay per DRAM burst +system.physmem.avgQLat 29051.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47800.73 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 47801.17 # Average memory access latency per DRAM burst system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s @@ -250,58 +250,58 @@ system.physmem.busUtilRead 0.90 # Da system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing -system.physmem.readRowHits 775403 # Number of row buffer hits during reads -system.physmem.writeRowHits 420503 # Number of row buffer hits during writes +system.physmem.readRowHits 775435 # Number of row buffer hits during reads +system.physmem.writeRowHits 420473 # Number of row buffer hits during writes system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes -system.physmem.avgGap 368081.27 # Average gap between requests +system.physmem.avgGap 368081.93 # Average gap between requests system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6704024460 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3563246940 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 6703938780 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3563201400 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 71584047600.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47598370410 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2598119520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 242886973860 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 71929585440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 82360762695 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 539073775965 # Total energy per rank (pJ) -system.physmem_0.averagePower 468.667814 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1039023905500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3501879500 # Time in different power states -system.physmem_0.memoryStateTime::REF 30346756000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 319059811750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 187317352250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77352878250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 532647044750 # Time in different power states -system.physmem_1.actEnergy 7059682140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3752298660 # Energy for precharge commands per rank (pJ) +system.physmem_0.refreshEnergy 71587735440.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47610368340 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2598027360 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 242891748180 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 71936235360 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 82347779655 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 539087705175 # Total energy per rank (pJ) +system.physmem_0.averagePower 468.679083 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1039000185750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3501543500 # Time in different power states +system.physmem_0.memoryStateTime::REF 30348316000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 319007908000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 187335147250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77377438000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 532657433750 # Time in different power states +system.physmem_1.actEnergy 7059753540 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3752336610 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 71064062160.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47576528010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2430223200 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 248601681570 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 68458810560 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 80907988260 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 540316908180 # Total energy per rank (pJ) -system.physmem_1.averagePower 469.748583 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1039511813000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3059644000 # Time in different power states -system.physmem_1.memoryStateTime::REF 30118792000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 316054273750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 178278810500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77535412750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 545178789500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019882 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610383 # Number of conditional branches predicted +system.physmem_1.refreshEnergy 71062832880.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47583848520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2430369600 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 248599905450 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68453747040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 80907358950 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 540315522360 # Total energy per rank (pJ) +system.physmem_1.averagePower 469.746535 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1039499383250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3059154750 # Time in different power states +system.physmem_1.memoryStateTime::REF 30118266000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 316057409750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 178263690250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77550921750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 545178344000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240019900 # Number of BP lookups +system.cpu.branchPred.condPredicted 186610401 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131646647 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324605 # Number of BTB hits +system.cpu.branchPred.BTBLookups 131646658 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122324616 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.918891 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.918892 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. @@ -309,7 +309,7 @@ system.cpu.branchPred.indirectHits 232 # Nu system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -339,7 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,7 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,7 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -430,16 +430,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1150225722500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2300451445 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2300455573 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363683 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41363694 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.489387 # CPI: cycles per instruction -system.cpu.ipc 0.671417 # IPC: instructions per cycle +system.cpu.cpi 1.489389 # CPI: cycles per instruction +system.cpu.ipc 0.671416 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -479,16 +479,16 @@ system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1845014986 # Number of cycles that the object actually ticked -system.cpu.idleCycles 455436459 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 1845015660 # Number of cycles that the object actually ticked +system.cpu.idleCycles 455439913 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9220107 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.805290 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624493165 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4085.805308 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624493167 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805290 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805308 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -497,43 +497,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391151 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391151 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454163885 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454163885 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170329157 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170329157 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277391153 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277391153 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454163886 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454163886 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170329158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170329158 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624493042 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624493042 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624493043 # number of overall hits -system.cpu.dcache.overall_hits::total 624493043 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 624493044 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624493044 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624493045 # number of overall hits +system.cpu.dcache.overall_hits::total 624493045 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2256890 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2256890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2256889 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2256889 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9590307 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9590307 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9590309 # number of overall misses -system.cpu.dcache.overall_misses::total 9590309 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 208195707500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 208195707500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119902321500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119902321500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 328098029000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 328098029000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 328098029000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 328098029000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497302 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9590306 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9590306 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9590308 # number of overall misses +system.cpu.dcache.overall_misses::total 9590308 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 208196327000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 208196327000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119903341000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119903341000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 328099668000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 328099668000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 328099668000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 328099668000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461497303 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461497303 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -542,10 +542,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083349 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083349 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083352 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083352 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634083350 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634083350 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634083353 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634083353 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses @@ -556,14 +556,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28389.999846 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28389.999846 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.233272 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.233272 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.420865 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34211.420865 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.413730 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34211.413730 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28390.084322 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28390.084322 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.708540 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.708540 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.595334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34211.595334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.588199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34211.588199 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -574,12 +574,12 @@ system.cpu.dcache.writebacks::writebacks 3670055 # nu system.cpu.dcache.writebacks::total 3670055 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366056 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 366056 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366105 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366105 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366105 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366105 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366055 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 366055 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366104 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366104 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366104 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366104 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses @@ -590,16 +590,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200857919000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 200857919000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92466638500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92466638500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200858538000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 200858538000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92467008500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92467008500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293324557500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 293324557500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293324638500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 293324638500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293325546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 293325546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293325627500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 293325627500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -610,24 +610,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.586749 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.586749 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.568126 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.568126 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.671158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.671158 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.763807 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.763807 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.450782 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.450782 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.456116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.456116 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.558000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.558000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.563334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.563334 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 33 # number of replacements -system.cpu.icache.tags.tagsinuse 660.478132 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466274661 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 660.477823 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466274758 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567244.113139 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567244.231144 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.478132 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 660.477823 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.322499 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.322499 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id @@ -635,15 +635,15 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 32 system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932551788 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932551788 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466274661 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466274661 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466274661 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466274661 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466274661 # number of overall hits -system.cpu.icache.overall_hits::total 466274661 # number of overall hits +system.cpu.icache.tags.tag_accesses 932551982 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932551982 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466274758 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466274758 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466274758 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466274758 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466274758 # number of overall hits +system.cpu.icache.overall_hits::total 466274758 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses @@ -656,12 +656,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 74803000 system.cpu.icache.demand_miss_latency::total 74803000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 74803000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 74803000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466275483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466275483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466275483 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466275483 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466275483 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466275483 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 466275580 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466275580 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466275580 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466275580 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466275580 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466275580 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses @@ -706,16 +706,16 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90001.216545 system.cpu.icache.demand_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 2032334 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31895.835750 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31895.837315 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 16378248 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2065102 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 7.930963 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10.372188 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535695 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.927867 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 10.372175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535649 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.929491 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000317 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000779 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.972288 # Average percentage of cache occupancy @@ -729,7 +729,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21752 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149613670 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149613670 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3670055 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3670055 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits @@ -758,18 +758,18 @@ system.cpu.l2cache.demand_misses::total 2064773 # nu system.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2063988 # number of overall misses system.cpu.l2cache.overall_misses::total 2064773 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282559500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 78282559500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282928500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 78282928500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72328000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 72328000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125996723500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 125996723500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125997338000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 125997338000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 72328000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 204279283000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 204351611000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 204280266500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 204352594500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 72328000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 204279283000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 204351611000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 204280266500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 204352594500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 3670055 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 3670055 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) @@ -798,18 +798,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.223823 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.223758 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.223823 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96368.759102 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96368.759102 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96369.213355 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96369.213355 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92137.579618 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92137.579618 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.295291 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.295291 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.786237 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.786237 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98970.497483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 98970.973807 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98970.497483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 98970.973807 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -838,18 +838,18 @@ system.cpu.l2cache.demand_mshr_misses::total 2064767 system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2063982 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2064767 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159329500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159329500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159698500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159698500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64478000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64478000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113479586000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113479586000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113480200500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113480200500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64478000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183638915500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 183703393500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183639899000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 183704377000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64478000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183638915500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 183703393500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183639899000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 183704377000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses @@ -864,25 +864,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86368.759102 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86368.759102 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86369.213355 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86369.213355 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.340415 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.340415 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.831363 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.831363 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution @@ -922,7 +922,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1252444 # Transaction distribution system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution system.membus.trans_dist::CleanEvict 970949 # Transaction distribution @@ -945,9 +945,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 2064767 # Request fanout histogram -system.membus.reqLayer0.occupancy 8804910500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8804919500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11285155750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11285149250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |