diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt | 974 |
1 files changed, 487 insertions, 487 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index c13f099b6..fe9262960 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.150228 # Number of seconds simulated -sim_ticks 1150227786500 # Number of ticks simulated -final_tick 1150227786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.150356 # Number of seconds simulated +sim_ticks 1150356296500 # Number of ticks simulated +final_tick 1150356296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 394229 # Simulator instruction rate (inst/s) -host_op_rate 424722 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 293579950 # Simulator tick rate (ticks/s) -host_mem_usage 273524 # Number of bytes of host memory used -host_seconds 3917.94 # Real time elapsed on the host +host_inst_rate 374766 # Simulator instruction rate (inst/s) +host_op_rate 403753 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 279117141 # Simulator tick rate (ticks/s) +host_mem_usage 273688 # Number of bytes of host memory used +host_seconds 4121.41 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory -system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132097728 # Number of bytes read from this memory +system.physmem.bytes_read::total 132147968 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67849984 # Number of bytes written to this memory -system.physmem.bytes_written::total 67849984 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67851072 # Number of bytes written to this memory +system.physmem.bytes_written::total 67851072 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2063982 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2064767 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 114842338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 114886016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 58988302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 58988302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 58988302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 114842338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 173874318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2064767 # Number of read requests accepted -system.physmem.writeReqs 1060156 # Number of write requests accepted -system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1060156 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 132061888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83200 # Total number of bytes read from write queue -system.physmem.bytesWritten 67848256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132145088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67849984 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1300 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 2064027 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2064812 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1060173 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1060173 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 43673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 114832012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 114875685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 43673 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 43673 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 58982658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 58982658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 58982658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 43673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 114832012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 173858343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2064812 # Number of read requests accepted +system.physmem.writeReqs 1060173 # Number of write requests accepted +system.physmem.readBursts 2064812 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1060173 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 132064448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83520 # Total number of bytes read from write queue +system.physmem.bytesWritten 67849344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132147968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67851072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1305 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128524 # Per bank write bursts -system.physmem.perBankRdBursts::1 125801 # Per bank write bursts -system.physmem.perBankRdBursts::2 122666 # Per bank write bursts -system.physmem.perBankRdBursts::3 124575 # Per bank write bursts -system.physmem.perBankRdBursts::4 123572 # Per bank write bursts -system.physmem.perBankRdBursts::5 123680 # Per bank write bursts -system.physmem.perBankRdBursts::6 124357 # Per bank write bursts +system.physmem.perBankRdBursts::0 128530 # Per bank write bursts +system.physmem.perBankRdBursts::1 125798 # Per bank write bursts +system.physmem.perBankRdBursts::2 122667 # Per bank write bursts +system.physmem.perBankRdBursts::3 124564 # Per bank write bursts +system.physmem.perBankRdBursts::4 123583 # Per bank write bursts +system.physmem.perBankRdBursts::5 123689 # Per bank write bursts +system.physmem.perBankRdBursts::6 124368 # Per bank write bursts system.physmem.perBankRdBursts::7 124965 # Per bank write bursts -system.physmem.perBankRdBursts::8 132488 # Per bank write bursts -system.physmem.perBankRdBursts::9 134781 # Per bank write bursts -system.physmem.perBankRdBursts::10 133246 # Per bank write bursts +system.physmem.perBankRdBursts::8 132503 # Per bank write bursts +system.physmem.perBankRdBursts::9 134776 # Per bank write bursts +system.physmem.perBankRdBursts::10 133237 # Per bank write bursts system.physmem.perBankRdBursts::11 134508 # Per bank write bursts -system.physmem.perBankRdBursts::12 134523 # Per bank write bursts -system.physmem.perBankRdBursts::13 134597 # Per bank write bursts -system.physmem.perBankRdBursts::14 130537 # Per bank write bursts -system.physmem.perBankRdBursts::15 130647 # Per bank write bursts -system.physmem.perBankWrBursts::0 66781 # Per bank write bursts -system.physmem.perBankWrBursts::1 64940 # Per bank write bursts -system.physmem.perBankWrBursts::2 63173 # Per bank write bursts -system.physmem.perBankWrBursts::3 63584 # Per bank write bursts -system.physmem.perBankWrBursts::4 63558 # Per bank write bursts -system.physmem.perBankWrBursts::5 63644 # Per bank write bursts -system.physmem.perBankWrBursts::6 65047 # Per bank write bursts -system.physmem.perBankWrBursts::7 66059 # Per bank write bursts -system.physmem.perBankWrBursts::8 67975 # Per bank write bursts -system.physmem.perBankWrBursts::9 68435 # Per bank write bursts -system.physmem.perBankWrBursts::10 68155 # Per bank write bursts -system.physmem.perBankWrBursts::11 68585 # Per bank write bursts -system.physmem.perBankWrBursts::12 68036 # Per bank write bursts -system.physmem.perBankWrBursts::13 68532 # Per bank write bursts -system.physmem.perBankWrBursts::14 67159 # Per bank write bursts +system.physmem.perBankRdBursts::12 134521 # Per bank write bursts +system.physmem.perBankRdBursts::13 134606 # Per bank write bursts +system.physmem.perBankRdBursts::14 130538 # Per bank write bursts +system.physmem.perBankRdBursts::15 130654 # Per bank write bursts +system.physmem.perBankWrBursts::0 66782 # Per bank write bursts +system.physmem.perBankWrBursts::1 64941 # Per bank write bursts +system.physmem.perBankWrBursts::2 63176 # Per bank write bursts +system.physmem.perBankWrBursts::3 63581 # Per bank write bursts +system.physmem.perBankWrBursts::4 63564 # Per bank write bursts +system.physmem.perBankWrBursts::5 63647 # Per bank write bursts +system.physmem.perBankWrBursts::6 65050 # Per bank write bursts +system.physmem.perBankWrBursts::7 66062 # Per bank write bursts +system.physmem.perBankWrBursts::8 67977 # Per bank write bursts +system.physmem.perBankWrBursts::9 68434 # Per bank write bursts +system.physmem.perBankWrBursts::10 68153 # Per bank write bursts +system.physmem.perBankWrBursts::11 68587 # Per bank write bursts +system.physmem.perBankWrBursts::12 68034 # Per bank write bursts +system.physmem.perBankWrBursts::13 68534 # Per bank write bursts +system.physmem.perBankWrBursts::14 67158 # Per bank write bursts system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1150227685500 # Total gap between requests +system.physmem.totGap 1150356195500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2064767 # Read request sizes (log2) +system.physmem.readPktSize::6 2064812 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1060156 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1919511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 143942 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1060173 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1919552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143941 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 62501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62667 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 62593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 62501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 62570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,122 +194,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1927678 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.704158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.827351 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.878363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1497959 77.71% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 310183 16.09% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52221 2.71% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20819 1.08% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1927714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.704114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.833686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.867792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1497696 77.69% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 310699 16.12% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52184 2.71% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20631 1.07% 97.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7800 0.40% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5214 0.27% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5117 0.27% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15291 0.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1927678 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 62183 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.137240 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.854238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 150.737609 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 62144 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::640-767 7807 0.40% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5185 0.27% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5186 0.27% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15252 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1927714 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62200 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.128826 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.842942 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 148.982645 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 62161 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 62183 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 62183 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.048534 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.017369 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.031425 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29894 48.07% 48.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1086 1.75% 49.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 29528 47.49% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1644 2.64% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 62183 # Writes before turning the bus around for reads -system.physmem.totQLat 59946131250 # Total ticks spent queuing -system.physmem.totMemAccLat 98636137500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29051.17 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 62200 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.044148 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.013066 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.029999 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29988 48.21% 48.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1141 1.83% 50.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29436 47.32% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1609 2.59% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 24 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 62200 # Writes before turning the bus around for reads +system.physmem.totQLat 60011294750 # Total ticks spent queuing +system.physmem.totMemAccLat 98702051000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10317535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29082.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47801.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 58.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47832.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 114.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 58.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 114.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 58.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.36 # Data bus utilization in percentage system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing -system.physmem.readRowHits 775435 # Number of row buffer hits during reads -system.physmem.writeRowHits 420473 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes -system.physmem.avgGap 368081.93 # Average gap between requests +system.physmem.avgWrQLen 24.14 # Average write queue length when enqueuing +system.physmem.readRowHits 775182 # Number of row buffer hits during reads +system.physmem.writeRowHits 420747 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.69 # Row buffer hit rate for writes +system.physmem.avgGap 368115.75 # Average gap between requests system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6703938780 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3563201400 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 71587735440.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47610368340 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2598027360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 242891748180 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 71936235360 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 82347779655 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 539087705175 # Total energy per rank (pJ) -system.physmem_0.averagePower 468.679083 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1039000185750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3501543500 # Time in different power states -system.physmem_0.memoryStateTime::REF 30348316000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 319007908000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 187335147250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77377438000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 532657433750 # Time in different power states -system.physmem_1.actEnergy 7059753540 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3752336610 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 6705024060 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3563778240 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7126890960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2697711660 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 71598184320.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47589199680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2602904160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 242927855970 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 71960703840 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 82354339920 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 539151608970 # Total energy per rank (pJ) +system.physmem_0.averagePower 468.682274 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1039160467250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3513710000 # Time in different power states +system.physmem_0.memoryStateTime::REF 30352766000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 319025802500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 187397997250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77329050000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 532736970750 # Time in different power states +system.physmem_1.actEnergy 7058925300 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3751896390 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7606549020 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 71062832880.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47583848520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2430369600 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 248599905450 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 68453747040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 80907358950 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 540315522360 # Total energy per rank (pJ) -system.physmem_1.averagePower 469.746535 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1039499383250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3059154750 # Time in different power states -system.physmem_1.memoryStateTime::REF 30118266000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 316057409750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 178263690250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77550921750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 545178344000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019900 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610401 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131646658 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324616 # Number of BTB hits +system.physmem_1.refreshEnergy 71153184960.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47703954360 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2452947360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 248582355720 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68636874240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 80784488595 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 540590019675 # Total energy per rank (pJ) +system.physmem_1.averagePower 469.932679 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1039304472000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3115835000 # Time in different power states +system.physmem_1.memoryStateTime::REF 30156708000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 315425606000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 178743425250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77779220750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 545135501500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240030332 # Number of BP lookups +system.cpu.branchPred.condPredicted 186613747 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14536765 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132238924 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122337864 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.918892 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.512749 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15662658 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 538 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 306 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -339,7 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,7 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,7 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -430,16 +430,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2300455573 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2300712593 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363694 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41389188 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.489389 # CPI: cycles per instruction -system.cpu.ipc 0.671416 # IPC: instructions per cycle +system.cpu.cpi 1.489556 # CPI: cycles per instruction +system.cpu.ipc 0.671341 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -479,16 +479,16 @@ system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1845015660 # Number of cycles that the object actually ticked -system.cpu.idleCycles 455439913 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9220107 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.805308 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624493167 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks. +system.cpu.tickCycles 1845105384 # Number of cycles that the object actually ticked +system.cpu.idleCycles 455607209 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9220185 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.806447 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624504262 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9224281 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.702216 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805308 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.806447 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -497,43 +497,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391153 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391153 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454163886 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454163886 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170329158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170329158 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277413521 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277413521 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454174952 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454174952 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170329187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170329187 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624493044 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624493044 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624493045 # number of overall hits -system.cpu.dcache.overall_hits::total 624493045 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2256889 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2256889 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624504139 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624504139 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624504140 # number of overall hits +system.cpu.dcache.overall_hits::total 624504140 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7333496 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7333496 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2256860 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2256860 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9590306 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9590306 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9590308 # number of overall misses -system.cpu.dcache.overall_misses::total 9590308 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 208196327000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 208196327000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119903341000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119903341000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 328099668000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 328099668000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 328099668000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 328099668000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497303 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497303 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9590356 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9590356 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9590358 # number of overall misses +system.cpu.dcache.overall_misses::total 9590358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 208281810000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 208281810000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119887020500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119887020500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 328168830500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 328168830500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 328168830500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 328168830500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461508448 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461508448 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -542,64 +542,64 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083350 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083350 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083353 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083353 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634094495 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634094495 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634094498 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634094498 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28390.084322 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28390.084322 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.708540 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.708540 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.595334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34211.595334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.588199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34211.588199 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.015124 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015124 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015124 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015124 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28401.435005 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28401.435005 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53121.159709 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53121.159709 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34218.628641 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34218.628641 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34218.621505 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34218.621505 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3670055 # number of writebacks -system.cpu.dcache.writebacks::total 3670055 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3670078 # number of writebacks +system.cpu.dcache.writebacks::total 3670078 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366055 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 366055 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366104 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366104 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366104 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366104 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890834 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366027 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 366027 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366076 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366076 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366076 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366076 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333447 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333447 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890833 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890833 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200858538000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 200858538000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92467008500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92467008500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9224280 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9224280 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9224281 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9224281 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200943921500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 200943921500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92449770000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92449770000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293325546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 293325546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293325627500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 293325627500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293393691500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 293393691500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293393772500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 293393772500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -610,70 +610,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.671158 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.671158 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.763807 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.763807 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27401.019125 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27401.019125 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48893.672789 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48893.672789 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.558000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.558000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.563334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.563334 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31806.676673 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31806.676673 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31806.682006 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31806.682006 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 33 # number of replacements -system.cpu.icache.tags.tagsinuse 660.477823 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466274758 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 660.481453 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466324528 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567244.231144 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567304.778589 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.477823 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322499 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 660.481453 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322501 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322501 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932551982 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932551982 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466274758 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466274758 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466274758 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466274758 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466274758 # number of overall hits -system.cpu.icache.overall_hits::total 466274758 # number of overall hits +system.cpu.icache.tags.tag_accesses 932651522 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932651522 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466324528 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466324528 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466324528 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466324528 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466324528 # number of overall hits +system.cpu.icache.overall_hits::total 466324528 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses system.cpu.icache.overall_misses::total 822 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 74803000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 74803000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 74803000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 74803000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 74803000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 74803000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466275580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466275580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466275580 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466275580 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466275580 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466275580 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 75338000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 75338000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 75338000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 75338000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 75338000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 75338000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 466325350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466325350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466325350 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466325350 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466325350 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466325350 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91001.216545 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 91001.216545 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 91001.216545 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 91001.216545 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91652.068127 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 91652.068127 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 91652.068127 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 91652.068127 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -688,38 +688,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 822 system.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73981000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 73981000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73981000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 73981000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73981000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 73981000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 74516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 74516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74516000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 74516000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90001.216545 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90001.216545 # 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number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64478000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183639899000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 183704377000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64478000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183639899000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 183704377000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 2064027 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2064812 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70142301500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70142301500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65013000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65013000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113564745500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113564745500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65013000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183707047000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 183772060000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65013000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183707047000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 183772060000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429619 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429619 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170682 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170682 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.223825 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86369.213355 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86369.213355 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.831363 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.831363 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.223825 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86346.202566 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86346.202566 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82819.108280 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82819.108280 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90729.203101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90729.203101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18445321 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220230 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7334270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4730251 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6522313 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890833 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890833 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333448 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668513 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27670190 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668747 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27670424 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825232512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 825287232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2032334 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 67849984 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11257359 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825238976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 825293696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2032379 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 67851072 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11257482 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000271 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.016506 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11254309 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11254432 99.97% 99.97% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 3044 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11257359 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12892670500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11257482 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12892771500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13836307494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13836424993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4095872 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2031262 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 4095962 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2031307 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1252444 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution -system.membus.trans_dist::CleanEvict 970949 # Transaction distribution -system.membus.trans_dist::ReadExReq 812323 # Transaction distribution -system.membus.trans_dist::ReadExResp 812323 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1252444 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160639 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6160639 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 199995072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1252474 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1060173 # Transaction distribution +system.membus.trans_dist::CleanEvict 970977 # Transaction distribution +system.membus.trans_dist::ReadExReq 812338 # Transaction distribution +system.membus.trans_dist::ReadExResp 812338 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1252474 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160774 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6160774 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199999040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 199999040 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2064767 # Request fanout histogram +system.membus.snoop_fanout::samples 2064812 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2064767 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2064812 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2064767 # Request fanout histogram -system.membus.reqLayer0.occupancy 8804919500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2064812 # Request fanout histogram +system.membus.reqLayer0.occupancy 8805297000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11285149250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11285202500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |