diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt | 247 |
1 files changed, 143 insertions, 104 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 1d6a1c5a9..1df40303a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 1.108725 # Nu sim_ticks 1108725388000 # Number of ticks simulated final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243193 # Simulator instruction rate (inst/s) -host_op_rate 262004 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174570169 # Simulator tick rate (ticks/s) -host_mem_usage 311428 # Number of bytes of host memory used -host_seconds 6351.17 # Real time elapsed on the host +host_inst_rate 160331 # Simulator instruction rate (inst/s) +host_op_rate 172733 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115089854 # Simulator tick rate (ticks/s) +host_mem_usage 301444 # Number of bytes of host memory used +host_seconds 9633.56 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131558336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 131507968 # Number of bytes read from this memory system.physmem.bytes_read::total 131558336 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 66970688 # Number of bytes written to this memory system.physmem.bytes_written::total 66970688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2055599 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2054812 # Number of read requests responded to by this memory system.physmem.num_reads::total 2055599 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1046417 # Number of write requests responded to by this memory system.physmem.num_writes::total 1046417 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 118657277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 45429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 118611849 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 118657277 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 45429 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 45429 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 60403314 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 60403314 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 60403314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 118657277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 118611849 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 179060592 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 2055599 # Number of read requests accepted system.physmem.writeReqs 1046417 # Number of write requests accepted @@ -423,8 +427,8 @@ system.cpu.dcache.tags.total_refs 624087400 # To system.cpu.dcache.tags.sampled_refs 9227820 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.631076 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.606596 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997463 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.606596 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997463 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id @@ -434,61 +438,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1276555670 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1276555670 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 453740634 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 453740634 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 453740634 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 170346644 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170346644 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 170346644 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 624087278 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 624087278 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 624087278 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 624087278 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 624087278 # number of overall hits system.cpu.dcache.overall_hits::total 624087278 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7337122 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 7337122 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7337122 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2239403 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2239403 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2239403 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9576525 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 9576525 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 9576525 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9576525 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 9576525 # number of overall misses system.cpu.dcache.overall_misses::total 9576525 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183400270746 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 183400270746 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 183400270746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101399706750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 101399706750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 101399706750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 284799977496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 284799977496 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 284799977496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 284799977496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 284799977496 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 284799977496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 461077756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 461077756 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 461077756 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 633663803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633663803 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 633663803 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 633663803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633663803 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 633663803 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015913 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012976 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012976 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015113 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015113 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015113 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015113 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015113 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015113 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24996.213876 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24996.213876 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45279.794101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45279.794101 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 29739.386416 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 29739.386416 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -500,45 +504,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3701129 # number of writebacks system.cpu.dcache.writebacks::total 3701129 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 221 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 221 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348484 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 348484 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 348484 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 348705 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 348705 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 348705 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 348705 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 348705 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 348705 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336901 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336901 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7336901 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890919 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890919 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1890919 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9227820 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9227820 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 9227820 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9227820 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9227820 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9227820 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168309061254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168309061254 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 168309061254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77322111500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77322111500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 77322111500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245631172754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245631172754 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 245631172754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245631172754 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245631172754 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 245631172754 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015913 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22940.075279 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22940.075279 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22940.075279 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40891.286988 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40891.286988 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40891.286988 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26618.548341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26618.548341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements @@ -633,9 +637,11 @@ system.cpu.l2cache.tags.sampled_refs 2052670 # Sa system.cpu.l2cache.tags.avg_refs 4.377444 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 59502848750 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 14999.285776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 16254.854737 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.862616 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16227.992121 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.457742 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496059 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000820 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.495239 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.953801 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id @@ -646,57 +652,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 107381741 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 107381741 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6082213 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6082181 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6082213 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3701129 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 3701129 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090823 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1090823 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1090823 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7173036 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7173004 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 7173036 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7173036 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7173004 # 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number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 788 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2054816 # number of overall misses system.cpu.l2cache.overall_misses::total 2055604 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100200408000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55257250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 100145150750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 100200408000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64467346000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64467346000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 64467346000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 164667754000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 55257250 # 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number of cycles access was blocked @@ -708,43 +732,58 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1046417 # number of writebacks system.cpu.l2cache.writebacks::total 1046417 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # 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Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution |