diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt | 981 |
1 files changed, 496 insertions, 485 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index ddbab1eb8..16fb45e1d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.130744 # Number of seconds simulated -sim_ticks 1130744162500 # Number of ticks simulated -final_tick 1130744162500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.150226 # Number of seconds simulated +sim_ticks 1150225722500 # Number of ticks simulated +final_tick 1150225722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210155 # Simulator instruction rate (inst/s) -host_op_rate 226410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153850224 # Simulator tick rate (ticks/s) -host_mem_usage 274312 # Number of bytes of host memory used -host_seconds 7349.64 # Real time elapsed on the host +host_inst_rate 267770 # Simulator instruction rate (inst/s) +host_op_rate 288482 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 199406485 # Simulator tick rate (ticks/s) +host_mem_usage 271372 # Number of bytes of host memory used +host_seconds 5768.25 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132094976 # Number of bytes read from this memory -system.physmem.bytes_read::total 132145216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory +system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67850112 # Number of bytes written to this memory -system.physmem.bytes_written::total 67850112 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67849984 # Number of bytes written to this memory +system.physmem.bytes_written::total 67849984 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2063984 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2064769 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1060158 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1060158 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 44431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 116821276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116865707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 44431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 44431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60004831 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60004831 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60004831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 44431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 116821276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 176870538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2064769 # Number of read requests accepted -system.physmem.writeReqs 1060158 # Number of write requests accepted -system.physmem.readBursts 2064769 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1060158 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 132060352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84864 # Total number of bytes read from write queue -system.physmem.bytesWritten 67848640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132145216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67850112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1326 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 2063982 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2064767 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 114842544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 114886222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 58988408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 58988408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 58988408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 114842544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 173874630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2064767 # Number of read requests accepted +system.physmem.writeReqs 1060156 # Number of write requests accepted +system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1060156 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 132061888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83200 # Total number of bytes read from write queue +system.physmem.bytesWritten 67848256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132145088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67849984 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1300 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128520 # Per bank write bursts -system.physmem.perBankRdBursts::1 125806 # Per bank write bursts -system.physmem.perBankRdBursts::2 122672 # Per bank write bursts -system.physmem.perBankRdBursts::3 124571 # Per bank write bursts +system.physmem.perBankRdBursts::0 128524 # Per bank write bursts +system.physmem.perBankRdBursts::1 125801 # Per bank write bursts +system.physmem.perBankRdBursts::2 122666 # Per bank write bursts +system.physmem.perBankRdBursts::3 124575 # Per bank write bursts system.physmem.perBankRdBursts::4 123572 # Per bank write bursts -system.physmem.perBankRdBursts::5 123679 # Per bank write bursts -system.physmem.perBankRdBursts::6 124365 # Per bank write bursts -system.physmem.perBankRdBursts::7 124958 # Per bank write bursts -system.physmem.perBankRdBursts::8 132489 # Per bank write bursts -system.physmem.perBankRdBursts::9 134780 # Per bank write bursts -system.physmem.perBankRdBursts::10 133233 # Per bank write bursts -system.physmem.perBankRdBursts::11 134506 # Per bank write bursts -system.physmem.perBankRdBursts::12 134518 # Per bank write bursts -system.physmem.perBankRdBursts::13 134594 # Per bank write bursts -system.physmem.perBankRdBursts::14 130540 # Per bank write bursts -system.physmem.perBankRdBursts::15 130640 # Per bank write bursts +system.physmem.perBankRdBursts::5 123680 # Per bank write bursts +system.physmem.perBankRdBursts::6 124357 # Per bank write bursts +system.physmem.perBankRdBursts::7 124965 # Per bank write bursts +system.physmem.perBankRdBursts::8 132488 # Per bank write bursts +system.physmem.perBankRdBursts::9 134781 # Per bank write bursts +system.physmem.perBankRdBursts::10 133246 # Per bank write bursts +system.physmem.perBankRdBursts::11 134508 # Per bank write bursts +system.physmem.perBankRdBursts::12 134524 # Per bank write bursts +system.physmem.perBankRdBursts::13 134597 # Per bank write bursts +system.physmem.perBankRdBursts::14 130537 # Per bank write bursts +system.physmem.perBankRdBursts::15 130646 # Per bank write bursts system.physmem.perBankWrBursts::0 66781 # Per bank write bursts -system.physmem.perBankWrBursts::1 64941 # Per bank write bursts +system.physmem.perBankWrBursts::1 64940 # Per bank write bursts system.physmem.perBankWrBursts::2 63173 # Per bank write bursts system.physmem.perBankWrBursts::3 63584 # Per bank write bursts system.physmem.perBankWrBursts::4 63558 # Per bank write bursts system.physmem.perBankWrBursts::5 63644 # Per bank write bursts system.physmem.perBankWrBursts::6 65047 # Per bank write bursts -system.physmem.perBankWrBursts::7 66055 # Per bank write bursts -system.physmem.perBankWrBursts::8 67972 # Per bank write bursts -system.physmem.perBankWrBursts::9 68438 # Per bank write bursts -system.physmem.perBankWrBursts::10 68161 # Per bank write bursts -system.physmem.perBankWrBursts::11 68586 # Per bank write bursts -system.physmem.perBankWrBursts::12 68040 # Per bank write bursts -system.physmem.perBankWrBursts::13 68530 # Per bank write bursts +system.physmem.perBankWrBursts::7 66059 # Per bank write bursts +system.physmem.perBankWrBursts::8 67975 # Per bank write bursts +system.physmem.perBankWrBursts::9 68435 # Per bank write bursts +system.physmem.perBankWrBursts::10 68155 # Per bank write bursts +system.physmem.perBankWrBursts::11 68585 # Per bank write bursts +system.physmem.perBankWrBursts::12 68036 # Per bank write bursts +system.physmem.perBankWrBursts::13 68532 # Per bank write bursts system.physmem.perBankWrBursts::14 67159 # Per bank write bursts system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1130744067500 # Total gap between requests +system.physmem.totGap 1150225621500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2064769 # Read request sizes (log2) +system.physmem.readPktSize::6 2064767 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1060158 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1931837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131592 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1060156 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1919491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143962 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 62386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 62484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 62514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 62444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,103 +194,114 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1925169 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.839212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.850367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 126.421931 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1496084 77.71% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 309482 16.08% 93.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52255 2.71% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20716 1.08% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12793 0.66% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7748 0.40% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5753 0.30% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5054 0.26% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15284 0.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1925169 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61990 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.244314 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.928422 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 148.698604 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61952 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 16 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1927680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.704050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.827428 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.877785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1497957 77.71% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 310202 16.09% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52219 2.71% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20801 1.08% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13076 0.68% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7806 0.40% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5210 0.27% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5119 0.27% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15290 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1927680 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.137773 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.854622 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 150.738788 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 62143 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::17408-18431 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61990 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.101710 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.070337 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.034747 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 28322 45.69% 45.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1015 1.64% 47.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 30732 49.58% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1873 3.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 43 0.07% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61990 # Writes before turning the bus around for reads -system.physmem.totQLat 38536102500 # Total ticks spent queuing -system.physmem.totMemAccLat 77225658750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10317215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18675.63 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 62182 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62182 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.048808 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.017651 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.031288 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29885 48.06% 48.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1078 1.73% 49.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29552 47.53% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1636 2.63% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 62182 # Writes before turning the bus around for reads +system.physmem.totQLat 59945214750 # Total ticks spent queuing +system.physmem.totMemAccLat 98635221000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29050.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37425.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 116.79 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 60.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.87 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.00 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47800.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 58.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.38 # Data bus utilization in percentage -system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.36 # Data bus utilization in percentage +system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing -system.physmem.readRowHits 775929 # Number of row buffer hits during reads -system.physmem.writeRowHits 422476 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.85 # Row buffer hit rate for writes -system.physmem.avgGap 361846.55 # Average gap between requests -system.physmem.pageHitRate 38.37 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7091695800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3869476875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7785421800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3348753840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 423921506085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 306584736000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 826456199280 # Total energy per rank (pJ) -system.physmem_0.averagePower 730.896688 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 507283799000 # Time in different power states -system.physmem_0.memoryStateTime::REF 37757980000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 585701078500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7462581840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4071845250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8309316600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3520920960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 432965070225 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 298651785000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 828836128755 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.001436 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 494051909000 # Time in different power states -system.physmem_1.memoryStateTime::REF 37757980000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 598934101500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019432 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610009 # Number of conditional branches predicted +system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing +system.physmem.readRowHits 775403 # Number of row buffer hits during reads +system.physmem.writeRowHits 420503 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes +system.physmem.avgGap 368081.27 # Average gap between requests +system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6704024460 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3563246940 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 71584047600.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47598370410 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2598119520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 242886973860 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 71929585440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 82360762695 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 539073775965 # Total energy per rank (pJ) +system.physmem_0.averagePower 468.667814 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1039023905500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3501879500 # Time in different power states +system.physmem_0.memoryStateTime::REF 30346756000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 319059811750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 187317352250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77352878250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 532647044750 # Time in different power states +system.physmem_1.actEnergy 7059682140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3752298660 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 71064062160.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47576528010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2430223200 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 248601681570 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68458810560 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 80907988260 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 540316908180 # Total energy per rank (pJ) +system.physmem_1.averagePower 469.748583 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1039511813000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3059644000 # Time in different power states +system.physmem_1.memoryStateTime::REF 30118792000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 316054273750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 178278810500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77535412750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 545178789500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240019882 # Number of BP lookups +system.cpu.branchPred.condPredicted 186610383 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131647101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324380 # Number of BTB hits +system.cpu.branchPred.BTBLookups 131646647 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122324605 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.918400 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.918891 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. @@ -298,7 +309,7 @@ system.cpu.branchPred.indirectHits 232 # Nu system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -328,7 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,7 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -388,7 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,16 +430,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2261488325 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2300451445 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363718 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41363683 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.464161 # CPI: cycles per instruction -system.cpu.ipc 0.682985 # IPC: instructions per cycle +system.cpu.cpi 1.489387 # CPI: cycles per instruction +system.cpu.ipc 0.671417 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -464,61 +475,61 @@ system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1844743027 # Number of cycles that the object actually ticked -system.cpu.idleCycles 416745298 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9220102 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.712457 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624495296 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9224198 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.701853 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9823555500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.712457 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997488 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997488 # Average percentage of cache occupancy +system.cpu.tickCycles 1845014986 # Number of cycles that the object actually ticked +system.cpu.idleCycles 455436459 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9220107 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.805290 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624493165 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805290 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391740 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391740 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454164183 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454164183 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170330990 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170330990 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277391151 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277391151 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454163885 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454163885 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170329157 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170329157 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624495173 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624495173 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624495174 # number of overall hits -system.cpu.dcache.overall_hits::total 624495174 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7333416 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7333416 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2255057 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2255057 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624493042 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624493042 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624493043 # number of overall hits +system.cpu.dcache.overall_hits::total 624493043 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2256890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2256890 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9588473 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9588473 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9588475 # number of overall misses -system.cpu.dcache.overall_misses::total 9588475 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 192638967000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 192638967000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 111261397000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 111261397000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 303900364000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 303900364000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 303900364000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 303900364000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497599 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9590307 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9590307 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9590309 # number of overall misses +system.cpu.dcache.overall_misses::total 9590309 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 208195707500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 208195707500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119902321500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119902321500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 328098029000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 328098029000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 328098029000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 328098029000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461497302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461497302 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -527,64 +538,64 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083646 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083646 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083649 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083649 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634083349 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634083349 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634083352 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634083352 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015122 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015122 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015122 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015122 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26268.653926 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26268.653926 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49338.618492 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49338.618492 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31694.344240 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31694.344240 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31694.337629 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31694.337629 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28389.999846 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28389.999846 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.233272 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.233272 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.420865 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34211.420865 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.413730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34211.413730 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3670051 # number of writebacks -system.cpu.dcache.writebacks::total 3670051 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3670055 # number of writebacks +system.cpu.dcache.writebacks::total 3670055 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364227 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364227 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364276 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364276 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364276 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364276 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333367 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333367 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890830 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890830 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366056 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 366056 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366105 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366105 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366105 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366105 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890834 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9224197 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9224197 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9224198 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9224198 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 185303496000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 185303496000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86626211500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86626211500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 271929707500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 271929707500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 271929782500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 271929782500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200857919000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 200857919000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92466638500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92466638500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293324557500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 293324557500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293324638500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 293324638500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -595,70 +606,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25268.542540 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25268.542540 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45813.855027 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45813.855027 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29480.041189 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29480.041189 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29480.046124 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29480.046124 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.586749 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.586749 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.568126 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.568126 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.450782 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.450782 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.456116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.456116 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 33 # number of replacements -system.cpu.icache.tags.tagsinuse 660.343836 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466264831 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 660.478132 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466274661 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567232.154501 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567244.113139 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.343836 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322434 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322434 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 660.478132 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322499 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932532128 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932532128 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466264831 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466264831 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466264831 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466264831 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466264831 # number of overall hits -system.cpu.icache.overall_hits::total 466264831 # number of overall hits +system.cpu.icache.tags.tag_accesses 932551788 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932551788 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466274661 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466274661 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466274661 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466274661 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466274661 # number of overall hits +system.cpu.icache.overall_hits::total 466274661 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses system.cpu.icache.overall_misses::total 822 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62977000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62977000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62977000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62977000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62977000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62977000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466265653 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466265653 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466265653 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466265653 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466265653 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466265653 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 74803000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 74803000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 74803000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 74803000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 74803000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 74803000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 466275483 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466275483 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466275483 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466275483 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466275483 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466275483 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76614.355231 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76614.355231 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76614.355231 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76614.355231 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91001.216545 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 91001.216545 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 91001.216545 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 91001.216545 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,106 +684,106 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 822 system.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62155000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 62155000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62155000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 62155000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62155000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 62155000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73981000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 73981000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73981000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 73981000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73981000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 73981000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # 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Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16378248 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2065102 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.930963 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 10.372188 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.927867 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000317 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000779 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.972288 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.973384 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 912 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2876 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7195 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21737 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 831 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2946 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7191 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21752 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149613593 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162242977000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 162295628000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52651000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162242977000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 162295628000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 2063982 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2064767 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159329500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159329500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64478000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64478000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113479586000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113479586000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64478000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183638915500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 183703393500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64478000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183638915500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 183703393500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429612 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429611 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.223823 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.223823 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79177.093746 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79177.093746 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67071.337580 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67071.337580 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78236.520701 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78236.520701 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18445155 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220147 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86368.759102 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86368.759102 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.340415 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.340415 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1445 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7334190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4730209 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890834 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333369 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27670175 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668513 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27670190 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825231936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 825286656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2032337 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 67850112 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11257357 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.016509 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825232512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 825287232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2032334 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 67849984 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11257359 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000271 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.016506 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11254306 99.97% 99.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3045 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11254309 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3044 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11257357 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12892661500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11257359 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12892670500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13836299994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13836307494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4095876 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2031264 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 4095872 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2031262 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1252445 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1060158 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1252444 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution system.membus.trans_dist::CleanEvict 970949 # Transaction distribution -system.membus.trans_dist::ReadExReq 812324 # Transaction distribution -system.membus.trans_dist::ReadExResp 812324 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1252445 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160645 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6160645 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 199995328 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 812323 # Transaction distribution +system.membus.trans_dist::ReadExResp 812323 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1252444 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160639 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6160639 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 199995072 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2064769 # Request fanout histogram +system.membus.snoop_fanout::samples 2064767 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2064769 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2064767 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2064769 # Request fanout histogram -system.membus.reqLayer0.occupancy 8803577000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2064767 # Request fanout histogram +system.membus.reqLayer0.occupancy 8804910500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11289358000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11285155750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |