diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/minor-timing')
4 files changed, 0 insertions, 1984 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini deleted file mode 100644 index 7df53f247..000000000 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini +++ /dev/null @@ -1,997 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2 -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr deleted file mode 100755 index caeab8324..000000000 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr +++ /dev/null @@ -1,4 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout deleted file mode 100755 index b95f9cdb7..000000000 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout +++ /dev/null @@ -1,30 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:43:01 -gem5 executing on e108600-lin, pid 17341 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 1150225722500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt deleted file mode 100644 index 24c0fbbea..000000000 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ /dev/null @@ -1,953 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.150356 # Number of seconds simulated -sim_ticks 1150356296500 # Number of ticks simulated -final_tick 1150356296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 374766 # Simulator instruction rate (inst/s) -host_op_rate 403753 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 279117141 # Simulator tick rate (ticks/s) -host_mem_usage 273688 # Number of bytes of host memory used -host_seconds 4121.41 # Real time elapsed on the host -sim_insts 1544563088 # Number of instructions simulated -sim_ops 1664032481 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132097728 # Number of bytes read from this memory -system.physmem.bytes_read::total 132147968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67851072 # Number of bytes written to this memory -system.physmem.bytes_written::total 67851072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2064027 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2064812 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1060173 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1060173 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 43673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 114832012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 114875685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 43673 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 43673 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 58982658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 58982658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 58982658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 43673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 114832012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 173858343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2064812 # Number of read requests accepted -system.physmem.writeReqs 1060173 # Number of write requests accepted -system.physmem.readBursts 2064812 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1060173 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 132064448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83520 # Total number of bytes read from write queue -system.physmem.bytesWritten 67849344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132147968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67851072 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1305 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128530 # Per bank write bursts -system.physmem.perBankRdBursts::1 125798 # Per bank write bursts -system.physmem.perBankRdBursts::2 122667 # Per bank write bursts -system.physmem.perBankRdBursts::3 124564 # Per bank write bursts -system.physmem.perBankRdBursts::4 123583 # Per bank write bursts -system.physmem.perBankRdBursts::5 123689 # Per bank write bursts -system.physmem.perBankRdBursts::6 124368 # Per bank write bursts -system.physmem.perBankRdBursts::7 124965 # Per bank write bursts -system.physmem.perBankRdBursts::8 132503 # Per bank write bursts -system.physmem.perBankRdBursts::9 134776 # Per bank write bursts -system.physmem.perBankRdBursts::10 133237 # Per bank write bursts -system.physmem.perBankRdBursts::11 134508 # Per bank write bursts -system.physmem.perBankRdBursts::12 134521 # Per bank write bursts -system.physmem.perBankRdBursts::13 134606 # Per bank write bursts -system.physmem.perBankRdBursts::14 130538 # Per bank write bursts -system.physmem.perBankRdBursts::15 130654 # Per bank write bursts -system.physmem.perBankWrBursts::0 66782 # Per bank write bursts -system.physmem.perBankWrBursts::1 64941 # Per bank write bursts -system.physmem.perBankWrBursts::2 63176 # Per bank write bursts -system.physmem.perBankWrBursts::3 63581 # Per bank write bursts -system.physmem.perBankWrBursts::4 63564 # Per bank write bursts -system.physmem.perBankWrBursts::5 63647 # Per bank write bursts -system.physmem.perBankWrBursts::6 65050 # Per bank write bursts -system.physmem.perBankWrBursts::7 66062 # Per bank write bursts -system.physmem.perBankWrBursts::8 67977 # Per bank write bursts -system.physmem.perBankWrBursts::9 68434 # Per bank write bursts -system.physmem.perBankWrBursts::10 68153 # Per bank write bursts -system.physmem.perBankWrBursts::11 68587 # Per bank write bursts -system.physmem.perBankWrBursts::12 68034 # Per bank write bursts -system.physmem.perBankWrBursts::13 68534 # Per bank write bursts -system.physmem.perBankWrBursts::14 67158 # Per bank write bursts -system.physmem.perBankWrBursts::15 66466 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1150356195500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2064812 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1060173 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1919552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 143941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1927714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.704114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.833686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.867792 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1497696 77.69% 77.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 310699 16.12% 93.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52184 2.71% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20631 1.07% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7807 0.40% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5185 0.27% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5186 0.27% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15252 0.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1927714 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 62200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.128826 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.842942 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 148.982645 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 62161 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 62200 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 62200 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.044148 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.013066 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.029999 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29988 48.21% 48.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1141 1.83% 50.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 29436 47.32% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1609 2.59% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 24 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 62200 # Writes before turning the bus around for reads -system.physmem.totQLat 60011294750 # Total ticks spent queuing -system.physmem.totMemAccLat 98702051000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10317535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29082.19 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47832.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 114.80 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 58.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 114.88 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 58.98 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.36 # Data bus utilization in percentage -system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.14 # Average write queue length when enqueuing -system.physmem.readRowHits 775182 # Number of row buffer hits during reads -system.physmem.writeRowHits 420747 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.69 # Row buffer hit rate for writes -system.physmem.avgGap 368115.75 # Average gap between requests -system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6705024060 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3563778240 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7126890960 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2697711660 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 71598184320.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47589199680 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2602904160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 242927855970 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 71960703840 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 82354339920 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 539151608970 # Total energy per rank (pJ) -system.physmem_0.averagePower 468.682274 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1039160467250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3513710000 # Time in different power states -system.physmem_0.memoryStateTime::REF 30352766000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 319025802500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 187397997250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77329050000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 532736970750 # Time in different power states -system.physmem_1.actEnergy 7058925300 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3751896390 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7606549020 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 71153184960.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47703954360 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2452947360 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 248582355720 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 68636874240 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 80784488595 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 540590019675 # Total energy per rank (pJ) -system.physmem_1.averagePower 469.932679 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1039304472000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3115835000 # Time in different power states -system.physmem_1.memoryStateTime::REF 30156708000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 315425606000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 178743425250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77779220750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 545135501500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240030332 # Number of BP lookups -system.cpu.branchPred.condPredicted 186613747 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14536765 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132238924 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122337864 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.512749 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15662658 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 538 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 306 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2300712593 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1544563088 # Number of instructions committed -system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41389188 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.489556 # CPI: cycles per instruction -system.cpu.ipc 0.671341 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction -system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction -system.cpu.op_class_0::MemWrite 174847022 10.51% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1845105384 # Number of cycles that the object actually ticked -system.cpu.idleCycles 455607209 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9220185 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.806447 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624504262 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9224281 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.702216 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.806447 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277413521 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277413521 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454174952 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454174952 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170329187 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170329187 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624504139 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624504139 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624504140 # number of overall hits -system.cpu.dcache.overall_hits::total 624504140 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7333496 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7333496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2256860 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2256860 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9590356 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9590356 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9590358 # number of overall misses -system.cpu.dcache.overall_misses::total 9590358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 208281810000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 208281810000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119887020500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119887020500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 328168830500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 328168830500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 328168830500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 328168830500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461508448 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461508448 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634094495 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634094495 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634094498 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634094498 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015124 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015124 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015124 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015124 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28401.435005 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28401.435005 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53121.159709 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53121.159709 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34218.628641 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34218.628641 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34218.621505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34218.621505 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3670078 # number of writebacks -system.cpu.dcache.writebacks::total 3670078 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366027 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 366027 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366076 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366076 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366076 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366076 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333447 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333447 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890833 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890833 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9224280 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9224280 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9224281 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9224281 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200943921500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 200943921500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92449770000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92449770000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293393691500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 293393691500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293393772500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 293393772500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27401.019125 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27401.019125 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48893.672789 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48893.672789 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31806.676673 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31806.676673 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31806.682006 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31806.682006 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 33 # number of replacements -system.cpu.icache.tags.tagsinuse 660.481453 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466324528 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567304.778589 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.481453 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322501 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322501 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932651522 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932651522 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466324528 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466324528 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466324528 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466324528 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466324528 # number of overall hits -system.cpu.icache.overall_hits::total 466324528 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses -system.cpu.icache.overall_misses::total 822 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 75338000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 75338000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 75338000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 75338000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 75338000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 75338000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466325350 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466325350 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466325350 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466325350 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466325350 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466325350 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91652.068127 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 91652.068127 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 91652.068127 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 91652.068127 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 33 # number of writebacks -system.cpu.icache.writebacks::total 33 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 822 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 822 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 822 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74516000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 74516000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74516000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 74516000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74516000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 74516000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90652.068127 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90652.068127 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90652.068127 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 90652.068127 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90652.068127 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 90652.068127 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 2032379 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31895.934748 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16378358 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2065147 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.930844 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10.372068 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.532774 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31860.029906 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000317 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000779 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.972291 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.973387 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 831 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2946 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7191 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21752 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149614963 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149614963 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3670078 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3670078 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1078495 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1078495 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 37 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 37 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6081752 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6081752 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7160247 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7160284 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7160247 # number of overall hits -system.cpu.l2cache.overall_hits::total 7160284 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 812338 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 812338 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 785 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 785 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1251696 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1251696 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 785 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2064034 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2064819 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2064034 # number of overall misses -system.cpu.l2cache.overall_misses::total 2064819 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78265681500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 78265681500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72863000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 72863000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 126082122000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 126082122000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 72863000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 204347803500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 204420666500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 72863000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 204347803500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 204420666500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3670078 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3670078 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890833 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1890833 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 822 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 822 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7333448 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7333448 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 822 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9224281 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9225103 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 822 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9224281 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9225103 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.429619 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.429619 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.954988 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.954988 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.170683 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.170683 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.954988 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223761 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.223826 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223761 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.223826 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96346.202566 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96346.202566 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92819.108280 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92819.108280 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100729.028454 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100729.028454 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92819.108280 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99004.087869 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 99001.736472 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92819.108280 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99004.087869 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 99001.736472 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1060173 # number of writebacks -system.cpu.l2cache.writebacks::total 1060173 # number of writebacks -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 7 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 7 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 215 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 215 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812338 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 812338 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 785 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 785 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251689 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251689 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2064027 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2064812 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2064027 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2064812 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70142301500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70142301500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65013000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65013000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113564745500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113564745500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65013000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183707047000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 183772060000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65013000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183707047000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 183772060000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429619 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429619 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170682 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170682 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.223825 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.223825 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86346.202566 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86346.202566 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82819.108280 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82819.108280 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90729.203101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90729.203101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18445321 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220230 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7334270 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4730251 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6522313 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890833 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890833 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333448 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668747 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27670424 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825238976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 825293696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2032379 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 67851072 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11257482 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000271 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.016506 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11254432 99.97% 99.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3044 0.03% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11257482 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12892771500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13836424993 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4095962 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2031307 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1252474 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1060173 # Transaction distribution -system.membus.trans_dist::CleanEvict 970977 # Transaction distribution -system.membus.trans_dist::ReadExReq 812338 # Transaction distribution -system.membus.trans_dist::ReadExResp 812338 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1252474 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160774 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6160774 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199999040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 199999040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2064812 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2064812 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2064812 # Request fanout histogram -system.membus.reqLayer0.occupancy 8805297000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11285202500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |