diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 1334 |
1 files changed, 668 insertions, 666 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index a3e0cc680..21ff71fb2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.473434 # Number of seconds simulated -sim_ticks 473433799500 # Number of ticks simulated -final_tick 473433799500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.515058 # Number of seconds simulated +sim_ticks 515058060000 # Number of ticks simulated +final_tick 515058060000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169995 # Simulator instruction rate (inst/s) -host_op_rate 189642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52106394 # Simulator tick rate (ticks/s) -host_mem_usage 499160 # Number of bytes of host memory used -host_seconds 9085.91 # Real time elapsed on the host -sim_insts 1544563083 # Number of instructions simulated -sim_ops 1723073895 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156296704 # Number of bytes read from this memory -system.physmem.bytes_read::total 156345088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71931712 # Number of bytes written to this memory -system.physmem.bytes_written::total 71931712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 756 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2442136 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2442892 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1123933 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1123933 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 102198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330134232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 330236430 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 102198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 102198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 151936157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 151936157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 151936157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 102198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330134232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 482172587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2442892 # Total number of read requests seen -system.physmem.writeReqs 1123933 # Total number of write requests seen -system.physmem.cpureqs 3566825 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 156345088 # Total number of bytes read from memory -system.physmem.bytesWritten 71931712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 156345088 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 71931712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1286 # Number of read reqs serviced by write Q +host_inst_rate 166099 # Simulator instruction rate (inst/s) +host_op_rate 185296 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55388247 # Simulator tick rate (ticks/s) +host_mem_usage 494292 # Number of bytes of host memory used +host_seconds 9299.05 # Real time elapsed on the host +sim_insts 1544563078 # Number of instructions simulated +sim_ops 1723073890 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 144392128 # Number of bytes read from this memory +system.physmem.bytes_read::total 144440448 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70617600 # Number of bytes written to this memory +system.physmem.bytes_written::total 70617600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2256127 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2256882 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1103400 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1103400 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 280341459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 280435274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 137106096 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 137106096 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 137106096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 280341459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 417541370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2256882 # Total number of read requests seen +system.physmem.writeReqs 1103400 # Total number of write requests seen +system.physmem.cpureqs 3360282 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 144440448 # Total number of bytes read from memory +system.physmem.bytesWritten 70617600 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 144440448 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70617600 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 637 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 151934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 156031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 154856 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 153024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 150249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 152372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 153472 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 154746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 153379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 151879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 152199 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 152305 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 150118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 153271 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 150713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 151058 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 70393 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 72288 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 71658 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 69978 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 69490 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 69799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 70024 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 70449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 69754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 69615 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 69971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 69698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 68976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 71736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 70217 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69887 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 140407 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 144367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 142491 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141453 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 138510 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 140931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 142120 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 141749 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 141832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 140373 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140948 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 141413 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 137790 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 141680 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 139536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 140645 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 70506 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69820 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 68968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 67927 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68673 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 68853 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68680 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 68439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 68530 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 68800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 68663 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 67351 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70531 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 69216 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69077 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 473433771000 # Total gap between requests +system.physmem.totGap 515058007000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2442892 # Categorize read packet sizes +system.physmem.readPktSize::6 2256882 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1123933 # categorize write packet sizes +system.physmem.writePktSize::6 1103400 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1613567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 411043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 122672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 76227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 63723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 50754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 28949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 23035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 15102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1580398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 450395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 158442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 66982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,60 +138,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 46512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 48422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 48759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 48833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 48858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 48865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 39045821973 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 121584903973 # Sum of mem lat for all requests -system.physmem.totBusLat 9766424000 # Total cycles spent in databus access -system.physmem.totBankLat 72772658000 # Total cycles spent in bank access -system.physmem.avgQLat 15991.86 # Average queueing delay per request -system.physmem.avgBankLat 29805.24 # Average bank access latency per request +system.physmem.totQLat 27231628654 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 103251704654 # Sum of mem lat for all requests +system.physmem.totBusLat 9024980000 # Total cycles spent in databus access +system.physmem.totBankLat 66995096000 # Total cycles spent in bank access +system.physmem.avgQLat 12069.45 # Average queueing delay per request +system.physmem.avgBankLat 29693.18 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 49797.10 # Average memory access latency -system.physmem.avgRdBW 330.24 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 151.94 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 330.24 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 151.94 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 45762.63 # Average memory access latency +system.physmem.avgRdBW 280.44 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 137.11 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 280.44 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 137.11 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.01 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.26 # Average read queue length over time -system.physmem.avgWrQLen 10.90 # Average write queue length over time -system.physmem.readRowHits 966664 # Number of row buffer hits during reads -system.physmem.writeRowHits 336338 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.93 # Row buffer hit rate for writes -system.physmem.avgGap 132732.55 # Average gap between requests +system.physmem.busUtil 2.61 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.20 # Average read queue length over time +system.physmem.avgWrQLen 11.32 # Average write queue length over time +system.physmem.readRowHits 919391 # Number of row buffer hits during reads +system.physmem.writeRowHits 189315 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 17.16 # Row buffer hit rate for writes +system.physmem.avgGap 153278.21 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,140 +235,142 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 946867600 # number of cpu cycles simulated +system.cpu.numCycles 1030116121 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 299593765 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 245452602 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16045022 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 170764551 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155662191 # Number of BTB hits +system.cpu.BPredUnit.lookups 307748972 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 253170818 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16168830 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 178836343 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 162524431 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18346296 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 201 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 291830558 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2150759454 # Number of instructions fetch has processed -system.cpu.fetch.Branches 299593765 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174008487 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 427702866 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 82463506 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 122599229 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 282801731 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5377782 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 908156186 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.634401 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.243337 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18394581 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 234 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 302711500 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2208582342 # Number of instructions fetch has processed +system.cpu.fetch.Branches 307748972 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 180919012 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 439713036 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 91477277 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 153604124 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 69 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 292882660 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6106896 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 969047070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.529561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.216174 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 480453401 52.90% 52.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 22859151 2.52% 55.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38736937 4.27% 59.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47688218 5.25% 64.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40498646 4.46% 69.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46746329 5.15% 74.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38999717 4.29% 78.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18064778 1.99% 80.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174109009 19.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 529334144 54.62% 54.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25043926 2.58% 57.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39264186 4.05% 61.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48337631 4.99% 66.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43062270 4.44% 70.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 47882627 4.94% 75.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39313310 4.06% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19335068 2.00% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 177473908 18.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 908156186 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316405 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.271447 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 320351849 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 103310609 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403372314 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15098642 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 66022772 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46034722 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2339352792 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2529 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 66022772 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 341796573 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 48717971 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14906 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 395855837 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55748127 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2282794185 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 39847 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4611517 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42695661 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2257537981 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10537280026 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10537275559 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4467 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706320026 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 551217955 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 838 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 835 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 129599333 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 622569059 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 218142237 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 84983278 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 64739003 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2182778805 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 865 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2010794421 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4810108 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 455220170 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1060725588 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 683 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 908156186 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.214150 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.929063 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 969047070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.298752 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.144013 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 334775915 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 131820236 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 409429631 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20003640 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 73017648 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46459880 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 721 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2395467722 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2521 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 73017648 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 358478616 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61310545 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17059 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 404218624 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 72004578 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2331266224 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 128849 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5208113 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58805545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2308002536 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10761064902 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10761060796 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4106 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706320018 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 601682518 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1074 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1071 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160130696 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 634128265 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 221560674 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 87711423 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 69100091 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2223438682 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1093 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2032725138 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5162970 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 495697928 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1172411676 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 912 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 969047070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.097654 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906175 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 247277493 27.23% 27.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 133932127 14.75% 41.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 156228000 17.20% 59.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 116195915 12.79% 71.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125706835 13.84% 85.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75923793 8.36% 94.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39533015 4.35% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10697910 1.18% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2661098 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 282916763 29.20% 29.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 152378116 15.72% 44.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 162831122 16.80% 61.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119917560 12.37% 74.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126106053 13.01% 87.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 74105592 7.65% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38169342 3.94% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10016302 1.03% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2606220 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 908156186 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 969047070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 703286 2.81% 2.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4771 0.02% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19012865 76.06% 78.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5274676 21.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 856823 3.47% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4485 0.02% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18914760 76.65% 80.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4900553 19.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1230823853 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 930532 0.05% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1244244744 61.21% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 933049 0.05% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued @@ -390,475 +392,475 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 30 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 585374477 29.11% 90.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193665439 9.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 593617066 29.20% 90.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193930151 9.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2010794421 # Type of FU issued -system.cpu.iq.rate 2.123628 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24995598 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4959550302 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2638184259 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1953078988 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2035789802 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 217 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63764603 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2032725138 # Type of FU issued +system.cpu.iq.rate 1.973297 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24676621 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012140 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5064336479 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2719325477 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1969225475 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 784 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 183 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2057401528 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63678179 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 136642278 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 284566 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 187935 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43295180 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 148201485 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 301622 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 191452 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46713618 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 386993 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3827005 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 66022772 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23145640 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1044628 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2182779773 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5713944 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 622569059 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 218142237 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 173655 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 44651 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 187935 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8601247 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10177350 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18778597 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1981378382 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 570935022 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29416039 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 73017648 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27244100 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1491546 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2223439933 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6134188 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 634128265 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 221560674 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1025 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 470403 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 82153 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 191452 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8679785 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10261943 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18941728 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2001081478 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 578449212 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 31643660 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 103 # number of nop insts executed -system.cpu.iew.exec_refs 761630934 # number of memory reference insts executed -system.cpu.iew.exec_branches 237544754 # Number of branches executed -system.cpu.iew.exec_stores 190695912 # Number of stores executed -system.cpu.iew.exec_rate 2.092561 # Inst execution rate -system.cpu.iew.wb_sent 1962075581 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1953079152 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1293757962 # num instructions producing a value -system.cpu.iew.wb_consumers 2065123050 # num instructions consuming a value +system.cpu.iew.exec_nop 158 # number of nop insts executed +system.cpu.iew.exec_refs 769422153 # number of memory reference insts executed +system.cpu.iew.exec_branches 239265351 # Number of branches executed +system.cpu.iew.exec_stores 190972941 # Number of stores executed +system.cpu.iew.exec_rate 1.942579 # Inst execution rate +system.cpu.iew.wb_sent 1978131551 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1969225658 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1302526017 # num instructions producing a value +system.cpu.iew.wb_consumers 2074719324 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.062674 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626480 # average fanout of values written-back +system.cpu.iew.wb_rate 1.911654 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.627808 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 459769347 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 182 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16044351 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 842133415 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.046082 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.757625 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 500462812 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 181 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16168149 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 896029423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.923010 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718948 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 351966566 41.79% 41.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194208080 23.06% 64.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73932281 8.78% 73.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35396184 4.20% 77.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18675547 2.22% 80.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 31087553 3.69% 83.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19760319 2.35% 86.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10744228 1.28% 87.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106362657 12.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 406862083 45.41% 45.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193059933 21.55% 66.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73977423 8.26% 75.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35390708 3.95% 79.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18895903 2.11% 81.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30453376 3.40% 84.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19841212 2.21% 86.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11401039 1.27% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106147746 11.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 842133415 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563101 # Number of instructions committed -system.cpu.commit.committedOps 1723073913 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 896029423 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563096 # Number of instructions committed +system.cpu.commit.committedOps 1723073908 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773838 # Number of memory references committed -system.cpu.commit.loads 485926781 # Number of loads committed +system.cpu.commit.refs 660773836 # Number of memory references committed +system.cpu.commit.loads 485926780 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462438 # Number of branches committed +system.cpu.commit.branches 213462437 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941889 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941885 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106362657 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106147746 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2918613419 # The number of ROB reads -system.cpu.rob.rob_writes 4431868415 # The number of ROB writes -system.cpu.timesIdled 795856 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 38711414 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563083 # Number of Instructions Simulated -system.cpu.committedOps 1723073895 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563083 # Number of Instructions Simulated -system.cpu.cpi 0.613033 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.613033 # CPI: Total CPI of All Threads -system.cpu.ipc 1.631234 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.631234 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9926647662 # number of integer regfile reads -system.cpu.int_regfile_writes 1933066427 # number of integer regfile writes -system.cpu.fp_regfile_reads 168 # number of floating regfile reads -system.cpu.fp_regfile_writes 190 # number of floating regfile writes -system.cpu.misc_regfile_reads 2888912367 # number of misc regfile reads -system.cpu.misc_regfile_writes 148 # number of misc regfile writes -system.cpu.icache.replacements 20 # number of replacements -system.cpu.icache.tagsinuse 632.636403 # Cycle average of tags in use -system.cpu.icache.total_refs 282800594 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 786 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 359797.193384 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3013417798 # The number of ROB reads +system.cpu.rob.rob_writes 4520246386 # The number of ROB writes +system.cpu.timesIdled 1016810 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 61069051 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563078 # Number of Instructions Simulated +system.cpu.committedOps 1723073890 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563078 # Number of Instructions Simulated +system.cpu.cpi 0.666930 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.666930 # CPI: Total CPI of All Threads +system.cpu.ipc 1.499407 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.499407 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10019536016 # number of integer regfile reads +system.cpu.int_regfile_writes 1949927429 # number of integer regfile writes +system.cpu.fp_regfile_reads 198 # number of floating regfile reads +system.cpu.fp_regfile_writes 204 # number of floating regfile writes +system.cpu.misc_regfile_reads 2950890294 # number of misc regfile reads +system.cpu.misc_regfile_writes 146 # number of misc regfile writes +system.cpu.icache.replacements 21 # number of replacements +system.cpu.icache.tagsinuse 635.874030 # Cycle average of tags in use +system.cpu.icache.total_refs 292881421 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 787 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 372149.200762 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 632.636403 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.308904 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.308904 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 282800594 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 282800594 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 282800594 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 282800594 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 282800594 # number of overall hits -system.cpu.icache.overall_hits::total 282800594 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1137 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1137 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1137 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1137 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1137 # number of overall misses -system.cpu.icache.overall_misses::total 1137 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39598000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39598000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39598000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39598000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39598000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39598000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 282801731 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 282801731 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 282801731 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 282801731 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 282801731 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 282801731 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 635.874030 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310485 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310485 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 292881421 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 292881421 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 292881421 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 292881421 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 292881421 # number of overall hits +system.cpu.icache.overall_hits::total 292881421 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1239 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1239 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1239 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1239 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1239 # number of overall misses +system.cpu.icache.overall_misses::total 1239 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62929999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62929999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62929999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62929999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62929999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62929999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 292882660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 292882660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 292882660 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 292882660 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 292882660 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 292882660 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34826.737027 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34826.737027 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34826.737027 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34826.737027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34826.737027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34826.737027 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50790.959645 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50790.959645 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50790.959645 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50790.959645 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 213 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 351 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 351 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 351 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 351 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 786 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 786 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 786 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 786 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 786 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28796000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28796000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28796000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28796000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28796000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28796000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 452 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 452 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 452 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 452 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 452 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 452 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 787 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 787 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 787 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42672499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42672499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42672499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42672499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42672499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42672499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36636.132316 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36636.132316 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36636.132316 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36636.132316 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36636.132316 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36636.132316 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54221.726811 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54221.726811 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9616903 # number of replacements -system.cpu.dcache.tagsinuse 4087.861296 # Cycle average of tags in use -system.cpu.dcache.total_refs 660505517 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9620999 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.652488 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3324501000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.861296 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998013 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998013 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 492433938 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 492433938 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168071407 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168071407 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 99 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 99 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 73 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 73 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 660505345 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 660505345 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 660505345 # number of overall hits -system.cpu.dcache.overall_hits::total 660505345 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10054191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10054191 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4514640 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4514640 # number of WriteReq misses +system.cpu.dcache.replacements 9616996 # number of replacements +system.cpu.dcache.tagsinuse 4088.070177 # Cycle average of tags in use +system.cpu.dcache.total_refs 662383558 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9621092 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.847025 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3431633000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4088.070177 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998064 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998064 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 495328808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 495328808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167054576 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167054576 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 102 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 102 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 72 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 72 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 662383384 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 662383384 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 662383384 # number of overall hits +system.cpu.dcache.overall_hits::total 662383384 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11493898 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11493898 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5531471 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5531471 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 14568831 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 14568831 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 14568831 # number of overall misses -system.cpu.dcache.overall_misses::total 14568831 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 192605585000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 192605585000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 133759941491 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 133759941491 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 146500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 146500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 326365526491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 326365526491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 326365526491 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 326365526491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 502488129 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 502488129 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17025369 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17025369 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17025369 # number of overall misses +system.cpu.dcache.overall_misses::total 17025369 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 300469698500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 300469698500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 217116494201 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 217116494201 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 190500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 190500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 517586192701 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 517586192701 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 517586192701 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 517586192701 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 506822706 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 506822706 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 102 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 102 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 73 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 73 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 675074176 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 675074176 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 675074176 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 675074176 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026159 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026159 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.029412 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.029412 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021581 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021581 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021581 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021581 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19156.746177 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19156.746177 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29628.041547 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29628.041547 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22401.627591 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22401.627591 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22401.627591 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22401.627591 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1880438 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 248831 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 88187 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1969 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.323302 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 126.374302 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 105 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 105 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 72 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 72 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 679408753 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 679408753 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 679408753 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 679408753 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022678 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022678 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032051 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032051 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.028571 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.028571 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025059 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025059 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025059 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025059 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26141.670867 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26141.670867 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39251.131245 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39251.131245 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30400.879576 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30400.879576 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30400.879576 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30400.879576 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19937535 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 989836 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1174592 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64547 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.974009 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15.335120 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3473899 # number of writebacks -system.cpu.dcache.writebacks::total 3473899 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2327206 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2327206 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2620625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2620625 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3785750 # number of writebacks +system.cpu.dcache.writebacks::total 3785750 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3766794 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3766794 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3637483 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3637483 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4947831 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4947831 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4947831 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4947831 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7726985 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7726985 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894015 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1894015 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9621000 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9621000 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9621000 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9621000 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100672222000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 100672222000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58875647012 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 58875647012 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 159547869012 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 159547869012 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 159547869012 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 159547869012 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015377 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7404277 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7404277 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7404277 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7404277 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7727104 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7727104 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893988 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893988 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9621092 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9621092 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9621092 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9621092 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171327843500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171327843500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71936813831 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71936813831 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 243264657331 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 243264657331 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 243264657331 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 243264657331 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015246 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015246 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014252 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014252 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014252 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014252 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13028.655032 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13028.655032 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31085.100705 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31085.100705 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16583.293734 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16583.293734 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16583.293734 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16583.293734 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014161 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014161 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014161 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014161 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22172.322710 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22172.322710 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37981.662941 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37981.662941 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25284.516283 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25284.516283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25284.516283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25284.516283 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2427272 # number of replacements -system.cpu.l2cache.tagsinuse 31171.716737 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8744168 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2456984 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.558903 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 80002919000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14002.042506 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 15.065518 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17154.608713 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.427308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000460 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.523517 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.951285 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6115863 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6115892 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3473899 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3473899 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1062992 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1062992 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7178855 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7178884 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7178855 # number of overall hits -system.cpu.l2cache.overall_hits::total 7178884 # number of overall hits +system.cpu.l2cache.replacements 2224194 # number of replacements +system.cpu.l2cache.tagsinuse 31538.307180 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9258938 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2253968 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.107839 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 20485728502 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14439.228019 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 20.648477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17078.430684 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440650 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000630 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.521192 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.962473 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6299217 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6299247 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3785750 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3785750 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1065742 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1065742 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7364959 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7364989 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7364959 # number of overall hits +system.cpu.l2cache.overall_hits::total 7364989 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1611122 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1611879 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 831023 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 831023 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1427887 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1428644 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 828246 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 828246 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 757 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2442145 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2442902 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2256133 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2256890 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 757 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2442145 # number of overall misses -system.cpu.l2cache.overall_misses::total 2442902 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27934500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 84953945000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 84981879500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55209394500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 55209394500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27934500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 140163339500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 140191274000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27934500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 140163339500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 140191274000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 786 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7726985 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7727771 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3473899 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3473899 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894015 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1894015 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 786 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9621000 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9621786 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 786 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9621000 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9621786 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963104 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208506 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.208583 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438763 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.438763 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963104 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.253835 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.253893 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963104 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.253835 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.253893 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36901.585205 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52729.678448 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52722.244970 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66435.459067 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66435.459067 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36901.585205 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57393.537034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 57387.187042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36901.585205 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57393.537034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 57387.187042 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1390172 # number of cycles access was blocked +system.cpu.l2cache.overall_misses::cpu.data 2256133 # number of overall misses +system.cpu.l2cache.overall_misses::total 2256890 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41571500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98780136000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98821707500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58846759000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 58846759000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41571500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 157626895000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 157668466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41571500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 157626895000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 157668466500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 787 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7727104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7727891 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3785750 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3785750 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893988 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893988 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 787 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9621092 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9621879 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 787 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9621092 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9621879 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184789 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.184869 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437303 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.437303 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961881 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.234499 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.234558 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961881 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.234499 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.234558 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54916.116248 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69179.238973 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69171.681329 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71049.855961 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71049.855961 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54916.116248 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69865.958700 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69860.944264 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54916.116248 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69865.958700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69860.944264 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 31316 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 44.391749 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1123933 # number of writebacks -system.cpu.l2cache.writebacks::total 1123933 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 756 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611113 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1611869 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 831023 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 831023 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 756 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2442136 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2442892 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 756 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2442136 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2442892 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25190143 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 79130491462 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79155681605 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 52276530586 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 52276530586 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25190143 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131407022048 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 131432212191 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25190143 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131407022048 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 131432212191 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208505 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208581 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438763 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438763 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253834 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.253892 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253834 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.253892 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33320.294974 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49115.419876 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49108.011634 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62906.237957 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62906.237957 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33320.294974 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53808.232649 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53801.892262 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33320.294974 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53808.232649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53801.892262 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1103400 # number of writebacks +system.cpu.l2cache.writebacks::total 1103400 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1427881 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1428636 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 828246 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 828246 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2256127 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2256882 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2256127 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2256882 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31971694 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80731453067 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80763424761 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48402066091 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48402066091 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31971694 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 129133519158 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 129165490852 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31971694 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 129133519158 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 129165490852 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184789 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184868 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437303 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437303 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.234498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.234557 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.234498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.234557 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42346.614570 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56539.342611 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56531.842093 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58439.239177 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58439.239177 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42346.614570 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57236.812980 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57231.831727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42346.614570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57236.812980 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57231.831727 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |