diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 960 |
1 files changed, 480 insertions, 480 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index b46ca3b4f..45a43d0ac 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.464095 # Number of seconds simulated -sim_ticks 464094642500 # Number of ticks simulated -final_tick 464094642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.463994 # Number of seconds simulated +sim_ticks 463993693500 # Number of ticks simulated +final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178110 # Simulator instruction rate (inst/s) -host_op_rate 198694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53516537 # Simulator tick rate (ticks/s) -host_mem_usage 227392 # Number of bytes of host memory used -host_seconds 8671.99 # Real time elapsed on the host -sim_insts 1544563041 # Number of instructions simulated -sim_ops 1723073854 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 189817088 # Number of bytes read from this memory -system.physmem.bytes_inst_read 48640 # Number of instructions bytes read from this memory -system.physmem.bytes_written 78237376 # Number of bytes written to this memory -system.physmem.num_reads 2965892 # Number of read requests responded to by this memory -system.physmem.num_writes 1222459 # Number of write requests responded to by this memory +host_inst_rate 212934 # Simulator instruction rate (inst/s) +host_op_rate 237543 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63966219 # Simulator tick rate (ticks/s) +host_mem_usage 224764 # Number of bytes of host memory used +host_seconds 7253.73 # Real time elapsed on the host +sim_insts 1544563066 # Number of instructions simulated +sim_ops 1723073879 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 189795648 # Number of bytes read from this memory +system.physmem.bytes_inst_read 49344 # Number of instructions bytes read from this memory +system.physmem.bytes_written 78222144 # Number of bytes written to this memory +system.physmem.num_reads 2965557 # Number of read requests responded to by this memory +system.physmem.num_writes 1222221 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 409005127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 104806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 168580649 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 577585776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 409047904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 106346 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 168584498 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 577632403 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,107 +64,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 928189286 # number of cpu cycles simulated +system.cpu.numCycles 927987388 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 300558884 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 246363041 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16110008 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 171748174 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 156362542 # Number of BTB hits +system.cpu.BPredUnit.lookups 300553850 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 246366147 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16098585 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 170916236 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 156311774 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18325675 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 390 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 292832773 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2158671516 # Number of instructions fetch has processed -system.cpu.fetch.Branches 300558884 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174688217 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 429285540 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83802150 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 129138530 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 283809493 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5370008 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 918527985 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.613925 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.238783 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18335288 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 425 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 292740519 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2158326699 # Number of instructions fetch has processed +system.cpu.fetch.Branches 300553850 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174647062 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 429206926 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83759589 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 129259054 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 283730265 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5372560 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 918446800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.613763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.238744 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 489242491 53.26% 53.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23031671 2.51% 55.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38788083 4.22% 59.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47826065 5.21% 65.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40763412 4.44% 69.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46954546 5.11% 74.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39099426 4.26% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18124481 1.97% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174697810 19.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 489239924 53.27% 53.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23020148 2.51% 55.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38764254 4.22% 60.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47809734 5.21% 65.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40766066 4.44% 69.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46976906 5.11% 74.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39072572 4.25% 79.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18137057 1.97% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174660139 19.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 918527985 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.323812 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.325680 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 322137890 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 109173401 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403303983 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16642613 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 67270098 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46182318 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 747 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2347171741 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2550 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 67270098 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 343773810 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50758192 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21988 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 397138305 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 59565592 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2290275122 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23158 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4666704 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 46265569 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2264842596 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10571584644 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10571581459 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3185 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319959 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 558522637 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5679 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5674 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 136915079 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624891325 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 218844969 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86018221 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66187056 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2190772661 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1712 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2016120341 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4885308 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 463006686 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1075673735 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1208 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 918527985 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.194947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.923224 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 918446800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.323877 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325815 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 322039794 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 109288431 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403236235 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16643003 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 67239337 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46165390 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 810 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2346870217 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2646 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 67239337 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 343676895 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50827249 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9551 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 397069716 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 59624052 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2289998307 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23088 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4666333 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 46320806 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2264655243 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10570139009 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10570134861 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4148 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319999 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 558335244 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4462 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4454 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 136929133 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624839821 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 218742392 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85961960 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 66558298 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2190567677 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 692 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2016055896 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4892741 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462785080 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1074735939 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 918446800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.195071 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.923309 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 251260735 27.35% 27.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 138867546 15.12% 42.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158222967 17.23% 59.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 116427032 12.68% 72.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125736326 13.69% 86.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75508875 8.22% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39162431 4.26% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10675084 1.16% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2666989 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 251194344 27.35% 27.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 138877340 15.12% 42.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158309179 17.24% 59.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 116273452 12.66% 72.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125754756 13.69% 86.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75525220 8.22% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39163504 4.26% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10678346 1.16% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2670659 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 918527985 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 918446800 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 822239 3.28% 3.28% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4824 0.02% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 824240 3.28% 3.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4827 0.02% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available @@ -192,13 +192,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19001190 75.81% 79.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5234373 20.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19025079 75.82% 79.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5238831 20.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234297815 61.22% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 931066 0.05% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234276939 61.22% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 932607 0.05% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued @@ -220,160 +220,160 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 50 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 9 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 29 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587044073 29.12% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193847304 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587048024 29.12% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193798201 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2016120341 # Type of FU issued -system.cpu.iq.rate 2.172100 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25062626 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4980716257 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2653967070 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1958162011 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 344 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2041182792 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 175 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63608263 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2016055896 # Type of FU issued +system.cpu.iq.rate 2.172504 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25092977 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012447 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4980543862 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2653539100 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1958126109 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 448 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2041148646 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 227 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63700277 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138964553 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 284704 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189296 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43997922 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138913044 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 284373 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189336 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43895340 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 451252 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 451092 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 67270098 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23165985 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1316827 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2190782552 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5581738 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624891325 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 218844969 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1648 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 207697 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 50017 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189296 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8647984 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10198062 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18846046 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986617242 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 572452659 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29503099 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 67239337 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23164250 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1316440 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2190576494 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5585867 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624839821 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 218742392 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 626 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 207277 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 49894 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189336 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8626288 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10208500 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18834788 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1986583692 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 572477440 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29472204 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 8179 # number of nop insts executed -system.cpu.iew.exec_refs 763318356 # number of memory reference insts executed -system.cpu.iew.exec_branches 238198091 # Number of branches executed -system.cpu.iew.exec_stores 190865697 # Number of stores executed -system.cpu.iew.exec_rate 2.140315 # Inst execution rate -system.cpu.iew.wb_sent 1967150761 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1958162143 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296167059 # num instructions producing a value -system.cpu.iew.wb_consumers 2068734310 # num instructions consuming a value +system.cpu.iew.exec_nop 8125 # number of nop insts executed +system.cpu.iew.exec_refs 763312359 # number of memory reference insts executed +system.cpu.iew.exec_branches 238194699 # Number of branches executed +system.cpu.iew.exec_stores 190834919 # Number of stores executed +system.cpu.iew.exec_rate 2.140744 # Inst execution rate +system.cpu.iew.wb_sent 1967109112 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1958126281 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296093484 # num instructions producing a value +system.cpu.iew.wb_consumers 2068479796 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.109658 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626551 # average fanout of values written-back +system.cpu.iew.wb_rate 2.110079 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626592 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1544563059 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1723073872 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 467775476 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 504 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16109498 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 851257888 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.024150 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.756084 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1544563084 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1723073897 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 467569115 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 177 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16098007 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 851207464 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.024270 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.756192 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 363004636 42.64% 42.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192697561 22.64% 65.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73553862 8.64% 73.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35091204 4.12% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18733793 2.20% 80.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30684966 3.60% 83.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19668934 2.31% 86.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10962087 1.29% 87.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106860845 12.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 362905349 42.63% 42.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192760849 22.65% 65.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73571189 8.64% 73.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35131293 4.13% 78.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18689200 2.20% 80.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30622248 3.60% 83.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19666355 2.31% 86.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10977227 1.29% 87.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106883754 12.56% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 851257888 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563059 # Number of instructions committed -system.cpu.commit.committedOps 1723073872 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 851207464 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563084 # Number of instructions committed +system.cpu.commit.committedOps 1723073897 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773819 # Number of memory references committed -system.cpu.commit.loads 485926772 # Number of loads committed +system.cpu.commit.refs 660773829 # Number of memory references committed +system.cpu.commit.loads 485926777 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462366 # Number of branches committed +system.cpu.commit.branches 213462371 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941877 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106860845 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106883754 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2935245792 # The number of ROB reads -system.cpu.rob.rob_writes 4449143808 # The number of ROB writes -system.cpu.timesIdled 899784 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9661301 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563041 # Number of Instructions Simulated -system.cpu.committedOps 1723073854 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563041 # Number of Instructions Simulated -system.cpu.cpi 0.600940 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.600940 # CPI: Total CPI of All Threads -system.cpu.ipc 1.664060 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.664060 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9952061686 # number of integer regfile reads -system.cpu.int_regfile_writes 1938314522 # number of integer regfile writes -system.cpu.fp_regfile_reads 132 # number of floating regfile reads -system.cpu.fp_regfile_writes 135 # number of floating regfile writes -system.cpu.misc_regfile_reads 2898335768 # number of misc regfile reads -system.cpu.misc_regfile_writes 128 # number of misc regfile writes -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 636.409684 # Cycle average of tags in use -system.cpu.icache.total_refs 283808312 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 793 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 357891.944515 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2934966123 # The number of ROB reads +system.cpu.rob.rob_writes 4448699546 # The number of ROB writes +system.cpu.timesIdled 899596 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9540588 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563066 # Number of Instructions Simulated +system.cpu.committedOps 1723073879 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563066 # Number of Instructions Simulated +system.cpu.cpi 0.600809 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.600809 # CPI: Total CPI of All Threads +system.cpu.ipc 1.664422 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.664422 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9951953141 # number of integer regfile reads +system.cpu.int_regfile_writes 1938266429 # number of integer regfile writes +system.cpu.fp_regfile_reads 186 # number of floating regfile reads +system.cpu.fp_regfile_writes 205 # number of floating regfile writes +system.cpu.misc_regfile_reads 2897977277 # number of misc regfile reads +system.cpu.misc_regfile_writes 138 # number of misc regfile writes +system.cpu.icache.replacements 28 # number of replacements +system.cpu.icache.tagsinuse 641.389873 # Cycle average of tags in use +system.cpu.icache.total_refs 283729068 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 801 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 354218.561798 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 636.409684 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.310747 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.310747 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 283808312 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 283808312 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 283808312 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 283808312 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 283808312 # number of overall hits -system.cpu.icache.overall_hits::total 283808312 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1181 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1181 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1181 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1181 # number of overall misses -system.cpu.icache.overall_misses::total 1181 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39284000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39284000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39284000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39284000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39284000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39284000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 283809493 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 283809493 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 283809493 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 283809493 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 283809493 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 283809493 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 641.389873 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.313179 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.313179 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 283729068 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 283729068 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 283729068 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 283729068 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 283729068 # number of overall hits +system.cpu.icache.overall_hits::total 283729068 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1197 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1197 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1197 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1197 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1197 # number of overall misses +system.cpu.icache.overall_misses::total 1197 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39840000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39840000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39840000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39840000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39840000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39840000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 283730265 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 283730265 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 283730265 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 283730265 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 283730265 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 283730265 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33263.336156 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33263.336156 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33263.336156 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,269 +382,269 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 388 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 388 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 388 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 388 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 388 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 388 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 793 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 793 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 793 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 793 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 793 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27229500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27229500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27229500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27229500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27229500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27229500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 396 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 396 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 396 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 396 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 396 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # 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number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34337.326608 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34337.326608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34337.326608 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9619385 # number of replacements -system.cpu.dcache.tagsinuse 4087.714803 # Cycle average of tags in use -system.cpu.dcache.total_refs 660788859 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9623481 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.664224 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3348066000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.714803 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997977 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997977 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 493410063 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 493410063 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167378645 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167378645 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 88 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 88 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 63 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 63 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 660788708 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 660788708 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 660788708 # number of overall hits -system.cpu.dcache.overall_hits::total 660788708 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10697227 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10697227 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5207402 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5207402 # number of WriteReq misses +system.cpu.dcache.replacements 9619302 # number of replacements +system.cpu.dcache.tagsinuse 4087.756066 # Cycle average of tags in use +system.cpu.dcache.total_refs 660726669 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9623398 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.658354 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3346373000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.756066 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997987 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997987 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 493348220 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 493348220 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167378287 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167378287 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 68 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 68 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 660726507 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 660726507 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 660726507 # number of overall hits +system.cpu.dcache.overall_hits::total 660726507 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10693817 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10693817 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5207760 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5207760 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15904629 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15904629 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15904629 # number of overall misses -system.cpu.dcache.overall_misses::total 15904629 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 189148262000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 189148262000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129349741794 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129349741794 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 15901577 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15901577 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15901577 # number of overall misses +system.cpu.dcache.overall_misses::total 15901577 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 189065481500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 189065481500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129319032251 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129319032251 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 318498003794 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 318498003794 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 318498003794 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 318498003794 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 504107290 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 504107290 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 318384513751 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 318384513751 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 318384513751 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 318384513751 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 504042037 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 504042037 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 91 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 91 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 63 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 63 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 676693337 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 676693337 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 676693337 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 676693337 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021220 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030173 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032967 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023503 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023503 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.990108 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24839.592141 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 68 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 68 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 676628084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 676628084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 676628084 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 676628084 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021216 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023501 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023501 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20025.490931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20025.490931 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 271743722 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 161500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 91838 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2958.946427 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20187.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 271440605 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 164500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 91957 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2951.821014 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16450 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3133740 # number of writebacks -system.cpu.dcache.writebacks::total 3133740 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2967640 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2967640 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313508 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3313508 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3133684 # number of writebacks +system.cpu.dcache.writebacks::total 3133684 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2964371 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2964371 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313808 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3313808 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6281148 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6281148 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6281148 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6281148 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729587 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7729587 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893894 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893894 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9623481 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9623481 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9623481 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9623481 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93074627500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 93074627500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45380366039 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 45380366039 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138454993539 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 138454993539 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138454993539 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 138454993539 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015333 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 6278179 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6278179 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6278179 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6278179 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729446 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7729446 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893952 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893952 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9623398 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9623398 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9623398 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9623398 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93061119500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 93061119500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45369971960 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 45369971960 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138431091460 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 138431091460 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460 # 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mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.817537 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23955.185749 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2953454 # number of replacements -system.cpu.l2cache.tagsinuse 26874.371014 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7878176 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2980778 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.642993 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 100977467500 # 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mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |