diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 1612 |
1 files changed, 814 insertions, 798 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index d2f403426..493c10cfc 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.771725 # Number of seconds simulated -sim_ticks 771725169000 # Number of ticks simulated -final_tick 771725169000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.770277 # Number of seconds simulated +sim_ticks 770277033000 # Number of ticks simulated +final_tick 770277033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137392 # Simulator instruction rate (inst/s) -host_op_rate 148019 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68646343 # Simulator tick rate (ticks/s) -host_mem_usage 311812 # Number of bytes of host memory used -host_seconds 11242.04 # Real time elapsed on the host +host_inst_rate 139677 # Simulator instruction rate (inst/s) +host_op_rate 150481 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69657391 # Simulator tick rate (ticks/s) +host_mem_usage 313196 # Number of bytes of host memory used +host_seconds 11058.08 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 238609216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63286144 # Number of bytes read from this memory -system.physmem.bytes_read::total 301961664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104822848 # Number of bytes written to this memory -system.physmem.bytes_written::total 104822848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3728269 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 988846 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4718151 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1637857 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1637857 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 85917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309189366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82006065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 391281347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 85917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 135829246 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 135829246 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 135829246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 85917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309189366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82006065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 527110594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4718151 # Number of read requests accepted -system.physmem.writeReqs 1637857 # Number of write requests accepted -system.physmem.readBursts 4718151 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1637857 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 301519872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 441792 # Total number of bytes read from write queue -system.physmem.bytesWritten 104820544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 301961664 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104822848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6903 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 19 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 66048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238802560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63353600 # Number of bytes read from this memory +system.physmem.bytes_read::total 302222208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104930816 # Number of bytes written to this memory +system.physmem.bytes_written::total 104930816 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3731290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 989900 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4722222 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1639544 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1639544 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 85746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 310021654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82247811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 392355211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 85746 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85746 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136224776 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136224776 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136224776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 85746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 310021654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82247811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 528579987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4722222 # Number of read requests accepted +system.physmem.writeReqs 1639544 # Number of write requests accepted +system.physmem.readBursts 4722222 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1639544 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301770432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 451776 # Total number of bytes read from write queue +system.physmem.bytesWritten 104928448 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 302222208 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104930816 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7059 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 16 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 296668 # Per bank write bursts -system.physmem.perBankRdBursts::1 294562 # Per bank write bursts -system.physmem.perBankRdBursts::2 288307 # Per bank write bursts -system.physmem.perBankRdBursts::3 292737 # Per bank write bursts -system.physmem.perBankRdBursts::4 290232 # Per bank write bursts -system.physmem.perBankRdBursts::5 289394 # Per bank write bursts -system.physmem.perBankRdBursts::6 285167 # Per bank write bursts -system.physmem.perBankRdBursts::7 280683 # Per bank write bursts -system.physmem.perBankRdBursts::8 297292 # Per bank write bursts -system.physmem.perBankRdBursts::9 302920 # Per bank write bursts -system.physmem.perBankRdBursts::10 295430 # Per bank write bursts -system.physmem.perBankRdBursts::11 301815 # Per bank write bursts -system.physmem.perBankRdBursts::12 303322 # Per bank write bursts -system.physmem.perBankRdBursts::13 302849 # Per bank write bursts -system.physmem.perBankRdBursts::14 297025 # Per bank write bursts -system.physmem.perBankRdBursts::15 292845 # Per bank write bursts -system.physmem.perBankWrBursts::0 103942 # Per bank write bursts -system.physmem.perBankWrBursts::1 102053 # Per bank write bursts -system.physmem.perBankWrBursts::2 99317 # Per bank write bursts -system.physmem.perBankWrBursts::3 99871 # Per bank write bursts -system.physmem.perBankWrBursts::4 99169 # Per bank write bursts -system.physmem.perBankWrBursts::5 98963 # Per bank write bursts -system.physmem.perBankWrBursts::6 102735 # Per bank write bursts -system.physmem.perBankWrBursts::7 104389 # Per bank write bursts -system.physmem.perBankWrBursts::8 105226 # Per bank write bursts -system.physmem.perBankWrBursts::9 104532 # Per bank write bursts -system.physmem.perBankWrBursts::10 102159 # Per bank write bursts -system.physmem.perBankWrBursts::11 102806 # Per bank write bursts -system.physmem.perBankWrBursts::12 103028 # Per bank write bursts -system.physmem.perBankWrBursts::13 102702 # Per bank write bursts -system.physmem.perBankWrBursts::14 104263 # Per bank write bursts -system.physmem.perBankWrBursts::15 102666 # Per bank write bursts +system.physmem.perBankRdBursts::0 297173 # Per bank write bursts +system.physmem.perBankRdBursts::1 295012 # Per bank write bursts +system.physmem.perBankRdBursts::2 289245 # Per bank write bursts +system.physmem.perBankRdBursts::3 293018 # Per bank write bursts +system.physmem.perBankRdBursts::4 289731 # Per bank write bursts +system.physmem.perBankRdBursts::5 289594 # Per bank write bursts +system.physmem.perBankRdBursts::6 284433 # Per bank write bursts +system.physmem.perBankRdBursts::7 281274 # Per bank write bursts +system.physmem.perBankRdBursts::8 297880 # Per bank write bursts +system.physmem.perBankRdBursts::9 304149 # Per bank write bursts +system.physmem.perBankRdBursts::10 295533 # Per bank write bursts +system.physmem.perBankRdBursts::11 302217 # Per bank write bursts +system.physmem.perBankRdBursts::12 302962 # Per bank write bursts +system.physmem.perBankRdBursts::13 302377 # Per bank write bursts +system.physmem.perBankRdBursts::14 297334 # Per bank write bursts +system.physmem.perBankRdBursts::15 293231 # Per bank write bursts +system.physmem.perBankWrBursts::0 104274 # Per bank write bursts +system.physmem.perBankWrBursts::1 102166 # Per bank write bursts +system.physmem.perBankWrBursts::2 99582 # Per bank write bursts +system.physmem.perBankWrBursts::3 100201 # Per bank write bursts +system.physmem.perBankWrBursts::4 99226 # Per bank write bursts +system.physmem.perBankWrBursts::5 98958 # Per bank write bursts +system.physmem.perBankWrBursts::6 102876 # Per bank write bursts +system.physmem.perBankWrBursts::7 104542 # Per bank write bursts +system.physmem.perBankWrBursts::8 105498 # Per bank write bursts +system.physmem.perBankWrBursts::9 104632 # Per bank write bursts +system.physmem.perBankWrBursts::10 102325 # Per bank write bursts +system.physmem.perBankWrBursts::11 102766 # Per bank write bursts +system.physmem.perBankWrBursts::12 102939 # Per bank write bursts +system.physmem.perBankWrBursts::13 102535 # Per bank write bursts +system.physmem.perBankWrBursts::14 104418 # Per bank write bursts +system.physmem.perBankWrBursts::15 102569 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 771725022000 # Total gap between requests +system.physmem.totGap 770276886500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4718151 # Read request sizes (log2) +system.physmem.readPktSize::6 4722222 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1637857 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2774626 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1044189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 331696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 233512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 153773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 84990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 39149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1639544 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2779707 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1048806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 331545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 232118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 150885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 83926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 38903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 195 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,37 +148,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 59860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 75448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 110632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 113547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 106733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 103419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 23226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 60170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 75550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 106819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 114103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 105493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -197,122 +197,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4287400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.775232 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.917076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 101.448471 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3413764 79.62% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 675374 15.75% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96809 2.26% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35249 0.82% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22885 0.53% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12087 0.28% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7187 0.17% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5043 0.12% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19002 0.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4287400 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98767 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.700609 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 32.313411 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 98.282358 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-127 94950 96.14% 96.14% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-255 1367 1.38% 97.52% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-511 428 0.43% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-639 356 0.36% 99.09% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-767 374 0.38% 99.47% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-895 247 0.25% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::896-1023 145 0.15% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1151 66 0.07% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1152-1279 31 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1407 13 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1408-1535 9 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4293402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.726038 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.887603 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.441683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3419558 79.65% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 676188 15.75% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96097 2.24% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35320 0.82% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22691 0.53% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12222 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7184 0.17% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5103 0.12% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19039 0.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4293402 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98787 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.730481 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.341812 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98.609970 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 94999 96.17% 96.17% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1343 1.36% 97.52% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 771 0.78% 98.31% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 397 0.40% 98.71% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 383 0.39% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 367 0.37% 99.47% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 255 0.26% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 139 0.14% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 71 0.07% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 36 0.04% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 14 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 4 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-1663 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1920-2047 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2688-2815 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2944-3071 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3199 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3200-3327 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2176-2303 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3328-3455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98767 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98767 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.582674 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.549780 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.086524 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 73305 74.22% 74.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1806 1.83% 76.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18343 18.57% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3630 3.68% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 937 0.95% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 387 0.39% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 162 0.16% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 107 0.11% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 60 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 22 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::3456-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3840-3967 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3968-4095 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98787 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98787 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.596384 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.562558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.102794 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 72931 73.83% 73.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1712 1.73% 75.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18497 18.72% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3886 3.93% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1013 1.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 377 0.38% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 169 0.17% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 93 0.09% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 49 0.05% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 46 0.05% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 12 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98767 # Writes before turning the bus around for reads -system.physmem.totQLat 132285118194 # Total ticks spent queuing -system.physmem.totMemAccLat 220621018194 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23556240000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28078.57 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98787 # Writes before turning the bus around for reads +system.physmem.totQLat 131372718643 # Total ticks spent queuing +system.physmem.totMemAccLat 219782024893 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23575815000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27861.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46828.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 390.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 135.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 391.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 135.83 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46611.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 391.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 136.22 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 392.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.22 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.11 # Data bus utilization in percentage -system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads +system.physmem.busUtil 4.12 # Data bus utilization in percentage +system.physmem.busUtilRead 3.06 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing -system.physmem.readRowHits 1709073 # Number of row buffer hits during reads -system.physmem.writeRowHits 352585 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.28 # Row buffer hit rate for reads +system.physmem.readRowHits 1708262 # Number of row buffer hits during reads +system.physmem.writeRowHits 352995 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.23 # Row buffer hit rate for reads system.physmem.writeRowHitRate 21.53 # Row buffer hit rate for writes -system.physmem.avgGap 121416.62 # Average gap between requests -system.physmem.pageHitRate 32.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16073195040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8770096500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18077007000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5251294800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50404907280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 410674128390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 102790850250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 612041479260 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.088667 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 168453702129 # Time in different power states -system.physmem_0.memoryStateTime::REF 25769380000 # Time in different power states +system.physmem.avgGap 121079.10 # Average gap between requests +system.physmem.pageHitRate 32.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16098316920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8783803875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18090555600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5260230720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50310315120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 409970854125 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102538812000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 611052888360 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.296379 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 168045428834 # Time in different power states +system.physmem_0.memoryStateTime::REF 25721020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 577496605871 # Time in different power states +system.physmem_0.memoryStateTime::ACT 576504578166 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16339027320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8915143875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18669222000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5361163200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50404907280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 412008151545 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 101620654500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 613318269720 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.743144 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 166509885283 # Time in different power states -system.physmem_1.memoryStateTime::REF 25769380000 # Time in different power states +system.physmem_1.actEnergy 16359303240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8926207125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18686249400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5363152560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50310315120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 411485095035 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 101210530500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 612340852980 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.968472 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165832482361 # Time in different power states +system.physmem_1.memoryStateTime::REF 25721020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 579440435717 # Time in different power states +system.physmem_1.memoryStateTime::ACT 578718185889 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286277860 # Number of BP lookups -system.cpu.branchPred.condPredicted 223409255 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14633591 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157407621 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150346120 # Number of BTB hits +system.cpu.branchPred.lookups 286281176 # Number of BP lookups +system.cpu.branchPred.condPredicted 223407845 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631280 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158010784 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150352507 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.513876 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16641206 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.153320 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16641956 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -431,128 +430,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1543450339 # number of cpu cycles simulated +system.cpu.numCycles 1540554067 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13927699 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067517377 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286277860 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166987326 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1514795150 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29291799 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 907 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656942032 # Number of cache lines fetched +system.cpu.fetch.icacheStallCycles 13926810 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067510841 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286281176 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166994463 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1511903145 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29287205 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 944 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656946227 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 957 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1543369835 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.435149 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229340 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 1540474684 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.437849 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228901 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 460957271 29.87% 29.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465455811 30.16% 60.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101360614 6.57% 66.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515596139 33.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 458056876 29.73% 29.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465435106 30.21% 59.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101413024 6.58% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515569678 33.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1543369835 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185479 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.339543 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74619350 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 545977788 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 850086533 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58040967 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14645197 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42200501 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 754 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037190940 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52475133 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14645197 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139685845 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 464851768 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13523 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837895691 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86277811 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976364426 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26735694 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45105241 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125505 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1481556 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25500508 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985835865 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128071192 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432849079 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 136 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1540474684 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185830 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.342057 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74648924 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 543079640 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849978540 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58124682 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14642898 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42203677 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 755 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037193143 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52473156 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14642898 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139724503 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 462464867 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13004 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837848817 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 85780595 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976362381 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26752450 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45148759 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125663 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1475660 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 24911172 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985832580 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128057886 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432844380 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 133 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310936920 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 149 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 140 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111342876 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542549398 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199301403 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26926926 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29153523 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947926711 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 208 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857446823 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13498178 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283894503 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 646939215 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1543369835 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.203501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151095 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310933635 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 157 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 149 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111445716 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542550479 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199301883 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26937332 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29252722 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947933921 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857470724 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13498979 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283901721 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647143115 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1540474684 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.205778 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150877 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 590630846 38.27% 38.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325771475 21.11% 59.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378267234 24.51% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219666416 14.23% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29027688 1.88% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6176 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 587582159 38.14% 38.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326005186 21.16% 59.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378227465 24.55% 83.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219635075 14.26% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29018612 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6187 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1543369835 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1540474684 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166059149 40.99% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1996 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191393147 47.24% 88.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47682914 11.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166090735 41.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2011 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191466761 47.26% 88.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47541933 11.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138268714 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801071 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138243565 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801032 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -574,90 +573,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 28 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532058987 28.64% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186318001 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532113978 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186312098 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857446823 # Type of FU issued -system.cpu.iq.rate 1.203438 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405137206 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5676898637 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231834122 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805736851 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 228 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 232 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262583902 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 127 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17817639 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857470724 # Type of FU issued +system.cpu.iq.rate 1.205716 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405101440 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218093 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5674016313 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231848584 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805694743 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 238 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262572030 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17810782 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84243064 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66651 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24454358 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84244145 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66602 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13196 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24454838 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4525889 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4805394 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4507141 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4884537 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14645197 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25323327 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1332663 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947926995 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14642898 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25317454 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1284847 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947934221 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542549398 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199301403 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 146 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 158839 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1172731 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7701738 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8706499 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16408237 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827783249 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516881888 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29663574 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542550479 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199301883 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 154 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159143 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1124751 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13196 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7700546 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8704736 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16405282 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827804607 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516933891 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29666117 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 76 # number of nop insts executed -system.cpu.iew.exec_refs 698636146 # number of memory reference insts executed -system.cpu.iew.exec_branches 229555717 # Number of branches executed -system.cpu.iew.exec_stores 181754258 # Number of stores executed -system.cpu.iew.exec_rate 1.184219 # Inst execution rate -system.cpu.iew.wb_sent 1808767141 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805736919 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169322951 # num instructions producing a value -system.cpu.iew.wb_consumers 1689713401 # num instructions consuming a value +system.cpu.iew.exec_nop 84 # number of nop insts executed +system.cpu.iew.exec_refs 698685293 # number of memory reference insts executed +system.cpu.iew.exec_branches 229544445 # Number of branches executed +system.cpu.iew.exec_stores 181751402 # Number of stores executed +system.cpu.iew.exec_rate 1.186459 # Inst execution rate +system.cpu.iew.wb_sent 1808724876 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805694813 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169261823 # num instructions producing a value +system.cpu.iew.wb_consumers 1689660637 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.169935 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692024 # average fanout of values written-back +system.cpu.iew.wb_rate 1.172107 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692010 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 258002520 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 258006259 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14632889 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1503882923 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.106491 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.024391 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14630576 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1500991330 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.108622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.025694 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 923604765 61.41% 61.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250635322 16.67% 78.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110056363 7.32% 85.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55280526 3.68% 89.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29292132 1.95% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34092515 2.27% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24716046 1.64% 94.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18126603 1.21% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58078651 3.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 920697347 61.34% 61.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250635150 16.70% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110066020 7.33% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55280178 3.68% 89.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29318113 1.95% 91.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34079049 2.27% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24716376 1.65% 94.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18134019 1.21% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58065078 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1503882923 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1500991330 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -703,76 +702,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58078651 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3367838627 # The number of ROB reads -system.cpu.rob.rob_writes 3883562090 # The number of ROB writes -system.cpu.timesIdled 851 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80504 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58065078 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3364964346 # The number of ROB reads +system.cpu.rob.rob_writes 3883565961 # The number of ROB writes +system.cpu.timesIdled 839 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79383 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.999280 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.999280 # CPI: Total CPI of All Threads -system.cpu.ipc 1.000721 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.000721 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175739809 # number of integer regfile reads -system.cpu.int_regfile_writes 1261583749 # number of integer regfile writes -system.cpu.fp_regfile_reads 38 # number of floating regfile reads -system.cpu.fp_regfile_writes 50 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965641029 # number of cc regfile reads -system.cpu.cc_regfile_writes 551880821 # number of cc regfile writes -system.cpu.misc_regfile_reads 675853491 # number of misc regfile reads +system.cpu.cpi 0.997404 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.997404 # CPI: Total CPI of All Threads +system.cpu.ipc 1.002602 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.002602 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175788919 # number of integer regfile reads +system.cpu.int_regfile_writes 1261560913 # number of integer regfile writes +system.cpu.fp_regfile_reads 42 # number of floating regfile reads +system.cpu.fp_regfile_writes 52 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965670330 # number of cc regfile reads +system.cpu.cc_regfile_writes 551865131 # number of cc regfile writes +system.cpu.misc_regfile_reads 675839076 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17005885 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964949 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638186886 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17006397 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.526284 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 78340000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964949 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 17004565 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.965160 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638055083 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17005077 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.521446 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 77552500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.965160 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 423 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335687679 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335687679 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469400845 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469400845 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168785923 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168785923 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335687503 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335687503 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469335942 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469335942 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168719023 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168719023 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638186768 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638186768 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638186768 # number of overall hits -system.cpu.dcache.overall_hits::total 638186768 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17353625 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17353625 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3800124 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3800124 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638054965 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638054965 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638054965 # number of overall hits +system.cpu.dcache.overall_hits::total 638054965 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17419100 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17419100 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3867024 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3867024 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21153749 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21153749 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21153751 # number of overall misses -system.cpu.dcache.overall_misses::total 21153751 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 417050356298 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 417050356298 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149886013526 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149886013526 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 204500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 566936369824 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 566936369824 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 566936369824 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 566936369824 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486754470 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486754470 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21286124 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21286124 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21286126 # number of overall misses +system.cpu.dcache.overall_misses::total 21286126 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 415512136500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 415512136500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149273741664 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149273741664 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 290000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 290000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 564785878164 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 564785878164 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 564785878164 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 564785878164 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486755042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486755042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -781,417 +780,434 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659340517 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659340517 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659340519 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659340519 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035652 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035652 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022019 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022019 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659341089 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659341089 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659341091 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659341091 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035786 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035786 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022406 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022406 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032083 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032083 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032083 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032083 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24032.463321 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24032.463321 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39442.400702 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39442.400702 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51125 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26800.751480 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26800.751480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26800.748946 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26800.748946 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20736521 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3309459 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 945396 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67047 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.934217 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49.360285 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032284 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032284 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032284 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032284 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23853.823475 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23853.823475 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38601.710686 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38601.710686 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26533.054029 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26533.054029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26533.051536 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26533.051536 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20783046 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3318451 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 945637 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67068 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.977827 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49.478902 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4830628 # number of writebacks -system.cpu.dcache.writebacks::total 4830628 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3084713 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3084713 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1062640 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1062640 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4838877 # number of writebacks +system.cpu.dcache.writebacks::total 4838877 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151642 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3151642 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129406 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1129406 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4147353 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4147353 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4147353 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4147353 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268912 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14268912 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737484 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737484 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4281048 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4281048 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4281048 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4281048 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267458 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14267458 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737618 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737618 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17006396 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17006396 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17006397 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17006397 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 328919129806 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 328919129806 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115124697729 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 115124697729 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444043827535 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 444043827535 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444043895285 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 444043895285 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 17005076 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17005076 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17005077 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17005077 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335579712500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 335579712500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116324734517 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116324734517 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451904447017 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 451904447017 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451904515017 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 451904515017 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029311 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23051.451281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23051.451281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42054.929902 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42054.929902 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.401495 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.401495 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.403943 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.403943 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025791 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025791 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23520.637839 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23520.637839 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42491.222120 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42491.222120 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26574.679644 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26574.679644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26574.682080 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26574.682080 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 589 # number of replacements -system.cpu.icache.tags.tagsinuse 446.078018 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656940406 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1077 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 609972.521820 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 585 # number of replacements +system.cpu.icache.tags.tagsinuse 445.973645 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656944607 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1073 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 612250.332712 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 446.078018 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.871246 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.871246 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 445.973645 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.871042 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.871042 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313885139 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313885139 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656940406 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656940406 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656940406 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656940406 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656940406 # number of overall hits -system.cpu.icache.overall_hits::total 656940406 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1625 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1625 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1625 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1625 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1625 # 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number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1619 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1619 # number of overall misses +system.cpu.icache.overall_misses::total 1619 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 105131986 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 105131986 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 105131986 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 105131986 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 105131986 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 105131986 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656946226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656946226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656946226 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656946226 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656946226 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656946226 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64625.707692 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64625.707692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64625.707692 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64625.707692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64625.707692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64625.707692 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17596 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 547 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 191 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 92.125654 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 60.777778 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64936.371834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64936.371834 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64936.371834 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64936.371834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64936.371834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64936.371834 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17916 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 510 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 192 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 93.312500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 63.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 548 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 548 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 548 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 548 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 548 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 548 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76192959 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 76192959 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76192959 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 76192959 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76192959 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 76192959 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 546 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 546 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 546 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 76698989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76698989 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 76698989 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70745.551532 # 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number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70893901794 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91380975745 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91380975745 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66562530 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304087696212 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 304154258742 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66562530 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304087696212 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70893901794 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 375048160536 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192489 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192547 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 1639544 # number of writebacks +system.cpu.l2cache.writebacks::total 1639544 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3899 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3899 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 38390 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 38390 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 42289 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 42289 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 42289 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 42289 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 100257 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 100257 # number of CleanEvict MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993873 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 993873 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981601 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 981601 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1032 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1032 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2748969 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2748969 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1032 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3730570 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3731602 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1032 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3730570 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993873 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4725475 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72684245482 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72684245482 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93518423498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93518423498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 69157500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 69157500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 219665951000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 219665951000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69157500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 313184374498 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 313253531998 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69157500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 313184374498 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72684245482 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 385937777480 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358368 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358368 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219191 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.219238 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219191 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358554 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358554 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.961789 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.961789 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.192675 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.192675 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961789 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219380 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.219427 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961789 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219380 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.277614 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64249.546332 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77443.477684 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77438.502904 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71405.522362 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93146.853799 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93146.853799 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64249.546332 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81576.290522 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81571.476355 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64249.546332 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81576.290522 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79433.792501 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.277869 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 73132.327251 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 73132.327251 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95271.320524 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95271.320524 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67013.081395 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67013.081395 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79908.486054 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79908.486054 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67013.081395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83950.810331 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83946.126087 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67013.081395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83950.810331 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 73132.327251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81671.742519 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 14269946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 14269946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4830628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1298291 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737528 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38843422 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38845576 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397569600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1397638528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1298291 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23136394 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.056115 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.230143 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 14268485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 6478421 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 15219349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1327311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737665 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737665 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1073 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267412 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2727 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50995885 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398013056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1398081728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 6041496 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 40052798 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.150838 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.357891 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 21838103 94.39% 94.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1298291 5.61% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 34011302 84.92% 84.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 6041496 15.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23136394 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15749679999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1817030 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 40052798 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21844528998 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1609500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 26101043977 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3736842 # Transaction distribution -system.membus.trans_dist::ReadResp 3736842 # Transaction distribution -system.membus.trans_dist::Writeback 1637857 # Transaction distribution -system.membus.trans_dist::ReadExReq 981309 # Transaction distribution -system.membus.trans_dist::ReadExResp 981309 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11074159 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11074159 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406784512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 406784512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 25507619991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) +system.membus.trans_dist::ReadResp 3740347 # Transaction distribution +system.membus.trans_dist::Writeback 1639544 # Transaction distribution +system.membus.trans_dist::CleanEvict 3065371 # Transaction distribution +system.membus.trans_dist::ReadExReq 981875 # Transaction distribution +system.membus.trans_dist::ReadExResp 981875 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3740347 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14149359 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14149359 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407153024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 407153024 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6356008 # Request fanout histogram +system.membus.snoop_fanout::samples 9427137 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6356008 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9427137 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6356008 # Request fanout histogram -system.membus.reqLayer0.occupancy 14483850639 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 25655332661 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9427137 # Request fanout histogram +system.membus.reqLayer0.occupancy 17268043532 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 25679820043 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |