diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/o3-timing')
3 files changed, 41 insertions, 33 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 9dd6f437e..b3f283cca 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -31,22 +31,18 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -69,23 +65,15 @@ forwardComSize=5 fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -97,7 +85,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -126,6 +113,24 @@ workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -522,7 +527,7 @@ egid=100 env= errout=cerr euid=100 -executable=/gem5/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 0fb886b0f..fa5d435db 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 4 2013 21:17:24 -gem5 started Jan 5 2013 00:51:58 -gem5 executing on u200540 +gem5 compiled Jan 23 2013 19:43:25 +gem5 started Jan 23 2013 21:12:52 +gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 506577346000 because target called exit() +Exiting @ tick 506353996500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index dd9ca10a0..fe1996e1b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.506354 # Nu sim_ticks 506353996500 # Number of ticks simulated final_tick 506353996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136322 # Simulator instruction rate (inst/s) -host_op_rate 152077 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44690362 # Simulator tick rate (ticks/s) -host_mem_usage 507940 # Number of bytes of host memory used -host_seconds 11330.27 # Real time elapsed on the host +host_inst_rate 105319 # Simulator instruction rate (inst/s) +host_op_rate 117491 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34526611 # Simulator tick rate (ticks/s) +host_mem_usage 552892 # Number of bytes of host memory used +host_seconds 14665.62 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory @@ -192,6 +192,15 @@ system.physmem.writeRowHits 189005 # Nu system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate 17.17 # Row buffer hit rate for writes system.physmem.avgGap 151240.81 # Average gap between requests +system.cpu.branchPred.lookups 301930111 # Number of BP lookups +system.cpu.branchPred.condPredicted 248173247 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15201095 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 171785530 # Number of BTB lookups +system.cpu.branchPred.BTBHits 160276899 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 93.300582 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17551988 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -238,14 +247,6 @@ system.cpu.workload.num_syscalls 46 # Nu system.cpu.numCycles 1012707994 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 301930111 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 248173247 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 15201095 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 171785530 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 160276899 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 17551988 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 296178013 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 2176838116 # Number of instructions fetch has processed system.cpu.fetch.Branches 301930111 # Number of branches that fetch encountered |