diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt | 226 |
1 files changed, 113 insertions, 113 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 6ff1664e3..8d9905464 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu sim_ticks 2391205115000 # Number of ticks simulated final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1213159 # Simulator instruction rate (inst/s) -host_op_rate 1353897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1885227488 # Simulator tick rate (ticks/s) -host_mem_usage 231376 # Number of bytes of host memory used -host_seconds 1268.39 # Real time elapsed on the host +host_inst_rate 809589 # Simulator instruction rate (inst/s) +host_op_rate 903509 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1258086461 # Simulator tick rate (ticks/s) +host_mem_usage 287292 # Number of bytes of host memory used +host_seconds 1900.67 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -177,114 +177,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9111140 # number of replacements -system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use -system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits -system.cpu.dcache.overall_hits::total 645854937 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses -system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks -system.cpu.dcache.writebacks::total 3697418 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1926075 # number of replacements system.cpu.l2cache.tagsinuse 30987.094489 # Cycle average of tags in use system.cpu.l2cache.total_refs 8967572 # Total number of references to valid blocks. @@ -423,5 +315,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9111140 # number of replacements +system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use +system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits +system.cpu.dcache.overall_hits::total 645854937 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses +system.cpu.dcache.overall_misses::total 9115236 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks +system.cpu.dcache.writebacks::total 3697418 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |