diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt | 456 |
1 files changed, 236 insertions, 220 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index de9b22f80..8e22dfda9 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.391205 # Number of seconds simulated -sim_ticks 2391205115000 # Number of ticks simulated -final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.363671 # Number of seconds simulated +sim_ticks 2363670998000 # Number of ticks simulated +final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 867002 # Simulator instruction rate (inst/s) -host_op_rate 967582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1347305237 # Simulator tick rate (ticks/s) -host_mem_usage 310408 # Number of bytes of host memory used -host_seconds 1774.81 # Real time elapsed on the host +host_inst_rate 1066052 # Simulator instruction rate (inst/s) +host_op_rate 1148821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1637550718 # Simulator tick rate (ticks/s) +host_mem_usage 316024 # Number of bytes of host memory used +host_seconds 1443.42 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated -sim_ops 1717270334 # Number of ops (including micro ops) simulated +sim_ops 1658228914 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data 1958158 # Nu system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 79651138 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 80578984 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1177898 # Transaction distribution system.membus.trans_dist::ReadResp 1177898 # Transaction distribution system.membus.trans_dist::Writeback 1017198 # Transaction distribution @@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1 system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 190462208 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -138,73 +138,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4782410230 # number of cpu cycles simulated +system.cpu.numCycles 4727341996 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759601 # Number of instructions committed -system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses +system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330256 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls -system.cpu.num_int_insts 1536941842 # number of integer instructions +system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls +system.cpu.num_int_insts 1477900422 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 9304895467 # number of times the integer registers were read -system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written +system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read +system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 660773815 # number of memory refs -system.cpu.num_load_insts 485926769 # Number of load instructions +system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read +system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written +system.cpu.num_mem_refs 633153380 # number of memory refs +system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4782410230 # Number of busy cycles +system.cpu.num_busy_cycles 4727341996 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 213462426 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1061599760 61.61% 61.61% # Class of executed instruction -system.cpu.op_class::IntMult 700322 0.04% 61.65% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::MemRead 485926769 28.20% 89.85% # Class of executed instruction -system.cpu.op_class::MemWrite 174847046 10.15% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction +system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction +system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1723073900 # Class of executed instruction +system.cpu.op_class::total 1664032480 # Class of executed instruction system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id @@ -224,12 +226,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses @@ -242,12 +244,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -262,44 +264,44 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1926075 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26880 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1732 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26841 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses @@ -327,17 +329,17 @@ system.cpu.l2cache.demand_misses::total 1958774 # nu system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32099000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61225555000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 61257654000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608829000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40608829000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32099000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101866483000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32099000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101866483000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) @@ -362,17 +364,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.214875 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,17 +396,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1958774 system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses @@ -416,92 +418,98 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1319055826 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1319055826 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits -system.cpu.dcache.overall_hits::total 645854937 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits +system.cpu.dcache.overall_hits::total 618379947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -512,40 +520,48 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks system.cpu.dcache.writebacks::total 3697418 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 346939438 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution |