diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt | 46 |
1 files changed, 41 insertions, 5 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 8d9905464..7f261f2f5 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu sim_ticks 2391205115000 # Number of ticks simulated final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 809589 # Simulator instruction rate (inst/s) -host_op_rate 903509 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1258086461 # Simulator tick rate (ticks/s) -host_mem_usage 287292 # Number of bytes of host memory used -host_seconds 1900.67 # Real time elapsed on the host +host_inst_rate 1401168 # Simulator instruction rate (inst/s) +host_op_rate 1563717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2177389973 # Simulator tick rate (ticks/s) +host_mem_usage 243008 # Number of bytes of host memory used +host_seconds 1098.20 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 27225047 # To system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 79651138 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1177898 # Transaction distribution +system.membus.trans_dist::ReadResp 1177898 # Transaction distribution +system.membus.trans_dist::Writeback 1017198 # Transaction distribution +system.membus.trans_dist::ReadExReq 780876 # Transaction distribution +system.membus.trans_dist::ReadExResp 780876 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 4934746 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4934746 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190462208 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21927890 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 21929166 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 820009856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 820050688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- |