diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt | 655 |
1 files changed, 655 insertions, 0 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index e69de29bb..6f79ed44a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,655 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.377030 # Number of seconds simulated +sim_ticks 2377029670500 # Number of ticks simulated +final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 651336 # Simulator instruction rate (inst/s) +host_op_rate 701905 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1006163929 # Simulator tick rate (ticks/s) +host_mem_usage 265624 # Number of bytes of host memory used +host_seconds 2362.47 # Real time elapsed on the host +sim_insts 1538759602 # Number of instructions simulated +sim_ops 1658228915 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory +system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory +system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.numCycles 4754059341 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1538759602 # Number of instructions committed +system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses +system.cpu.num_func_calls 27330256 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls +system.cpu.num_int_insts 1477900422 # number of integer instructions +system.cpu.num_fp_insts 36 # number of float instructions +system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read +system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written +system.cpu.num_fp_register_reads 24 # number of times the floating registers were read +system.cpu.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu.num_cc_register_reads 6356387678 # number of times the CC registers were read +system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written +system.cpu.num_mem_refs 633153380 # number of memory refs +system.cpu.num_load_insts 458306334 # Number of load instructions +system.cpu.num_store_insts 174847046 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 213462427 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction +system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction +system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1664032481 # Class of executed instruction +system.cpu.dcache.tags.replacements 9111140 # number of replacements +system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits +system.cpu.dcache.overall_hits::total 618379947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses +system.cpu.dcache.overall_misses::total 9115236 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # 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average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks +system.cpu.l2cache.writebacks::total 1021127 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919027 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1169580 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution +system.membus.trans_dist::CleanEvict 897056 # Transaction distribution +system.membus.trans_dist::ReadExReq 782134 # Transaction distribution +system.membus.trans_dist::ReadExResp 782134 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3869897 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3869897 # Request fanout histogram +system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |