diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt | 871 | ||||
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 1647 |
2 files changed, 1279 insertions, 1239 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 0ee27457c..0b0903e3c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,68 +1,68 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.116861 # Number of seconds simulated -sim_ticks 1116860578500 # Number of ticks simulated -final_tick 1116860578500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.116866 # Number of seconds simulated +sim_ticks 1116865668500 # Number of ticks simulated +final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 228405 # Simulator instruction rate (inst/s) -host_op_rate 246072 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 165157932 # Simulator tick rate (ticks/s) -host_mem_usage 318996 # Number of bytes of host memory used -host_seconds 6762.38 # Real time elapsed on the host +host_inst_rate 315195 # Simulator instruction rate (inst/s) +host_op_rate 339575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 227915704 # Simulator tick rate (ticks/s) +host_mem_usage 272300 # Number of bytes of host memory used +host_seconds 4900.35 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 50176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory -system.physmem.bytes_read::total 130981888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50176 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2045808 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2046592 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 44926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117231922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117276848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 44926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 44926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60175704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60175704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60175704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 44926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117231922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177452552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2046592 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 44868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117231388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 44868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 44868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 44868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117231388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2046591 # Number of read requests accepted system.physmem.writeReqs 1050123 # Number of write requests accepted -system.physmem.readBursts 2046592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 130898112 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83776 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 130898176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83648 # Total number of bytes read from write queue system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130981888 # Total read bytes from the system interface side +system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1309 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 1307 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 127279 # Per bank write bursts system.physmem.perBankRdBursts::1 124661 # Per bank write bursts system.physmem.perBankRdBursts::2 121601 # Per bank write bursts -system.physmem.perBankRdBursts::3 123659 # Per bank write bursts +system.physmem.perBankRdBursts::3 123656 # Per bank write bursts system.physmem.perBankRdBursts::4 122620 # Per bank write bursts -system.physmem.perBankRdBursts::5 122678 # Per bank write bursts +system.physmem.perBankRdBursts::5 122679 # Per bank write bursts system.physmem.perBankRdBursts::6 123247 # Per bank write bursts -system.physmem.perBankRdBursts::7 123768 # Per bank write bursts -system.physmem.perBankRdBursts::8 131395 # Per bank write bursts +system.physmem.perBankRdBursts::7 123770 # Per bank write bursts +system.physmem.perBankRdBursts::8 131396 # Per bank write bursts system.physmem.perBankRdBursts::9 133511 # Per bank write bursts -system.physmem.perBankRdBursts::10 132082 # Per bank write bursts -system.physmem.perBankRdBursts::11 133309 # Per bank write bursts +system.physmem.perBankRdBursts::10 132081 # Per bank write bursts +system.physmem.perBankRdBursts::11 133308 # Per bank write bursts system.physmem.perBankRdBursts::12 133249 # Per bank write bursts -system.physmem.perBankRdBursts::13 133361 # Per bank write bursts -system.physmem.perBankRdBursts::14 129308 # Per bank write bursts +system.physmem.perBankRdBursts::13 133362 # Per bank write bursts +system.physmem.perBankRdBursts::14 129309 # Per bank write bursts system.physmem.perBankRdBursts::15 129555 # Per bank write bursts system.physmem.perBankWrBursts::0 66136 # Per bank write bursts system.physmem.perBankWrBursts::1 64410 # Per bank write bursts @@ -71,25 +71,25 @@ system.physmem.perBankWrBursts::3 63006 # Pe system.physmem.perBankWrBursts::4 63000 # Per bank write bursts system.physmem.perBankWrBursts::5 63100 # Per bank write bursts system.physmem.perBankWrBursts::6 64443 # Per bank write bursts -system.physmem.perBankWrBursts::7 65435 # Per bank write bursts -system.physmem.perBankWrBursts::8 67311 # Per bank write bursts -system.physmem.perBankWrBursts::9 67795 # Per bank write bursts -system.physmem.perBankWrBursts::10 67548 # Per bank write bursts +system.physmem.perBankWrBursts::7 65436 # Per bank write bursts +system.physmem.perBankWrBursts::8 67310 # Per bank write bursts +system.physmem.perBankWrBursts::9 67797 # Per bank write bursts +system.physmem.perBankWrBursts::10 67549 # Per bank write bursts system.physmem.perBankWrBursts::11 67882 # Per bank write bursts -system.physmem.perBankWrBursts::12 67328 # Per bank write bursts +system.physmem.perBankWrBursts::12 67326 # Per bank write bursts system.physmem.perBankWrBursts::13 67793 # Per bank write bursts -system.physmem.perBankWrBursts::14 66483 # Per bank write bursts +system.physmem.perBankWrBursts::14 66482 # Per bank write bursts system.physmem.perBankWrBursts::15 65854 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1116860484000 # Total gap between requests +system.physmem.totGap 1116865574000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2046592 # Read request sizes (log2) +system.physmem.readPktSize::6 2046591 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1050123 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1916633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1916619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56911 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 61204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see @@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1910141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.711749 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.835384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.555895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485377 77.76% 77.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305179 15.98% 93.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52494 2.75% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21040 1.10% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13364 0.70% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7561 0.40% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5492 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5154 0.27% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14480 0.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1910141 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61138 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.410579 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 159.595244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61092 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1910138 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.711175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.836423 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.540224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1485349 77.76% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305158 15.98% 93.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52532 2.75% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21047 1.10% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13374 0.70% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7565 0.40% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5491 0.29% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5162 0.27% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14460 0.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1910138 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61136 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.411672 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 159.590236 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61090 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 21 0.03% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes @@ -219,27 +219,27 @@ system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61138 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61138 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.175897 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.140866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.098115 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27038 44.22% 44.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1118 1.83% 46.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28658 46.87% 92.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3907 6.39% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 362 0.59% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 47 0.08% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61136 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.176459 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.141461 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.097536 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27008 44.18% 44.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1128 1.85% 46.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28688 46.92% 92.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3895 6.37% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 363 0.59% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 46 0.08% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61138 # Writes before turning the bus around for reads -system.physmem.totQLat 38118822750 # Total ticks spent queuing -system.physmem.totMemAccLat 76467879000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10226415000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18637.43 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 61136 # Writes before turning the bus around for reads +system.physmem.totQLat 38124700750 # Total ticks spent queuing +system.physmem.totMemAccLat 76473775750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10226420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18640.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37387.43 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37390.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s @@ -250,49 +250,53 @@ system.physmem.busUtilRead 0.92 # Da system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing -system.physmem.readRowHits 773327 # Number of row buffer hits during reads -system.physmem.writeRowHits 411912 # Number of row buffer hits during writes +system.physmem.readRowHits 773341 # Number of row buffer hits during reads +system.physmem.writeRowHits 411895 # Number of row buffer hits during writes system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.23 # Row buffer hit rate for writes -system.physmem.avgGap 360659.76 # Average gap between requests +system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes +system.physmem.avgGap 360661.52 # Average gap between requests system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7038745560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3840585375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7718170200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3318446880 # Energy for write commands per rank (pJ) +system.physmem_0.actEnergy 7039078200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3840766875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7717881600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 420695682570 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 301084680000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 816644156985 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.196552 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 498171573500 # Time in different power states +system.physmem_0.actBackEnergy 420697412235 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301083150000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 816644588670 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.196952 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 498171344000 # Time in different power states system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 581394006750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 581396539000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7401920400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4038746250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8234982600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3486201120 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 7401549960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4038544125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8234959200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 429157184085 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 293662305750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 818929186605 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.242498 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 485776924250 # Time in different power states +system.physmem_1.actBackEnergy 429293377035 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 293542830000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 818945301360 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.256935 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 485580062750 # Time in different power states system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 593789084750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 239639085 # Number of BP lookups -system.cpu.branchPred.condPredicted 186342301 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14526140 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 130646105 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122079391 # Number of BTB hits +system.cpu.branchPred.lookups 239639355 # Number of BP lookups +system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 130646338 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122079091 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.442809 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15657029 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 93.442413 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15657057 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 537 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 230 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 307 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,68 +415,103 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2233721157 # number of cpu cycles simulated +system.cpu.numCycles 2233731337 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41470128 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41470388 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446183 # CPI: cycles per instruction -system.cpu.ipc 0.691475 # IPC: instructions per cycle -system.cpu.tickCycles 1834122800 # Number of cycles that the object actually ticked -system.cpu.idleCycles 399598357 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.446190 # CPI: cycles per instruction +system.cpu.ipc 0.691472 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction +system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction +system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 1664032481 # Class of committed instruction +system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked +system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 9221041 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.616187 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624218895 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.665000 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.665004 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616187 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616095 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 245 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276841907 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276841907 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453887715 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453887715 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331057 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331057 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331073 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624218772 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624218772 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624218773 # number of overall hits -system.cpu.dcache.overall_hits::total 624218773 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 624218805 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624218805 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624218806 # number of overall hits +system.cpu.dcache.overall_hits::total 624218806 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7334498 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7334498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254990 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254990 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254974 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254974 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9589488 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9589488 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9589490 # number of overall misses -system.cpu.dcache.overall_misses::total 9589490 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 190927662500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 190927662500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109073789000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109073789000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 300001451500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 300001451500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 300001451500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 300001451500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461222213 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461222213 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9589472 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9589472 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9589474 # number of overall misses +system.cpu.dcache.overall_misses::total 9589474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 190926660000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 190926660000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109083916000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109083916000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 300010576000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 300010576000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 300010576000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 300010576000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461222230 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461222230 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -481,10 +520,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633808260 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633808260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633808263 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633808263 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633808277 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633808277 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633808280 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633808280 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses @@ -495,14 +534,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.456072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.456072 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48369.965720 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48369.965720 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31284.407624 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31284.407624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.401100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31284.401100 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.319390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.319390 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48374.799887 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48374.799887 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.411334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31285.411334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.404809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31285.404809 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,16 +550,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3684566 # number of writebacks -system.cpu.dcache.writebacks::total 3684566 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3684567 # number of writebacks +system.cpu.dcache.writebacks::total 3684567 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364137 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364137 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364352 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364352 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364352 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364352 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364121 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364121 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364336 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364336 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364336 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364336 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334283 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7334283 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890853 # number of WriteReq MSHR misses @@ -531,16 +570,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9225136 system.cpu.dcache.demand_mshr_misses::total 9225136 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9225137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9225137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183587623500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 183587623500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84772423500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84772423500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183586477500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 183586477500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84779361000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84779361000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268360047000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 268360047000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268360121000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 268360121000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268365838500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 268365838500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268365912500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 268365912500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -551,69 +590,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.434361 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.434361 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44832.900019 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44832.900019 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.278109 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.278109 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.091138 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.091138 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.096006 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.096006 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.384835 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 465281420 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567416.365854 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.384835 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322942 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322942 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 660.385482 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322454 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322454 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 930565300 # Number of tag accesses -system.cpu.icache.tags.data_accesses 930565300 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 465281420 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 465281420 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 465281420 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 465281420 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 465281420 # number of overall hits -system.cpu.icache.overall_hits::total 465281420 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses -system.cpu.icache.overall_misses::total 820 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62291000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62291000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62291000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62291000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62291000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62291000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 465282240 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 465282240 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 465282240 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 465282240 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 465282240 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 465282240 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses +system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 465281510 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 465281510 # number of overall hits +system.cpu.icache.overall_hits::total 465281510 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 819 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 819 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 819 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 819 # number of overall misses +system.cpu.icache.overall_misses::total 819 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62402500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62402500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62402500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62402500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62402500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62402500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465282329 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465282329 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465282329 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465282329 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465282329 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465282329 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75964.634146 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75964.634146 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75964.634146 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75964.634146 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75964.634146 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75964.634146 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76193.528694 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76193.528694 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76193.528694 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76193.528694 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -624,133 +663,133 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 29 # number of writebacks system.cpu.icache.writebacks::total 29 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61471000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 61471000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61471000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 61471000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61471000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 61471000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61583500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 61583500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61583500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 61583500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61583500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61583500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74964.634146 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74964.634146 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74964.634146 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74964.634146 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74964.634146 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74964.634146 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2013920 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31258.306174 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14509192 # Total number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2013919 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.099490 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14832.753669 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.505297 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.047209 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.452660 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.500459 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.953928 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16398.892088 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.452664 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000807 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.500454 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.953926 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1251 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1250 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 151498012 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 151498012 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 3684566 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3684566 # number of WritebackDirty hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 29 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1089694 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1089694 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 35 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 35 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089631 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6089631 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 35 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7179325 # number of demand (read+write) hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 36 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7179324 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 7179360 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 35 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7179325 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 36 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7179324 # number of overall hits system.cpu.l2cache.overall_hits::total 7179360 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 801159 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 801159 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 785 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 785 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244653 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1244653 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 785 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2045812 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2046597 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2045812 # number of overall misses -system.cpu.l2cache.overall_misses::total 2046597 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70434494500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 70434494500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59842000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 59842000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108638363500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 108638363500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 59842000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 179072858000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179132700000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 59842000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 179072858000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179132700000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3684566 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3684566 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 783 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 783 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244654 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1244654 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 783 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2045813 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2046596 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 783 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2045813 # number of overall misses +system.cpu.l2cache.overall_misses::total 2046596 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70441435500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70441435500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59945000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 59945000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108637226500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 108637226500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 59945000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 179078662000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 179138607000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 59945000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 179078662000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 179138607000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3684567 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3684567 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 29 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 29 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890853 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1890853 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 820 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 820 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 819 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 819 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7334284 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 7334284 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 820 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 819 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 9225137 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9225957 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 820 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9225956 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 819 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9225137 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9225957 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9225956 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423702 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.423702 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.957317 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.957317 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169703 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169703 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.957317 # miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.956044 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.956044 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169704 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169704 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956044 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.221765 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.221830 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.957317 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956044 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87915.750182 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87915.750182 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76231.847134 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76231.847134 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87284.057083 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87284.057083 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76231.847134 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87531.433973 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87527.099864 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76231.847134 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87531.433973 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87527.099864 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87924.413880 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87924.413880 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76558.109834 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76558.109834 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87283.073449 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87283.073449 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76558.109834 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87530.028887 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76558.109834 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87530.028887 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -761,131 +800,127 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks system.cpu.l2cache.writebacks::total 1050123 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 214 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 214 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801159 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 801159 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 784 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 784 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 783 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 783 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 784 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2045808 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2046592 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 784 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2046591 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2045808 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2046592 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62422904500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62422904500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 51986500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 51986500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96191610000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96191610000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51986500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158614514500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 158666501000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51986500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158614514500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158666501000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 2046591 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62429845500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62429845500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52115000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52115000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96190393500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96190393500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52115000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158620239000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158672354000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52115000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158620239000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158672354000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423702 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423702 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956098 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956098 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956044 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169703 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169703 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956098 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956098 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77915.750182 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77915.750182 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66309.311224 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66309.311224 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77284.125886 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77284.125886 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66309.311224 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77531.476316 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77527.177376 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66309.311224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77531.476316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77527.177376 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77924.413880 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77924.413880 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66558.109834 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66558.109834 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77283.148502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77283.148502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 18447027 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1287 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1281 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7335104 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4734689 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6500272 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6500270 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 820 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1669 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1667 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671315 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27672984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27672982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826221056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2013920 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 11239877 # Request fanout histogram +system.cpu.toL2Bus.snoops 2013919 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11239875 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.016091 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.016088 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11236984 99.97% 99.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2887 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11236983 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2886 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11239877 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12908108500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11239875 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12908109000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1230499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13837707496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1245433 # Transaction distribution +system.membus.trans_dist::ReadResp 1245432 # Transaction distribution system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution system.membus.trans_dist::CleanEvict 962724 # Transaction distribution system.membus.trans_dist::ReadExReq 801159 # Transaction distribution system.membus.trans_dist::ReadExResp 801159 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1245433 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106031 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6106031 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198189760 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1245432 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106029 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6106029 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4059439 # Request fanout histogram +system.membus.snoop_fanout::samples 4059438 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4059439 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4059438 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4059439 # Request fanout histogram -system.membus.reqLayer0.occupancy 8663213500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4059438 # Request fanout histogram +system.membus.reqLayer0.occupancy 8663216000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11191513500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11191487250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 659d2c639..ad14d9d64 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.767851 # Number of seconds simulated -sim_ticks 767851412000 # Number of ticks simulated -final_tick 767851412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.767804 # Number of seconds simulated +sim_ticks 767803843500 # Number of ticks simulated +final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96147 # Simulator instruction rate (inst/s) -host_op_rate 103584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47797800 # Simulator tick rate (ticks/s) -host_mem_usage 342312 # Number of bytes of host memory used -host_seconds 16064.58 # Real time elapsed on the host +host_inst_rate 188017 # Simulator instruction rate (inst/s) +host_op_rate 202560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93463451 # Simulator tick rate (ticks/s) +host_mem_usage 313392 # Number of bytes of host memory used +host_seconds 8215.02 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 64960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 235334976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63685504 # Number of bytes read from this memory -system.physmem.bytes_read::total 299085440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104625984 # Number of bytes written to this memory -system.physmem.bytes_written::total 104625984 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1015 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3677109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 995086 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4673210 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1634781 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1634781 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 84600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 306485047 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82939880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 389509527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 84600 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84600 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136258112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136258112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136258112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 84600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 306485047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82939880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 525767639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4673210 # Number of read requests accepted -system.physmem.writeReqs 1634781 # Number of write requests accepted -system.physmem.readBursts 4673210 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1634781 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 298595648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 489792 # Total number of bytes read from write queue -system.physmem.bytesWritten 104623680 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299085440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104625984 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7653 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 16 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory +system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory +system.physmem.bytes_written::total 104697344 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3676881 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 995485 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4673385 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1635896 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1635896 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 84938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 306485030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82978277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 389548245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 84938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136359495 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136359495 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136359495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 84938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 306485030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82978277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 525907740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4673385 # Number of read requests accepted +system.physmem.writeReqs 1635896 # Number of write requests accepted +system.physmem.readBursts 4673385 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1635896 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 298598336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 498304 # Total number of bytes read from write queue +system.physmem.bytesWritten 104693696 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299096640 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104697344 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7786 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301092 # Per bank write bursts -system.physmem.perBankRdBursts::1 298585 # Per bank write bursts -system.physmem.perBankRdBursts::2 284412 # Per bank write bursts -system.physmem.perBankRdBursts::3 287553 # Per bank write bursts -system.physmem.perBankRdBursts::4 288019 # Per bank write bursts -system.physmem.perBankRdBursts::5 285340 # Per bank write bursts -system.physmem.perBankRdBursts::6 281024 # Per bank write bursts -system.physmem.perBankRdBursts::7 277791 # Per bank write bursts -system.physmem.perBankRdBursts::8 293545 # Per bank write bursts -system.physmem.perBankRdBursts::9 299289 # Per bank write bursts -system.physmem.perBankRdBursts::10 291195 # Per bank write bursts -system.physmem.perBankRdBursts::11 297241 # Per bank write bursts -system.physmem.perBankRdBursts::12 298946 # Per bank write bursts -system.physmem.perBankRdBursts::13 298565 # Per bank write bursts -system.physmem.perBankRdBursts::14 293948 # Per bank write bursts -system.physmem.perBankRdBursts::15 289012 # Per bank write bursts -system.physmem.perBankWrBursts::0 103815 # Per bank write bursts -system.physmem.perBankWrBursts::1 101663 # Per bank write bursts -system.physmem.perBankWrBursts::2 99081 # Per bank write bursts -system.physmem.perBankWrBursts::3 99729 # Per bank write bursts -system.physmem.perBankWrBursts::4 98947 # Per bank write bursts -system.physmem.perBankWrBursts::5 98825 # Per bank write bursts -system.physmem.perBankWrBursts::6 102537 # Per bank write bursts -system.physmem.perBankWrBursts::7 104314 # Per bank write bursts -system.physmem.perBankWrBursts::8 105187 # Per bank write bursts -system.physmem.perBankWrBursts::9 104412 # Per bank write bursts -system.physmem.perBankWrBursts::10 101681 # Per bank write bursts -system.physmem.perBankWrBursts::11 102588 # Per bank write bursts -system.physmem.perBankWrBursts::12 102740 # Per bank write bursts -system.physmem.perBankWrBursts::13 102708 # Per bank write bursts -system.physmem.perBankWrBursts::14 104126 # Per bank write bursts -system.physmem.perBankWrBursts::15 102392 # Per bank write bursts +system.physmem.perBankRdBursts::0 301126 # Per bank write bursts +system.physmem.perBankRdBursts::1 298685 # Per bank write bursts +system.physmem.perBankRdBursts::2 284250 # Per bank write bursts +system.physmem.perBankRdBursts::3 287696 # Per bank write bursts +system.physmem.perBankRdBursts::4 287908 # Per bank write bursts +system.physmem.perBankRdBursts::5 285921 # Per bank write bursts +system.physmem.perBankRdBursts::6 280645 # Per bank write bursts +system.physmem.perBankRdBursts::7 277366 # Per bank write bursts +system.physmem.perBankRdBursts::8 293768 # Per bank write bursts +system.physmem.perBankRdBursts::9 299240 # Per bank write bursts +system.physmem.perBankRdBursts::10 292091 # Per bank write bursts +system.physmem.perBankRdBursts::11 297828 # Per bank write bursts +system.physmem.perBankRdBursts::12 299005 # Per bank write bursts +system.physmem.perBankRdBursts::13 298032 # Per bank write bursts +system.physmem.perBankRdBursts::14 293386 # Per bank write bursts +system.physmem.perBankRdBursts::15 288652 # Per bank write bursts +system.physmem.perBankWrBursts::0 103980 # Per bank write bursts +system.physmem.perBankWrBursts::1 101811 # Per bank write bursts +system.physmem.perBankWrBursts::2 99205 # Per bank write bursts +system.physmem.perBankWrBursts::3 99712 # Per bank write bursts +system.physmem.perBankWrBursts::4 99000 # Per bank write bursts +system.physmem.perBankWrBursts::5 99026 # Per bank write bursts +system.physmem.perBankWrBursts::6 102693 # Per bank write bursts +system.physmem.perBankWrBursts::7 104157 # Per bank write bursts +system.physmem.perBankWrBursts::8 105172 # Per bank write bursts +system.physmem.perBankWrBursts::9 104159 # Per bank write bursts +system.physmem.perBankWrBursts::10 102137 # Per bank write bursts +system.physmem.perBankWrBursts::11 102620 # Per bank write bursts +system.physmem.perBankWrBursts::12 102863 # Per bank write bursts +system.physmem.perBankWrBursts::13 102594 # Per bank write bursts +system.physmem.perBankWrBursts::14 104213 # Per bank write bursts +system.physmem.perBankWrBursts::15 102497 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 767851370500 # Total gap between requests +system.physmem.totGap 767803802500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4673210 # Read request sizes (log2) +system.physmem.readPktSize::6 4673385 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1634781 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2763298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1028318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 325143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 231238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 149204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 81551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37590 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23700 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18069 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1700 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1635896 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2761676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1029435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 325938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 231496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 148985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 81565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 107211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 109230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 110922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 111311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 100806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 100214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 73202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 109489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 111204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 101152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,116 +197,120 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4241219 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 95.071143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.963204 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.762534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3377855 79.64% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 665363 15.69% 95.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 95455 2.25% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35191 0.83% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22820 0.54% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12430 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7284 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5212 0.12% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19609 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4241219 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97672 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.767497 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 100.584321 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95276 97.55% 97.55% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1151 1.18% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 710 0.73% 99.45% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 401 0.41% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 104 0.11% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4243508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 95.037234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.939445 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.771916 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3380789 79.67% 79.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 664864 15.67% 95.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95298 2.25% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35170 0.83% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22966 0.54% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12163 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7344 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19569 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4243508 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97753 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.727814 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 100.001834 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95363 97.56% 97.56% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1154 1.18% 98.74% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 681 0.70% 99.43% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 412 0.42% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 112 0.11% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 14 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 8 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3840-4095 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-4863 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97672 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97672 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.737089 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.693249 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.262570 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 68211 69.84% 69.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2039 2.09% 71.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18248 18.68% 90.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5781 5.92% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 2040 2.09% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 736 0.75% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 303 0.31% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 177 0.18% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 71 0.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 35 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 22 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 97753 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97753 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.734412 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.690766 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.259650 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 68350 69.92% 69.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1981 2.03% 71.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18352 18.77% 90.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5702 5.83% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2016 2.06% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 741 0.76% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 311 0.32% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 155 0.16% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 75 0.08% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 43 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 16 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97672 # Writes before turning the bus around for reads -system.physmem.totQLat 128403949042 # Total ticks spent queuing -system.physmem.totMemAccLat 215883142792 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23327785000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27521.68 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::35 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97753 # Writes before turning the bus around for reads +system.physmem.totQLat 128478496877 # Total ticks spent queuing +system.physmem.totMemAccLat 215958478127 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23327995000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27537.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46271.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 388.87 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 136.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 389.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.26 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46287.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 388.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 136.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 389.55 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.36 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.10 # Data bus utilization in percentage system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing -system.physmem.readRowHits 1711348 # Number of row buffer hits during reads -system.physmem.writeRowHits 347723 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.27 # Row buffer hit rate for writes -system.physmem.avgGap 121726.77 # Average gap between requests -system.physmem.pageHitRate 32.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15936283440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8695392750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 17969468400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5241691440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50152152960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 414929915685 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 96735845250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 609660749925 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.985115 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 158402074288 # Time in different power states -system.physmem_0.memoryStateTime::REF 25640160000 # Time in different power states +system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing +system.physmem.readRowHits 1710736 # Number of row buffer hits during reads +system.physmem.writeRowHits 347188 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.22 # Row buffer hit rate for writes +system.physmem.avgGap 121694.34 # Average gap between requests +system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15941658600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8698325625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 17967846000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5246104320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 414557114310 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 97034832000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 609594982455 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.947771 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 158900831773 # Time in different power states +system.physmem_0.memoryStateTime::REF 25638600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 583806871462 # Time in different power states +system.physmem_0.memoryStateTime::ACT 583262954477 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16127249040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8799590250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18421525200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5351352480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50152152960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 410152468095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100926587250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 609930925275 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.336977 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165409997970 # Time in different power states -system.physmem_1.memoryStateTime::REF 25640160000 # Time in different power states +system.physmem_1.actEnergy 16139254320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8806140750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18423607800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5354132400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 410075734410 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.363055 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states +system.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 576799157530 # Time in different power states +system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286283871 # Number of BP lookups -system.cpu.branchPred.condPredicted 223409198 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14630000 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157660833 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150354422 # Number of BTB hits +system.cpu.branchPred.lookups 286292198 # Number of BP lookups +system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150355883 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.365741 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16641462 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1888 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -425,128 +429,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1535702825 # number of cpu cycles simulated +system.cpu.numCycles 1535607688 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13928194 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067545272 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286283871 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166995884 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1507053814 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29284843 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 194 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 878 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656961352 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 924 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1535625501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.442414 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29287239 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 992 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656968436 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 958 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1535531474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.442524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228151 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 453179554 29.51% 29.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465452437 30.31% 59.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101425758 6.60% 66.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515567752 33.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 453078112 29.51% 29.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465445913 30.31% 59.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101427094 6.61% 66.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515580355 33.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1535625501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.186419 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.346319 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74705832 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 538167437 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849914387 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58196125 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14641720 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42203366 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 738 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037249572 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52491206 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14641720 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139798655 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 457197163 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837846796 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86126990 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976444651 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26741715 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45304447 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126733 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1592000 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25068959 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985917884 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128448478 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432959376 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 137 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1535531474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.186436 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.346420 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74706893 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 538056624 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849925630 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58199384 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14642943 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42203258 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 730 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037275151 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52500118 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14642943 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139803593 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 457092273 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13624 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837854747 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86124294 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976468269 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26746953 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45300136 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126625 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1588286 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25069373 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985943496 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128568325 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432995559 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 145 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 311018939 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 156 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 147 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111499439 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542575800 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199311764 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26984794 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29485637 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1948029914 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 213 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857440521 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13485383 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283997711 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647527066 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1535625501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.209566 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150575 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 311044551 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 174 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111502635 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542585286 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199312070 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26927303 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29234152 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1948047142 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857492479 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13497229 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 284014957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647584155 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1535531474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.209674 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150607 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 582643896 37.94% 37.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326148429 21.24% 59.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378192784 24.63% 83.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219661214 14.30% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28973008 1.89% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6170 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 582548107 37.94% 37.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326134076 21.24% 59.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378190631 24.63% 83.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219663672 14.31% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28988815 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6173 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1535625501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1535531474 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166041601 41.02% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1966 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191453028 47.29% 88.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47322574 11.69% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166038532 40.99% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1976 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191466165 47.27% 88.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47567904 11.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138257310 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800951 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138257084 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800920 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -568,88 +572,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532072663 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186309545 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532121986 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186312436 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857440521 # Type of FU issued -system.cpu.iq.rate 1.209505 # Inst issue rate -system.cpu.iq.fu_busy_cnt 404819169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.217945 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5668810855 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2232040657 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805715757 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 1857492479 # Type of FU issued +system.cpu.iq.rate 1.209614 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405074577 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218076 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5669087998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2232075127 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805719723 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 240 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262259556 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262566922 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17798811 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 17809734 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84269466 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66606 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13290 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24464719 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84278952 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66732 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13280 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24465025 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4470256 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4868274 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4505677 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4870984 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14641720 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25371637 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1306573 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1948030205 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14642943 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25375759 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1295309 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1948047519 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542575800 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199311764 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 151 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159252 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1145955 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13290 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7700252 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8704527 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16404779 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827784428 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516894749 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29656093 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542585286 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199312070 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159534 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1134383 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13280 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7701154 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8705181 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16406335 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827826675 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516940315 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29665804 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 78 # number of nop insts executed -system.cpu.iew.exec_refs 698647521 # number of memory reference insts executed -system.cpu.iew.exec_branches 229543891 # Number of branches executed -system.cpu.iew.exec_stores 181752772 # Number of stores executed -system.cpu.iew.exec_rate 1.190194 # Inst execution rate -system.cpu.iew.wb_sent 1808752237 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805715827 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169206310 # num instructions producing a value -system.cpu.iew.wb_consumers 1689633446 # num instructions consuming a value -system.cpu.iew.wb_rate 1.175824 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691988 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258099424 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 146 # number of nop insts executed +system.cpu.iew.exec_refs 698692225 # number of memory reference insts executed +system.cpu.iew.exec_branches 229542687 # Number of branches executed +system.cpu.iew.exec_stores 181751910 # Number of stores executed +system.cpu.iew.exec_rate 1.190295 # Inst execution rate +system.cpu.iew.wb_sent 1808754463 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805719795 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169207800 # num instructions producing a value +system.cpu.iew.wb_consumers 1689618799 # num instructions consuming a value +system.cpu.iew.wb_rate 1.175899 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 258113026 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14629299 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1496131949 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.112223 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.027889 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14630522 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1496036001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.112294 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.028030 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 915820639 61.21% 61.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250646763 16.75% 77.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110056209 7.36% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55261288 3.69% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29350080 1.96% 90.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34099698 2.28% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24719772 1.65% 94.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18148053 1.21% 96.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58029447 3.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 915722932 61.21% 61.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250663462 16.76% 77.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110062832 7.36% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55282207 3.70% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29306686 1.96% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34079757 2.28% 93.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24721963 1.65% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18129916 1.21% 96.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58066246 3.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1496131949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1496036001 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -695,76 +699,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58029447 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3360233761 # The number of ROB reads -system.cpu.rob.rob_writes 3883762364 # The number of ROB writes -system.cpu.timesIdled 834 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 77324 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58066246 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3360114616 # The number of ROB reads +system.cpu.rob.rob_writes 3883791528 # The number of ROB writes +system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76214 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.994264 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.994264 # CPI: Total CPI of All Threads -system.cpu.ipc 1.005769 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.005769 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175773439 # number of integer regfile reads -system.cpu.int_regfile_writes 1261589366 # number of integer regfile writes -system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 52 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965635020 # number of cc regfile reads -system.cpu.cc_regfile_writes 551858996 # number of cc regfile writes -system.cpu.misc_regfile_reads 675848866 # number of misc regfile reads +system.cpu.cpi 0.994202 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.994202 # CPI: Total CPI of All Threads +system.cpu.ipc 1.005832 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.005832 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads +system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes +system.cpu.fp_regfile_reads 42 # number of floating regfile reads +system.cpu.fp_regfile_writes 54 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads +system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes +system.cpu.misc_regfile_reads 675853701 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17003597 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964807 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638080633 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17004109 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.525085 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 77932500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964807 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 17003710 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 408 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335734207 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335734207 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469362265 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469362265 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168718228 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168718228 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638080493 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638080493 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638080493 # number of overall hits -system.cpu.dcache.overall_hits::total 638080493 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17416613 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17416613 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3867819 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3867819 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638076218 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638076218 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638076218 # number of overall hits +system.cpu.dcache.overall_hits::total 638076218 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17418310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17418310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3867432 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3867432 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21284432 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21284432 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21284434 # number of overall misses -system.cpu.dcache.overall_misses::total 21284434 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 412110560500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 412110560500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 148910053049 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 148910053049 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 21285742 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21285742 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21285744 # number of overall misses +system.cpu.dcache.overall_misses::total 21285744 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 411945425500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 148954509432 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 561020613549 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 561020613549 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 561020613549 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 561020613549 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486778878 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486778878 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 560899934932 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 560899934932 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 560899934932 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 560899934932 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486775913 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486775913 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -773,72 +777,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659364925 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659364925 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659364927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659364927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022411 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022411 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659361960 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659361960 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659361962 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659361962 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022409 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022409 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032280 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032280 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032280 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032280 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23661.923274 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23661.923274 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38499.747028 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38499.747028 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26358.260984 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26358.260984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26358.258507 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26358.258507 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20478587 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3417945 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 942442 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67202 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.729281 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50.860763 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26350.969345 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 17003597 # number of writebacks -system.cpu.dcache.writebacks::total 17003597 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150032 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3150032 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130287 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1130287 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks +system.cpu.dcache.writebacks::total 17003710 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4280319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4280319 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4280319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4280319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266581 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14266581 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737532 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737532 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4281515 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4281515 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4281515 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4281515 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266638 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14266638 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737589 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737589 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17004113 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17004113 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17004114 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17004114 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331850986000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 331850986000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115586978404 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 115586978404 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17004227 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17004227 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17004228 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17004228 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447437964404 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 447437964404 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447438032404 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 447438032404 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 447484732765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 447484800765 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses @@ -849,393 +853,394 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23260.722804 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23260.722804 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42223.060189 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42223.060189 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26313.513937 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26313.513937 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26313.516388 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26313.516388 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 586 # number of replacements -system.cpu.icache.tags.tagsinuse 444.620453 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656959766 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1072 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 612835.602612 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 589 # number of replacements +system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 444.620453 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.868399 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.868399 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313923770 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313923770 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656959766 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656959766 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656959766 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656959766 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656959766 # number of overall hits -system.cpu.icache.overall_hits::total 656959766 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1583 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1583 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1583 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1583 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1583 # number of overall misses -system.cpu.icache.overall_misses::total 1583 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 101448987 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 101448987 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 101448987 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 101448987 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 101448987 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 101448987 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656961349 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656961349 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656961349 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656961349 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656961349 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656961349 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits +system.cpu.icache.overall_hits::total 656966815 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1620 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1620 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1620 # number of overall misses +system.cpu.icache.overall_misses::total 1620 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 98788987 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 98788987 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 98788987 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 98788987 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 98788987 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 98788987 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656968435 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656968435 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656968435 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656968435 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656968435 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656968435 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64086.536323 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64086.536323 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64086.536323 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64086.536323 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64086.536323 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64086.536323 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 16918 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 173 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 89.513228 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 34.600000 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60980.856173 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60980.856173 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17260 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 439 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 586 # number of writebacks -system.cpu.icache.writebacks::total 586 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 509 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 509 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 509 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 509 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 509 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 509 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1074 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1074 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1074 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1074 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1074 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74582990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 74582990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74582990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 74582990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74582990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 74582990 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 589 # number of writebacks +system.cpu.icache.writebacks::total 589 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 544 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 544 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 544 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 544 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73759491 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 73759491 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73759491 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 73759491 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73759491 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 73759491 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69444.124767 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69444.124767 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69444.124767 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69444.124767 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69444.124767 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69444.124767 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 11607728 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11635838 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 19050 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 5 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4655842 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 4705864 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16099.842459 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 22826032 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4721788 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.834192 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 54104143500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 13102.285184 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2.119304 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2995.437971 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.799700 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000129 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.182827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.982656 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 773 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15151 # Occupied blocks per task id +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 4706089 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4722015 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.834615 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 54111720000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2.290302 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2999.119162 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.799460 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000140 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183052 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.982651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15097 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 599 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2950 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4343 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5551 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1838 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.047180 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.924744 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 552240776 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 552240776 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 4834377 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 4834377 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 12148517 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 12148517 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1758217 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1758217 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 57 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 57 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11520794 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 11520794 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 57 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13279011 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13279068 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 57 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13279011 # number of overall hits -system.cpu.l2cache.overall_hits::total 13279068 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 979355 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 979355 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1017 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1017 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2745743 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2745743 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3725098 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3726115 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1017 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3725098 # number of overall misses -system.cpu.l2cache.overall_misses::total 3726115 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 100500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 100500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98934121000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 98934121000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 73094500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 73094500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234186702000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 234186702000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 73094500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 333120823000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 333193917500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 73094500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 333120823000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 333193917500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 4834377 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 4834377 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 12148517 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 12148517 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737572 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737572 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1074 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1074 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266537 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 14266537 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1074 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17004109 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17005183 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1074 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17004109 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17005183 # number of overall (read+write) accesses +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 636 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 191 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 453 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 12149903 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1757087 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1757087 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 56 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 56 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11522367 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 11522367 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 56 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 13279454 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13279510 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 56 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 13279454 # number of overall hits +system.cpu.l2cache.overall_hits::total 13279510 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 980546 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 980546 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1020 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1020 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2744222 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 2744222 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1020 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3724768 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3725788 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1020 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3724768 # number of overall misses +system.cpu.l2cache.overall_misses::total 3725788 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 121000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 121000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99083213500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 99083213500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72272000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 72272000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234079710000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 234079710000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 72272000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 333162923500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 333235195500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 72272000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 333162923500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 333235195500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 4833112 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 4833112 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 12149903 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 12149903 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737633 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2737633 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266589 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 14266589 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 17004222 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17005298 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 17004222 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17005298 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.357746 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.357746 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.946927 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.946927 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192460 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192460 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.946927 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.219070 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.219116 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.946927 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.219070 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.219116 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20100 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20100 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101019.672131 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101019.672131 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71872.664700 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71872.664700 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85290.830934 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85290.830934 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71872.664700 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89426.056174 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89421.265178 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71872.664700 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89426.056174 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89421.265178 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 398 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358173 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.358173 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947955 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947955 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192353 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192353 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947955 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.219050 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.219096 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947955 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.219050 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.219096 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101049.021158 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101049.021158 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70854.901961 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70854.901961 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85299.115742 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85299.115742 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89440.192383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89440.192383 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1634781 # number of writebacks -system.cpu.l2cache.writebacks::total 1634781 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3953 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3953 # number of ReadExReq MSHR hits +system.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks +system.cpu.l2cache.writebacks::total 1635896 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3915 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3915 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45302 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45302 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45253 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45253 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 49255 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 49256 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 49168 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 49169 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 49255 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 49256 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1144188 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1144188 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 975402 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 975402 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1016 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1016 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2700441 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2700441 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1016 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3675843 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3676859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1016 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3675843 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1144188 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4821047 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72422793987 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72422793987 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 70500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 70500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92707545500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92707545500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66931500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66931500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215168959000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215168959000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66931500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307876504500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 307943436000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66931500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307876504500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72422793987 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 380366229987 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 49168 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 49169 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1145204 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976631 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 976631 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1019 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1019 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2698969 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2698969 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3675600 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3676619 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3675600 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4821823 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72434619378 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 85000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 85000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92854351000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92854351000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66085000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66085000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215091513500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215091513500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66085000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307945864500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 308011949500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66085000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307945864500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 380446568878 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356302 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356302 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.945996 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189285 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189285 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216174 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216220 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216174 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356743 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356743 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947026 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189181 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189181 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216204 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.283505 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63296.236271 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14100 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14100 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95045.474071 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95045.474071 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65877.460630 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65877.460630 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79679.192769 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79679.192769 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65877.460630 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83756.706829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83751.766385 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65877.460630 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83756.706829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78897.017595 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.283548 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 34009371 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004197 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21289 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2918881 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2900097 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18784 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 14267609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6469158 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12169806 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5772538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1435459 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737572 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737572 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1074 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266537 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2732 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011834 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51014566 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176493760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176599872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 8842787 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 25847966 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.114476 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.320662 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737633 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737633 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266589 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51012175 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51014915 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 8842499 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 25847794 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.114446 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.320627 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22907787 88.63% 88.63% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2921395 11.30% 99.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 18784 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22908415 88.63% 88.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2920592 11.30% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 18787 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25847966 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34008868522 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25847794 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 13530 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1609497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25506170491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3697667 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1634781 # Transaction distribution -system.membus.trans_dist::CleanEvict 3002759 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 975542 # Transaction distribution -system.membus.trans_dist::ReadExResp 975542 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3697668 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13983964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13983964 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403711360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 403711360 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3696594 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution +system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 976790 # Transaction distribution +system.membus.trans_dist::ReadExResp 976790 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13984484 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403793920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 403793920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9310755 # Request fanout histogram +system.membus.snoop_fanout::samples 9311100 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9310755 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9311100 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9310755 # Request fanout histogram -system.membus.reqLayer0.occupancy 17653458992 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9311100 # Request fanout histogram +system.membus.reqLayer0.occupancy 17657610874 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 25411663187 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25413256779 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |