diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm')
16 files changed, 877 insertions, 566 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini index cb09befab..9ef5c346e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini @@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,9 +26,16 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -55,6 +64,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -99,12 +109,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -120,11 +135,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -132,13 +154,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -148,6 +175,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -156,8 +184,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=262144 @@ -180,9 +213,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -196,9 +234,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -591,13 +634,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -607,6 +655,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -615,8 +664,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=131072 @@ -626,6 +680,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -673,9 +728,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -689,9 +749,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -701,13 +766,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -717,6 +787,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -725,19 +796,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -745,6 +828,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -759,7 +849,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin kvmInSE=false @@ -791,9 +881,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -837,6 +933,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -848,7 +945,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=0:134217727 ranks_per_channel=2 read_buffer_size=32 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr index be90b0340..caeab8324 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout index 1664fb28c..b6bf1e68a 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 23:29:19 -gem5 started Sep 15 2015 02:59:16 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:58:37 +gem5 executing on e108600-lin, pid 24092 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -27,4 +27,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1116876142500 because target called exit() +Exiting @ tick 1128033563500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index d91451297..a63511156 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.116866 # Number of seconds simulated -sim_ticks 1116865668500 # Number of ticks simulated -final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.128034 # Number of seconds simulated +sim_ticks 1128033563500 # Number of ticks simulated +final_tick 1128033563500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 380135 # Simulator instruction rate (inst/s) -host_op_rate 409538 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 274873670 # Simulator tick rate (ticks/s) -host_mem_usage 314372 # Number of bytes of host memory used -host_seconds 4063.20 # Real time elapsed on the host +host_inst_rate 296898 # Simulator instruction rate (inst/s) +host_op_rate 319862 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216832014 # Simulator tick rate (ticks/s) +host_mem_usage 266856 # Number of bytes of host memory used +host_seconds 5202.34 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory -system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130888128 # Number of bytes read from this memory +system.physmem.bytes_read::total 130938240 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory -system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67194432 # Number of bytes written to this memory +system.physmem.bytes_written::total 67194432 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2045808 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 44868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117231388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 44868 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 44868 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 44868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117231388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2046591 # Number of read requests accepted -system.physmem.writeReqs 1050123 # Number of write requests accepted -system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 130898176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83648 # Total number of bytes read from write queue -system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1307 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 2045127 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2045910 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1049913 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1049913 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 44424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 116032122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116076546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 44424 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 44424 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 59567759 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 59567759 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 59567759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 44424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 116032122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 175644306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2045910 # Number of read requests accepted +system.physmem.writeReqs 1049913 # Number of write requests accepted +system.physmem.readBursts 2045910 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1049913 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 130851840 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 86400 # Total number of bytes read from write queue +system.physmem.bytesWritten 67192960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130938240 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67194432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1350 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127279 # Per bank write bursts -system.physmem.perBankRdBursts::1 124661 # Per bank write bursts -system.physmem.perBankRdBursts::2 121601 # Per bank write bursts -system.physmem.perBankRdBursts::3 123656 # Per bank write bursts -system.physmem.perBankRdBursts::4 122620 # Per bank write bursts -system.physmem.perBankRdBursts::5 122679 # Per bank write bursts -system.physmem.perBankRdBursts::6 123247 # Per bank write bursts -system.physmem.perBankRdBursts::7 123770 # Per bank write bursts -system.physmem.perBankRdBursts::8 131396 # Per bank write bursts -system.physmem.perBankRdBursts::9 133511 # Per bank write bursts -system.physmem.perBankRdBursts::10 132081 # Per bank write bursts -system.physmem.perBankRdBursts::11 133308 # Per bank write bursts -system.physmem.perBankRdBursts::12 133249 # Per bank write bursts -system.physmem.perBankRdBursts::13 133362 # Per bank write bursts -system.physmem.perBankRdBursts::14 129309 # Per bank write bursts -system.physmem.perBankRdBursts::15 129555 # Per bank write bursts -system.physmem.perBankWrBursts::0 66136 # Per bank write bursts -system.physmem.perBankWrBursts::1 64410 # Per bank write bursts -system.physmem.perBankWrBursts::2 62576 # Per bank write bursts -system.physmem.perBankWrBursts::3 63006 # Per bank write bursts -system.physmem.perBankWrBursts::4 63000 # Per bank write bursts -system.physmem.perBankWrBursts::5 63100 # Per bank write bursts -system.physmem.perBankWrBursts::6 64443 # Per bank write bursts -system.physmem.perBankWrBursts::7 65436 # Per bank write bursts -system.physmem.perBankWrBursts::8 67310 # Per bank write bursts -system.physmem.perBankWrBursts::9 67797 # Per bank write bursts -system.physmem.perBankWrBursts::10 67549 # Per bank write bursts -system.physmem.perBankWrBursts::11 67882 # Per bank write bursts -system.physmem.perBankWrBursts::12 67326 # Per bank write bursts -system.physmem.perBankWrBursts::13 67793 # Per bank write bursts -system.physmem.perBankWrBursts::14 66482 # Per bank write bursts -system.physmem.perBankWrBursts::15 65854 # Per bank write bursts +system.physmem.perBankRdBursts::0 127234 # Per bank write bursts +system.physmem.perBankRdBursts::1 124635 # Per bank write bursts +system.physmem.perBankRdBursts::2 121565 # Per bank write bursts +system.physmem.perBankRdBursts::3 123578 # Per bank write bursts +system.physmem.perBankRdBursts::4 122544 # Per bank write bursts +system.physmem.perBankRdBursts::5 122632 # Per bank write bursts +system.physmem.perBankRdBursts::6 123221 # Per bank write bursts +system.physmem.perBankRdBursts::7 123735 # Per bank write bursts +system.physmem.perBankRdBursts::8 131340 # Per bank write bursts +system.physmem.perBankRdBursts::9 133478 # Per bank write bursts +system.physmem.perBankRdBursts::10 132036 # Per bank write bursts +system.physmem.perBankRdBursts::11 133242 # Per bank write bursts +system.physmem.perBankRdBursts::12 133211 # Per bank write bursts +system.physmem.perBankRdBursts::13 133326 # Per bank write bursts +system.physmem.perBankRdBursts::14 129274 # Per bank write bursts +system.physmem.perBankRdBursts::15 129509 # Per bank write bursts +system.physmem.perBankWrBursts::0 66120 # Per bank write bursts +system.physmem.perBankWrBursts::1 64398 # Per bank write bursts +system.physmem.perBankWrBursts::2 62563 # Per bank write bursts +system.physmem.perBankWrBursts::3 62980 # Per bank write bursts +system.physmem.perBankWrBursts::4 62981 # Per bank write bursts +system.physmem.perBankWrBursts::5 63086 # Per bank write bursts +system.physmem.perBankWrBursts::6 64437 # Per bank write bursts +system.physmem.perBankWrBursts::7 65431 # Per bank write bursts +system.physmem.perBankWrBursts::8 67296 # Per bank write bursts +system.physmem.perBankWrBursts::9 67792 # Per bank write bursts +system.physmem.perBankWrBursts::10 67535 # Per bank write bursts +system.physmem.perBankWrBursts::11 67858 # Per bank write bursts +system.physmem.perBankWrBursts::12 67312 # Per bank write bursts +system.physmem.perBankWrBursts::13 67784 # Per bank write bursts +system.physmem.perBankWrBursts::14 66474 # Per bank write bursts +system.physmem.perBankWrBursts::15 65843 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1116865574000 # Total gap between requests +system.physmem.totGap 1128033469500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2046591 # Read request sizes (log2) +system.physmem.readPktSize::6 2045910 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1050123 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1916619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1049913 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1917702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,30 +145,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -194,113 +194,113 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1910138 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.711175 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.836423 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.540224 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485349 77.76% 77.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305158 15.98% 93.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52532 2.75% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21047 1.10% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13374 0.70% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7565 0.40% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5491 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5162 0.27% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14460 0.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1910138 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61136 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.411672 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 159.590236 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61090 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 21 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1910047 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.685692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.827100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.490486 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1485463 77.77% 77.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305174 15.98% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52509 2.75% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20929 1.10% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13256 0.69% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7619 0.40% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5519 0.29% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5102 0.27% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14476 0.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1910047 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61113 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.412400 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 159.518866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61065 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 24 0.04% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61136 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61136 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.176459 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.141461 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.097536 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27008 44.18% 44.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1128 1.85% 46.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28688 46.92% 92.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3895 6.37% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 363 0.59% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 46 0.08% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61136 # Writes before turning the bus around for reads -system.physmem.totQLat 38124700750 # Total ticks spent queuing -system.physmem.totMemAccLat 76473775750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10226420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18640.30 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 61113 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.179487 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.144319 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.100540 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 26981 44.15% 44.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1028 1.68% 45.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28814 47.15% 92.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3825 6.26% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 400 0.65% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 47 0.08% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 11 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61113 # Writes before turning the bus around for reads +system.physmem.totQLat 38097515250 # Total ticks spent queuing +system.physmem.totMemAccLat 76433015250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10222800000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18633.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37390.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37383.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 59.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.08 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 59.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.39 # Data bus utilization in percentage -system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.37 # Data bus utilization in percentage +system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing -system.physmem.readRowHits 773341 # Number of row buffer hits during reads -system.physmem.writeRowHits 411895 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes -system.physmem.avgGap 360661.52 # Average gap between requests -system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7039078200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3840766875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7717881600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 420697412235 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 301083150000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 816644588670 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.196952 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 498171344000 # Time in different power states -system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states +system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing +system.physmem.readRowHits 772369 # Number of row buffer hits during reads +system.physmem.writeRowHits 412032 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.24 # Row buffer hit rate for writes +system.physmem.avgGap 364372.73 # Average gap between requests +system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7040703600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3841653750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7715315400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3317734080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 73677630000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 423036881190 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 305734953750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 824364871770 # Total energy per rank (pJ) +system.physmem_0.averagePower 730.798394 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 505893058250 # Time in different power states +system.physmem_0.memoryStateTime::REF 37667500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 581396539000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 584472684250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7401549960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4038544125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8234959200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 429293377035 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 293542830000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 818945301360 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.256935 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 485580062750 # Time in different power states -system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states +system.physmem_1.actEnergy 7399251720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4037290125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8232221400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3485553120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 73677630000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 432494110575 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 297439138500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 826765195440 # Total energy per rank (pJ) +system.physmem_1.averagePower 732.926278 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 492041493250 # Time in different power states +system.physmem_1.memoryStateTime::REF 37667500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 598324400250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 239639355 # Number of BP lookups -system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 130646338 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122079091 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240019627 # Number of BP lookups +system.cpu.branchPred.condPredicted 186610234 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 131647639 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122324320 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.442413 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15657057 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.917975 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15657430 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 537 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 230 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 307 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 534 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 302 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,7 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,16 +421,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1116865668500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2233731337 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2256067127 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41470388 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41363716 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446190 # CPI: cycles per instruction -system.cpu.ipc 0.691472 # IPC: instructions per cycle +system.cpu.cpi 1.460651 # CPI: cycles per instruction +system.cpu.ipc 0.684626 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -466,61 +466,61 @@ system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked -system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9221041 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.665004 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616095 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy +system.cpu.tickCycles 1844612574 # Number of cycles that the object actually ticked +system.cpu.idleCycles 411454553 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9220101 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.702912 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624495427 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9224197 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.701874 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9818932500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.702912 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997486 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997486 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 241 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1240 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 62 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331073 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277391791 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277391791 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454164210 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454164210 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331094 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331094 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624218805 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624218805 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624218806 # number of overall hits -system.cpu.dcache.overall_hits::total 624218806 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7334498 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7334498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254974 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254974 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624495304 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624495304 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624495305 # number of overall hits +system.cpu.dcache.overall_hits::total 624495305 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7333415 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7333415 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254953 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254953 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9589472 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9589472 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9589474 # number of overall misses -system.cpu.dcache.overall_misses::total 9589474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 190926660000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 190926660000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109083916000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109083916000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 300010576000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 300010576000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 300010576000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 300010576000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461222230 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461222230 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9588368 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9588368 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9588370 # number of overall misses +system.cpu.dcache.overall_misses::total 9588370 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 190988166000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 190988166000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108977258000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108977258000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 299965424000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 299965424000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 299965424000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 299965424000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461497625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461497625 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -529,404 +529,406 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633808277 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633808277 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633808280 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633808280 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 634083672 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634083672 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634083675 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634083675 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.319390 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.319390 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48374.799887 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48374.799887 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.411334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31285.411334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.404809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31285.404809 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.015122 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015122 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015122 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015122 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26043.550788 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26043.550788 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48327.950960 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48327.950960 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31284.304482 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31284.304482 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.297957 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31284.297957 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3684567 # number of writebacks -system.cpu.dcache.writebacks::total 3684567 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364121 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364121 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364336 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364336 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364336 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364336 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334283 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334283 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890853 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890853 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3684499 # number of writebacks +system.cpu.dcache.writebacks::total 3684499 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364123 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364123 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364172 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364172 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364172 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364172 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333366 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333366 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890830 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890830 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9225136 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9225136 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9225137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9225137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183586477500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 183586477500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84779361000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84779361000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9224196 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9224196 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9224197 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9224197 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183652478000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 183652478000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84692070000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84692070000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268365838500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 268365838500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268365912500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 268365912500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268344548000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 268344548000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268344622000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 268344622000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.278109 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.278109 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25043.408170 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.408170 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44790.948948 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44790.948948 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.375335 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.375335 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.380204 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.380204 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 30 # number of replacements +system.cpu.icache.tags.tagsinuse 660.287317 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466254411 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 569297.205128 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.385482 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322454 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322454 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 660.287317 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322406 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322406 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses -system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 465281510 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 465281510 # number of overall hits -system.cpu.icache.overall_hits::total 465281510 # number of overall hits +system.cpu.icache.tags.age_task_id_blocks_1024::4 752 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 932511279 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932511279 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466254411 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466254411 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466254411 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466254411 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466254411 # number of overall hits +system.cpu.icache.overall_hits::total 466254411 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 819 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 819 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 819 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 819 # number of overall misses system.cpu.icache.overall_misses::total 819 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62402500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62402500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62402500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62402500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62402500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62402500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 465282329 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 465282329 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 465282329 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 465282329 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 465282329 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 465282329 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61690000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61690000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61690000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61690000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61690000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61690000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 466255230 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466255230 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466255230 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466255230 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466255230 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466255230 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76193.528694 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76193.528694 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76193.528694 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76193.528694 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75323.565324 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75323.565324 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75323.565324 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75323.565324 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75323.565324 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75323.565324 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 29 # number of writebacks -system.cpu.icache.writebacks::total 29 # number of writebacks +system.cpu.icache.writebacks::writebacks 30 # number of writebacks +system.cpu.icache.writebacks::total 30 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61583500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 61583500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61583500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 61583500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61583500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 61583500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60871000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 60871000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60871000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 60871000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60871000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 60871000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 2013919 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16398.892088 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.452664 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000807 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.500454 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.953926 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74323.565324 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74323.565324 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74323.565324 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74323.565324 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74323.565324 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74323.565324 # average overall mshr miss latency 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000803 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.500007 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.954174 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1250 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12853 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 29 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1089694 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1089694 # number of ReadExReq hits +system.cpu.l2cache.tags.tag_accesses 151482269 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 151482269 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 3684499 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3684499 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 30 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 30 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1089818 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1089818 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits 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ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77875.455049 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65647.509579 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65647.509579 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77380.803222 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77380.803222 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65647.509579 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77574.542803 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77569.978152 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65647.509579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77574.542803 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77569.978152 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18445147 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220143 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1285 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6500270 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7334186 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4734412 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 30 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6498928 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890830 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1667 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671315 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27672982 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826221056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2013919 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 11239875 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333367 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1668 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668495 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27670163 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826156544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 826210880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2013239 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 67194432 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11238255 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.016088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.016087 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11236983 99.97% 99.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2886 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11235364 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2885 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11239875 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12908109000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 11238255 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12907102500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13836298494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1245432 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution -system.membus.trans_dist::CleanEvict 962724 # Transaction distribution -system.membus.trans_dist::ReadExReq 801159 # Transaction distribution -system.membus.trans_dist::ReadExResp 801159 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1245432 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106029 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6106029 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1244898 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1049913 # Transaction distribution +system.membus.trans_dist::CleanEvict 962255 # Transaction distribution +system.membus.trans_dist::ReadExReq 801012 # Transaction distribution +system.membus.trans_dist::ReadExResp 801012 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1244898 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6103988 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6103988 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198132672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198132672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4059438 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 4058078 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4059438 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4058078 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4059438 # Request fanout histogram -system.membus.reqLayer0.occupancy 8663216000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4058078 # Request fanout histogram +system.membus.reqLayer0.occupancy 8755432500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11191487250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11187827500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 540dec5ab..48a3a5266 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -72,6 +77,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -110,6 +116,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -166,12 +176,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -190,8 +205,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -214,9 +234,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -230,9 +255,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -508,12 +538,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -532,8 +567,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -591,9 +631,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -607,9 +652,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -620,12 +670,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu.l2cache.prefetcher response_latency=12 @@ -643,6 +698,7 @@ mem_side=system.membus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -653,6 +709,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -669,8 +729,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -678,10 +743,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -712,7 +782,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin kvmInSE=false @@ -744,10 +814,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -791,6 +866,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -802,7 +878,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=0:134217727 ranks_per_channel=2 read_buffer_size=32 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr index be90b0340..caeab8324 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 77417a942..3ee0ee7fa 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 16 2016 23:07:21 -gem5 started Mar 16 2016 23:41:21 -gem5 executing on dinar2c11, pid 25849 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 15:06:10 +gem5 executing on e108600-lin, pid 24215 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index bd5e79823..3ae5dc097 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.767804 # Nu sim_ticks 767803843500 # Number of ticks simulated final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 232978 # Simulator instruction rate (inst/s) -host_op_rate 250999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115813638 # Simulator tick rate (ticks/s) -host_mem_usage 356264 # Number of bytes of host memory used -host_seconds 6629.65 # Real time elapsed on the host +host_inst_rate 219812 # Simulator instruction rate (inst/s) +host_op_rate 236814 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 109268932 # Simulator tick rate (ticks/s) +host_mem_usage 308968 # Number of bytes of host memory used +host_seconds 7026.74 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1203,6 +1203,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 8842499 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104697920 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 25847794 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.114446 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.320627 # Request fanout histogram @@ -1235,6 +1236,7 @@ system.membus.pkt_count::total 13984484 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403793920 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 403793920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 9311100 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 1b535494d..0bd2c9396 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -73,6 +79,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -106,9 +116,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -122,9 +137,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.membus.slave[4] @@ -182,9 +202,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -198,9 +223,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.membus.slave[3] @@ -218,7 +248,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin kvmInSE=false @@ -250,10 +280,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -268,11 +303,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:134217727 port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr index 1a4f96712..aadc3d011 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr @@ -1 +1,2 @@ warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index 6fb821b07..c1b3d9c87 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,13 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simout +Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:13:20 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:22 +gem5 executing on e108600-lin, pid 23077 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-atomic + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 9d26db066..a861bb889 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490500 # Number of ticks simulated final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2178318 # Simulator instruction rate (inst/s) -host_op_rate 2346807 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1173405208 # Simulator tick rate (ticks/s) -host_mem_usage 302320 # Number of bytes of host memory used -host_seconds 709.06 # Real time elapsed on the host +host_inst_rate 1008264 # Simulator instruction rate (inst/s) +host_op_rate 1086251 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 543126570 # Simulator tick rate (ticks/s) +host_mem_usage 256604 # Number of bytes of host memory used +host_seconds 1531.90 # Real time elapsed on the host sim_insts 1544563042 # Number of instructions simulated sim_ops 1664032434 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -237,6 +237,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram system.membus.snoop_fanout::mean 0.711106 # Request fanout histogram system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index d42bc7142..65c2bbf99 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -72,6 +78,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -90,12 +100,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -114,8 +129,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=262144 @@ -138,9 +158,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -154,9 +179,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -167,12 +197,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -191,8 +226,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=131072 @@ -250,9 +290,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -266,9 +311,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -279,12 +329,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -303,8 +358,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=2097152 @@ -312,10 +372,15 @@ size=2097152 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -346,7 +411,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin kvmInSE=false @@ -378,10 +443,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -396,11 +466,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:134217727 port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr index 1a4f96712..aadc3d011 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr @@ -1 +1,2 @@ warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 8064c269e..4382bd2ba 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -3,10 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:15:41 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:49:25 +gem5 executing on e108600-lin, pid 23292 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 59601069e..e3d403cda 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.377030 # Nu sim_ticks 2377029670500 # Number of ticks simulated final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1373046 # Simulator instruction rate (inst/s) -host_op_rate 1479650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2121040557 # Simulator tick rate (ticks/s) -host_mem_usage 312336 # Number of bytes of host memory used -host_seconds 1120.69 # Real time elapsed on the host +host_inst_rate 744525 # Simulator instruction rate (inst/s) +host_op_rate 802329 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1150119113 # Simulator tick rate (ticks/s) +host_mem_usage 266344 # Number of bytes of host memory used +host_seconds 2066.77 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -623,6 +623,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1919027 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 65352128 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram @@ -652,6 +653,7 @@ system.membus.pkt_count::total 5821611 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 3869897 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram |