diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt | 112 |
1 files changed, 56 insertions, 56 deletions
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 50b0e856f..b95834217 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.901049 # Number of seconds simulated -sim_ticks 5901048931000 # Number of ticks simulated -final_tick 5901048931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5901048883000 # Number of ticks simulated +final_tick 5901048883000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 821481 # Simulator instruction rate (inst/s) -host_op_rate 1279942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1611526350 # Simulator tick rate (ticks/s) -host_mem_usage 228472 # Number of bytes of host memory used -host_seconds 3661.78 # Real time elapsed on the host -sim_insts 3008081057 # Number of instructions simulated -sim_ops 4686862651 # Number of ops (including micro ops) simulated +host_inst_rate 766833 # Simulator instruction rate (inst/s) +host_op_rate 1194795 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1504320663 # Simulator tick rate (ticks/s) +host_mem_usage 233368 # Number of bytes of host memory used +host_seconds 3922.73 # Real time elapsed on the host +sim_insts 3008081022 # Number of instructions simulated +sim_ops 4686862594 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory @@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst 7321 # To system.physmem.bw_total::cpu.data 23562520 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 34990498 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11802097862 # number of cpu cycles simulated +system.cpu.numCycles 11802097766 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 3008081057 # Number of instructions committed -system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses +system.cpu.committedInsts 3008081022 # Number of instructions committed +system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls -system.cpu.num_int_insts 4686862580 # number of integer instructions +system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls +system.cpu.num_int_insts 4686862523 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 14165752766 # number of times the integer registers were read -system.cpu.num_int_register_writes 6716691823 # number of times the integer registers were written +system.cpu.num_int_register_reads 14165752588 # number of times the integer registers were read +system.cpu.num_int_register_writes 6716691731 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1677713086 # number of memory refs -system.cpu.num_load_insts 1239184749 # Number of load instructions +system.cpu.num_mem_refs 1677713082 # number of memory refs +system.cpu.num_load_insts 1239184745 # Number of load instructions system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11802097862 # Number of busy cycles +system.cpu.num_busy_cycles 11802097766 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 555.745883 # Cycle average of tags in use -system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 555.745887 # Cycle average of tags in use +system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 555.745883 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 555.745887 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.271360 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.271360 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4013232252 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4013232252 # number of overall hits -system.cpu.icache.overall_hits::total 4013232252 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits +system.cpu.icache.overall_hits::total 4013232208 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 37868000 system.cpu.icache.demand_miss_latency::total 37868000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 37868000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 37868000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4013232927 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4013232927 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4013232927 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4013232927 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses @@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741 system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.618075 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4084.618108 # Cycle average of tags in use +system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58864243000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.618075 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 58864195000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4084.618108 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997221 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997221 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1231961899 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1668600409 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1668600409 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1668600409 # number of overall hits -system.cpu.dcache.overall_hits::total 1668600409 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1668600405 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1668600405 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1668600405 # number of overall hits +system.cpu.dcache.overall_hits::total 1668600405 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses @@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 218826366000 system.cpu.dcache.demand_miss_latency::total 218826366000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 218826366000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 218826366000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1677713086 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1677713086 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 1677713082 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1677713082 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1677713082 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1677713082 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses @@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892 system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2158210 # number of replacements -system.cpu.l2cache.tagsinuse 30851.471232 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30851.471482 # Cycle average of tags in use system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1317386171000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14661.795010 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 1317386123000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14661.795129 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 21.581563 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16168.094659 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16168.094790 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.447442 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.000659 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.493411 # Average percentage of cache occupancy |