diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
20 files changed, 3093 insertions, 3011 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 5a7d7b1a5..5da6802d2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -193,6 +194,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -205,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -316,38 +319,52 @@ pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 -[system.cpu.fuPool.FUList2.opList] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=2 pipelined=true +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList3] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 -[system.cpu.fuPool.FUList3.opList] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=2 pipelined=true +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 [system.cpu.fuPool.FUList4.opList00] type=OpDesc @@ -479,7 +496,7 @@ pipelined=true type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc -opLat=1 +opLat=5 pipelined=true [system.cpu.fuPool.FUList4.opList19] @@ -531,6 +548,20 @@ opClass=FloatMult opLat=4 pipelined=true +[system.cpu.fuPool.FUList4.opList26] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList4.opList27] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + [system.cpu.icache] type=Cache children=tags @@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -555,6 +586,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -567,15 +599,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu.interrupts] type=ArmInterrupts @@ -594,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -606,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -687,6 +716,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -729,15 +759,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu.toL2Bus] type=CoherentXBar @@ -773,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=bzip2 input.source 1 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing drivers= @@ -782,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr index caeab8324..5467490ac 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr @@ -1,4 +1,8 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index fbc8b4e01..19305f061 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -3,20 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:48:52 -gem5 executing on e108600-lin, pid 17438 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:14 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54235 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 787742202500 because target called exit() +Exiting @ tick 787835965500 because exiting with last active thread context diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 5ac1aa00b..6256fdd50 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,1282 +1,1282 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.787836 # Number of seconds simulated -sim_ticks 787835965500 # Number of ticks simulated -final_tick 787835965500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263266 # Simulator instruction rate (inst/s) -host_op_rate 283629 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 134283963 # Simulator tick rate (ticks/s) -host_mem_usage 329624 # Number of bytes of host memory used -host_seconds 5866.94 # Real time elapsed on the host -sim_insts 1544563024 # Number of instructions simulated -sim_ops 1664032416 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 236015808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63804544 # Number of bytes read from this memory -system.physmem.bytes_read::total 299885696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104593152 # Number of bytes written to this memory -system.physmem.bytes_written::total 104593152 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1021 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3687747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 996946 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4685714 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1634268 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1634268 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 82941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 299574808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 80987092 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380644841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 82941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 82941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 132760062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 132760062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 132760062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 82941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 299574808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 80987092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 513404904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4685714 # Number of read requests accepted -system.physmem.writeReqs 1634268 # Number of write requests accepted -system.physmem.readBursts 4685714 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1634268 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 299374336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 511360 # Total number of bytes read from write queue -system.physmem.bytesWritten 104589440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299885696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104593152 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7990 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 28 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301500 # Per bank write bursts -system.physmem.perBankRdBursts::1 301960 # Per bank write bursts -system.physmem.perBankRdBursts::2 285447 # Per bank write bursts -system.physmem.perBankRdBursts::3 288137 # Per bank write bursts -system.physmem.perBankRdBursts::4 288946 # Per bank write bursts -system.physmem.perBankRdBursts::5 285921 # Per bank write bursts -system.physmem.perBankRdBursts::6 281288 # Per bank write bursts -system.physmem.perBankRdBursts::7 278400 # Per bank write bursts -system.physmem.perBankRdBursts::8 294011 # Per bank write bursts -system.physmem.perBankRdBursts::9 300115 # Per bank write bursts -system.physmem.perBankRdBursts::10 292046 # Per bank write bursts -system.physmem.perBankRdBursts::11 297684 # Per bank write bursts -system.physmem.perBankRdBursts::12 299531 # Per bank write bursts -system.physmem.perBankRdBursts::13 298464 # Per bank write bursts -system.physmem.perBankRdBursts::14 294115 # Per bank write bursts -system.physmem.perBankRdBursts::15 290159 # Per bank write bursts -system.physmem.perBankWrBursts::0 103775 # Per bank write bursts -system.physmem.perBankWrBursts::1 101738 # Per bank write bursts -system.physmem.perBankWrBursts::2 99347 # Per bank write bursts -system.physmem.perBankWrBursts::3 99748 # Per bank write bursts -system.physmem.perBankWrBursts::4 99113 # Per bank write bursts -system.physmem.perBankWrBursts::5 98946 # Per bank write bursts -system.physmem.perBankWrBursts::6 102275 # Per bank write bursts -system.physmem.perBankWrBursts::7 103989 # Per bank write bursts -system.physmem.perBankWrBursts::8 105110 # Per bank write bursts -system.physmem.perBankWrBursts::9 104316 # Per bank write bursts -system.physmem.perBankWrBursts::10 101973 # Per bank write bursts -system.physmem.perBankWrBursts::11 102390 # Per bank write bursts -system.physmem.perBankWrBursts::12 102662 # Per bank write bursts -system.physmem.perBankWrBursts::13 102242 # Per bank write bursts -system.physmem.perBankWrBursts::14 104082 # Per bank write bursts -system.physmem.perBankWrBursts::15 102504 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 787835924500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4685714 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1634268 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2727826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1050681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 326941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 233426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 158423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 90275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 39813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 72860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 104977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 109635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 109963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 109142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4259361 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.841028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.814946 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.698820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3400000 79.82% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 662329 15.55% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94740 2.22% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35136 0.82% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22172 0.52% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12513 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7488 0.18% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5149 0.12% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19834 0.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4259361 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98005 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.729004 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.044358 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95588 97.53% 97.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1180 1.20% 98.74% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 706 0.72% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 397 0.41% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 101 0.10% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 3 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98005 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.674761 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.634865 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.202481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 70360 71.79% 71.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1982 2.02% 73.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 17660 18.02% 91.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5209 5.32% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1729 1.76% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 596 0.61% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 225 0.23% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 114 0.12% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 71 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 31 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 17 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98005 # Writes before turning the bus around for reads -system.physmem.totQLat 162836208305 # Total ticks spent queuing -system.physmem.totMemAccLat 250543533305 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23388620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34810.99 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53560.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 132.76 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 380.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.01 # Data bus utilization in percentage -system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing -system.physmem.readRowHits 1712017 # Number of row buffer hits during reads -system.physmem.writeRowHits 340548 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 20.84 # Row buffer hit rate for writes -system.physmem.avgGap 124657.94 # Average gap between requests -system.physmem.pageHitRate 32.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15118935720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8035889730 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16504816860 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4222619820 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 59457815040.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64415436660 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1624122240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 222796740750 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 36224267040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 16152645360 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 444563646270 # Total energy per rank (pJ) -system.physmem_0.averagePower 564.284526 # Core power per rank (mW) -system.physmem_0.totalIdleTime 642315388170 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1436139102 # Time in different power states -system.physmem_0.memoryStateTime::REF 25173062000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 59398115500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 94331998561 # Time in different power states -system.physmem_0.memoryStateTime::ACT 118911366978 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 488585283359 # Time in different power states -system.physmem_1.actEnergy 15292958940 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8128385265 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 16894132500 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4307956380 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 58918161120.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64834688190 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1616111040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 219342669570 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 35641510560 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18222503400 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 443208649005 # Total energy per rank (pJ) -system.physmem_1.averagePower 562.564626 # Core power per rank (mW) -system.physmem_1.totalIdleTime 641423107931 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1455389769 # Time in different power states -system.physmem_1.memoryStateTime::REF 24945910000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67593570250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 92814429154 # Time in different power states -system.physmem_1.memoryStateTime::ACT 120009883050 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 481016783277 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286288991 # Number of BP lookups -system.cpu.branchPred.condPredicted 223379889 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14638803 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157014468 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150316303 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.734046 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16636731 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3547 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2042 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1505 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1575671932 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13942337 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067450540 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286288991 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166955076 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1546978368 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29302455 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1029 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656906223 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 925 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1575573272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.405744 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.233501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 493163312 31.30% 31.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465492881 29.54% 60.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101391668 6.44% 67.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515525411 32.72% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1575573272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.181693 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.312107 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74679257 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 578142352 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849952798 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58148325 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14650540 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 135611620 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 746 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037153887 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52516232 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14650540 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139761664 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 493000122 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16309 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837842196 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 90302441 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976324662 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26749907 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45308958 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126668 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1624936 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 29276583 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985726338 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127758695 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432766069 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 161 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310827393 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 177 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 174 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111376144 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542477238 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199268014 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26870545 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28963209 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947887828 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 229 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857408251 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13517769 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283855641 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647022412 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 59 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1575573272 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.178878 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151815 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 622703787 39.52% 39.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326030740 20.69% 60.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378156304 24.00% 84.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219671219 13.94% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29004864 1.84% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6358 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1575573272 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166096777 40.98% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2401 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191354081 47.22% 88.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47812478 11.80% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 28 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138249696 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 803001 0.04% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 34 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532063614 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186291823 10.03% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 37 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857408251 # Type of FU issued -system.cpu.iq.rate 1.178804 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405265784 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218189 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5709173052 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231756417 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805664221 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 288 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 75 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262673874 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17815816 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84170904 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66799 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13274 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24420969 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4535474 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4852528 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14650540 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25426885 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1470128 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947888203 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542477238 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199268014 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 167 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159099 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1309527 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13274 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7696809 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8718333 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16415142 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827780120 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516898840 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29628131 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 146 # number of nop insts executed -system.cpu.iew.exec_refs 698650840 # number of memory reference insts executed -system.cpu.iew.exec_branches 229565077 # Number of branches executed -system.cpu.iew.exec_stores 181752000 # Number of stores executed -system.cpu.iew.exec_rate 1.160000 # Inst execution rate -system.cpu.iew.wb_sent 1808693799 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805664296 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169145221 # num instructions producing a value -system.cpu.iew.wb_consumers 1689395973 # num instructions consuming a value -system.cpu.iew.wb_rate 1.145965 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692049 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 257953466 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14638116 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1536081048 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.083297 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.009309 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 955788021 62.22% 62.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250630730 16.32% 78.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110093475 7.17% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55285008 3.60% 89.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29278263 1.91% 91.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34064309 2.22% 93.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24750177 1.61% 95.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18104449 1.18% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58086616 3.78% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1536081048 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563042 # Number of instructions committed -system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 633153379 # Number of memory references committed -system.cpu.commit.loads 458306334 # Number of loads committed -system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462427 # Number of branches committed -system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions. -system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 174847021 10.51% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58086616 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3399979733 # The number of ROB reads -system.cpu.rob.rob_writes 3883469027 # The number of ROB writes -system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 98660 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563024 # Number of Instructions Simulated -system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.020141 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.020141 # CPI: Total CPI of All Threads -system.cpu.ipc 0.980257 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.980257 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175723378 # number of integer regfile reads -system.cpu.int_regfile_writes 1261531313 # number of integer regfile writes -system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.fp_regfile_writes 57 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965468307 # number of cc regfile reads -system.cpu.cc_regfile_writes 551796531 # number of cc regfile writes -system.cpu.misc_regfile_reads 675796862 # number of misc regfile reads -system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17001793 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.963908 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638014747 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17002305 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 81846500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.963908 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335598455 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335598455 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469297691 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469297691 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168716899 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168716899 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638014590 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638014590 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638014590 # number of overall hits -system.cpu.dcache.overall_hits::total 638014590 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17414213 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17414213 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3869148 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3869148 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21283361 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21283361 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21283363 # number of overall misses -system.cpu.dcache.overall_misses::total 21283363 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 440649629000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 440649629000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157410000348 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157410000348 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 389500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 389500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 598059629348 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 598059629348 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 598059629348 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 598059629348 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486711904 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486711904 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659297951 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659297951 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659297953 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659297953 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022419 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022419 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25304.022008 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25304.022008 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40683.375345 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40683.375345 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 97375 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 97375 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28099.867749 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28099.867749 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28099.865108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28099.865108 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21246265 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3823077 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 940794 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67416 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.583334 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56.708749 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17001793 # number of writebacks -system.cpu.dcache.writebacks::total 17001793 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3149457 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3149457 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1131591 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1131591 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4281048 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4281048 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4281048 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4281048 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14264756 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14264756 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737557 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737557 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17002313 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17002313 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17002314 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17002314 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354315671500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 354315671500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121139018143 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 121139018143 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475454689643 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 475454689643 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475454764643 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 475454764643 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24838.537126 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24838.537126 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44250.774739 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44250.774739 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27964.118155 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27964.118155 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27964.120922 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27964.120922 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 591 # number of replacements -system.cpu.icache.tags.tagsinuse 443.744305 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656904625 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 611074.069767 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 443.744305 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.866688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.866688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 438 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313813517 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313813517 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 656904625 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656904625 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656904625 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656904625 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656904625 # number of overall hits -system.cpu.icache.overall_hits::total 656904625 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1596 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1596 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1596 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1596 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1596 # number of overall misses -system.cpu.icache.overall_misses::total 1596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 121940986 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 121940986 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 121940986 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 121940986 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 121940986 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 121940986 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656906221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656906221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656906221 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656906221 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656906221 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656906221 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76404.126566 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76404.126566 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76404.126566 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76404.126566 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76404.126566 # average overall miss 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4017 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7150 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2693 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1496 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008240 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962585 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 561731761 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 561731761 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 4837264 # 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of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256725449000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 256725449000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 88486500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 361229876500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 361318363000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 88486500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 361229876500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 361318363000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 4837264 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 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# miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.949814 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.949814 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193134 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193134 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.949814 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.219733 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.219779 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.949814 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.219733 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.219779 # miss rate for overall accesses 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-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237433882500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 82266500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335691273000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 335773539500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 82266500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335691273000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84363300436 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 420136839936 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356889 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356889 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.948885 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189938 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189938 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216865 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.287383 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70358.802876 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100568.350629 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100568.350629 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80574.436827 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80574.436827 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.283974 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.283974 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91058.589213 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85979.286956 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 34005774 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17002402 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21251 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 202098 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 202097 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14265775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6471532 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12165120 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3013301 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1495847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737605 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737605 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14264700 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2742 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51006435 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51009177 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176263168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176369792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 6143430 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104594048 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 23146806 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009650 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.097758 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22923448 99.04% 99.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 223357 0.96% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23146806 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34005271029 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 21045 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25503465992 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 9333292 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 4668829 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3708542 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1634268 # Transaction distribution -system.membus.trans_dist::CleanEvict 3013301 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 977171 # Transaction distribution -system.membus.trans_dist::ReadExResp 977171 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3708543 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14019005 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14019005 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404478784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 404478784 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4685723 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4685723 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4685723 # Request fanout histogram -system.membus.reqLayer0.occupancy 17639856241 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25447920698 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.2 # Layer utilization (%) +sim_seconds 0.787836 +sim_ticks 787835965500 +final_tick 787835965500 +sim_freq 1000000000000 +host_inst_rate 147468 +host_op_rate 158874 +host_tick_rate 75218875 +host_mem_usage 340272 +host_seconds 10473.91 +sim_insts 1544563024 +sim_ops 1664032416 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 787835965500 +system.physmem.bytes_read::cpu.inst 65344 +system.physmem.bytes_read::cpu.data 236015808 +system.physmem.bytes_read::cpu.l2cache.prefetcher 63804544 +system.physmem.bytes_read::total 299885696 +system.physmem.bytes_inst_read::cpu.inst 65344 +system.physmem.bytes_inst_read::total 65344 +system.physmem.bytes_written::writebacks 104593152 +system.physmem.bytes_written::total 104593152 +system.physmem.num_reads::cpu.inst 1021 +system.physmem.num_reads::cpu.data 3687747 +system.physmem.num_reads::cpu.l2cache.prefetcher 996946 +system.physmem.num_reads::total 4685714 +system.physmem.num_writes::writebacks 1634268 +system.physmem.num_writes::total 1634268 +system.physmem.bw_read::cpu.inst 82941 +system.physmem.bw_read::cpu.data 299574808 +system.physmem.bw_read::cpu.l2cache.prefetcher 80987092 +system.physmem.bw_read::total 380644841 +system.physmem.bw_inst_read::cpu.inst 82941 +system.physmem.bw_inst_read::total 82941 +system.physmem.bw_write::writebacks 132760062 +system.physmem.bw_write::total 132760062 +system.physmem.bw_total::writebacks 132760062 +system.physmem.bw_total::cpu.inst 82941 +system.physmem.bw_total::cpu.data 299574808 +system.physmem.bw_total::cpu.l2cache.prefetcher 80987092 +system.physmem.bw_total::total 513404904 +system.physmem.readReqs 4685714 +system.physmem.writeReqs 1634268 +system.physmem.readBursts 4685714 +system.physmem.writeBursts 1634268 +system.physmem.bytesReadDRAM 299374336 +system.physmem.bytesReadWrQ 511360 +system.physmem.bytesWritten 104589440 +system.physmem.bytesReadSys 299885696 +system.physmem.bytesWrittenSys 104593152 +system.physmem.servicedByWrQ 7990 +system.physmem.mergedWrBursts 28 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 301500 +system.physmem.perBankRdBursts::1 301960 +system.physmem.perBankRdBursts::2 285447 +system.physmem.perBankRdBursts::3 288137 +system.physmem.perBankRdBursts::4 288946 +system.physmem.perBankRdBursts::5 285921 +system.physmem.perBankRdBursts::6 281288 +system.physmem.perBankRdBursts::7 278400 +system.physmem.perBankRdBursts::8 294011 +system.physmem.perBankRdBursts::9 300115 +system.physmem.perBankRdBursts::10 292046 +system.physmem.perBankRdBursts::11 297684 +system.physmem.perBankRdBursts::12 299531 +system.physmem.perBankRdBursts::13 298464 +system.physmem.perBankRdBursts::14 294115 +system.physmem.perBankRdBursts::15 290159 +system.physmem.perBankWrBursts::0 103775 +system.physmem.perBankWrBursts::1 101738 +system.physmem.perBankWrBursts::2 99347 +system.physmem.perBankWrBursts::3 99748 +system.physmem.perBankWrBursts::4 99113 +system.physmem.perBankWrBursts::5 98946 +system.physmem.perBankWrBursts::6 102275 +system.physmem.perBankWrBursts::7 103989 +system.physmem.perBankWrBursts::8 105110 +system.physmem.perBankWrBursts::9 104316 +system.physmem.perBankWrBursts::10 101973 +system.physmem.perBankWrBursts::11 102390 +system.physmem.perBankWrBursts::12 102662 +system.physmem.perBankWrBursts::13 102242 +system.physmem.perBankWrBursts::14 104082 +system.physmem.perBankWrBursts::15 102504 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 787835924500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 4685714 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 1634268 +system.physmem.rdQLenPdf::0 2727826 +system.physmem.rdQLenPdf::1 1050681 +system.physmem.rdQLenPdf::2 326941 +system.physmem.rdQLenPdf::3 233426 +system.physmem.rdQLenPdf::4 158423 +system.physmem.rdQLenPdf::5 90275 +system.physmem.rdQLenPdf::6 39813 +system.physmem.rdQLenPdf::7 24457 +system.physmem.rdQLenPdf::8 17994 +system.physmem.rdQLenPdf::9 4464 +system.physmem.rdQLenPdf::10 1780 +system.physmem.rdQLenPdf::11 895 +system.physmem.rdQLenPdf::12 477 +system.physmem.rdQLenPdf::13 261 +system.physmem.rdQLenPdf::14 11 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 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+system.physmem.wrQLenPdf::28 109635 +system.physmem.wrQLenPdf::29 109963 +system.physmem.wrQLenPdf::30 109142 +system.physmem.wrQLenPdf::31 102277 +system.physmem.wrQLenPdf::32 101239 +system.physmem.wrQLenPdf::33 4710 +system.physmem.wrQLenPdf::34 1941 +system.physmem.wrQLenPdf::35 910 +system.physmem.wrQLenPdf::36 451 +system.physmem.wrQLenPdf::37 238 +system.physmem.wrQLenPdf::38 127 +system.physmem.wrQLenPdf::39 69 +system.physmem.wrQLenPdf::40 40 +system.physmem.wrQLenPdf::41 17 +system.physmem.wrQLenPdf::42 11 +system.physmem.wrQLenPdf::43 7 +system.physmem.wrQLenPdf::44 3 +system.physmem.wrQLenPdf::45 2 +system.physmem.wrQLenPdf::46 1 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 4259361 +system.physmem.bytesPerActivate::mean 94.841028 +system.physmem.bytesPerActivate::gmean 78.814946 +system.physmem.bytesPerActivate::stdev 102.698820 +system.physmem.bytesPerActivate::0-127 3400000 79.82% 79.82% +system.physmem.bytesPerActivate::128-255 662329 15.55% 95.37% +system.physmem.bytesPerActivate::256-383 94740 2.22% 97.60% +system.physmem.bytesPerActivate::384-511 35136 0.82% 98.42% +system.physmem.bytesPerActivate::512-639 22172 0.52% 98.94% +system.physmem.bytesPerActivate::640-767 12513 0.29% 99.24% +system.physmem.bytesPerActivate::768-895 7488 0.18% 99.41% +system.physmem.bytesPerActivate::896-1023 5149 0.12% 99.53% +system.physmem.bytesPerActivate::1024-1151 19834 0.47% 100.00% +system.physmem.bytesPerActivate::total 4259361 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+system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 787835965500 +system.membus.trans_dist::ReadResp 3708542 +system.membus.trans_dist::WritebackDirty 1634268 +system.membus.trans_dist::CleanEvict 3013301 +system.membus.trans_dist::UpgradeReq 9 +system.membus.trans_dist::ReadExReq 977171 +system.membus.trans_dist::ReadExResp 977171 +system.membus.trans_dist::ReadSharedReq 3708543 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14019005 +system.membus.pkt_count::total 14019005 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404478784 +system.membus.pkt_size::total 404478784 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 4685723 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 4685723 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 4685723 +system.membus.reqLayer0.occupancy 17639856241 +system.membus.reqLayer0.utilization 2.2 +system.membus.respLayer1.occupancy 25447920698 +system.membus.respLayer1.utilization 3.2 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 0bd2c9396..36301b9e3 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=bzip2 input.source 1 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index c1b3d9c87..61d98894f 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -3,20 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atom gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:22 -gem5 executing on e108600-lin, pid 23077 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:15:54 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 57397 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 832017490500 because target called exit() +Exiting @ tick 832017490500 because exiting with last active thread context diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 2806362a5..5e4ef201f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.832017 # Number of seconds simulated -sim_ticks 832017490500 # Number of ticks simulated -final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2178592 # Simulator instruction rate (inst/s) -host_op_rate 2347103 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1173553065 # Simulator tick rate (ticks/s) -host_mem_usage 260024 # Number of bytes of host memory used -host_seconds 708.97 # Real time elapsed on the host -sim_insts 1544563042 # Number of instructions simulated -sim_ops 1664032434 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory -system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6178262360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6178262360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory -system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1544565590 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1999474787 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory -system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1900666379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9326306381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 832017490500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1664034982 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1544563042 # Number of instructions committed -system.cpu.committedOps 1664032434 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses -system.cpu.num_func_calls 27330256 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls -system.cpu.num_int_insts 1477900422 # number of integer instructions -system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 2605402867 # number of times the integer registers were read -system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written -system.cpu.num_fp_register_reads 24 # number of times the floating registers were read -system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_cc_register_reads 4992096239 # number of times the CC registers were read -system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written -system.cpu.num_mem_refs 633153380 # number of memory refs -system.cpu.num_load_insts 458306334 # Number of load instructions -system.cpu.num_store_insts 174847046 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1664034981.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 213462427 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction -system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::MemRead 458306322 27.54% 89.49% # Class of executed instruction -system.cpu.op_class::MemWrite 174847022 10.51% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 12 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1664032481 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution -system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution -system.membus.trans_dist::WriteReq 172586047 # Transaction distribution -system.membus.trans_dist::WriteResp 172586047 # Transaction distribution -system.membus.trans_dist::SoftPFReq 1 # Transaction distribution -system.membus.trans_dist::SoftPFResp 1 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution -system.membus.trans_dist::StoreCondReq 61 # Transaction distribution -system.membus.trans_dist::StoreCondResp 61 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4344121790 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2172060895 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2172060895 # Request fanout histogram +sim_seconds 0.832017 +sim_ticks 832017490500 +final_tick 832017490500 +sim_freq 1000000000000 +host_inst_rate 917891 +host_op_rate 988888 +host_tick_rate 494444669 +host_mem_usage 271524 +host_seconds 1682.73 +sim_insts 1544563042 +sim_ops 1664032434 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 +system.physmem.bytes_read::cpu.inst 6178262360 +system.physmem.bytes_read::cpu.data 1581387671 +system.physmem.bytes_read::total 7759650031 +system.physmem.bytes_inst_read::cpu.inst 6178262360 +system.physmem.bytes_inst_read::total 6178262360 +system.physmem.bytes_written::cpu.data 624158392 +system.physmem.bytes_written::total 624158392 +system.physmem.num_reads::cpu.inst 1544565590 +system.physmem.num_reads::cpu.data 454909197 +system.physmem.num_reads::total 1999474787 +system.physmem.num_writes::cpu.data 172586108 +system.physmem.num_writes::total 172586108 +system.physmem.bw_read::cpu.inst 7425640002 +system.physmem.bw_read::cpu.data 1900666379 +system.physmem.bw_read::total 9326306381 +system.physmem.bw_inst_read::cpu.inst 7425640002 +system.physmem.bw_inst_read::total 7425640002 +system.physmem.bw_write::cpu.data 750174605 +system.physmem.bw_write::total 750174605 +system.physmem.bw_total::cpu.inst 7425640002 +system.physmem.bw_total::cpu.data 2650840984 +system.physmem.bw_total::total 10076480986 +system.pwrStateResidencyTicks::UNDEFINED 832017490500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 46 +system.cpu.pwrStateResidencyTicks::ON 832017490500 +system.cpu.numCycles 1664034982 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 1544563042 +system.cpu.committedOps 1664032434 +system.cpu.num_int_alu_accesses 1477900422 +system.cpu.num_fp_alu_accesses 36 +system.cpu.num_func_calls 27330256 +system.cpu.num_conditional_control_insts 167612489 +system.cpu.num_int_insts 1477900422 +system.cpu.num_fp_insts 36 +system.cpu.num_int_register_reads 2605402867 +system.cpu.num_int_register_writes 1125475224 +system.cpu.num_fp_register_reads 24 +system.cpu.num_fp_register_writes 16 +system.cpu.num_cc_register_reads 4992096239 +system.cpu.num_cc_register_writes 518236214 +system.cpu.num_mem_refs 633153380 +system.cpu.num_load_insts 458306334 +system.cpu.num_store_insts 174847046 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 1664034982 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 213462427 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% +system.cpu.op_class::IntMult 700322 0.04% 61.95% +system.cpu.op_class::IntDiv 0 0.00% 61.95% +system.cpu.op_class::FloatAdd 0 0.00% 61.95% +system.cpu.op_class::FloatCmp 0 0.00% 61.95% +system.cpu.op_class::FloatCvt 0 0.00% 61.95% +system.cpu.op_class::FloatMult 0 0.00% 61.95% +system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% +system.cpu.op_class::FloatDiv 0 0.00% 61.95% +system.cpu.op_class::FloatMisc 0 0.00% 61.95% +system.cpu.op_class::FloatSqrt 0 0.00% 61.95% +system.cpu.op_class::SimdAdd 0 0.00% 61.95% +system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% +system.cpu.op_class::SimdAlu 0 0.00% 61.95% +system.cpu.op_class::SimdCmp 0 0.00% 61.95% +system.cpu.op_class::SimdCvt 0 0.00% 61.95% +system.cpu.op_class::SimdMisc 0 0.00% 61.95% +system.cpu.op_class::SimdMult 0 0.00% 61.95% +system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% +system.cpu.op_class::SimdShift 0 0.00% 61.95% +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% +system.cpu.op_class::SimdSqrt 0 0.00% 61.95% +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% +system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% +system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% +system.cpu.op_class::MemRead 458306322 27.54% 89.49% +system.cpu.op_class::MemWrite 174847022 10.51% 100.00% +system.cpu.op_class::FloatMemRead 12 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 1664032481 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 +system.membus.trans_dist::ReadReq 1999474725 +system.membus.trans_dist::ReadResp 1999474786 +system.membus.trans_dist::WriteReq 172586047 +system.membus.trans_dist::WriteResp 172586047 +system.membus.trans_dist::SoftPFReq 1 +system.membus.trans_dist::SoftPFResp 1 +system.membus.trans_dist::LoadLockedReq 61 +system.membus.trans_dist::StoreCondReq 61 +system.membus.trans_dist::StoreCondResp 61 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 +system.membus.pkt_count::total 4344121790 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 +system.membus.pkt_size::total 8383808423 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 2172060895 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 2172060895 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 2172060895 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 65c2bbf99..c5f8c8ed0 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=bzip2 input.source 1 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 4382bd2ba..3fe74519c 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -3,20 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:49:25 -gem5 executing on e108600-lin, pid 23292 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:57:50 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54313 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2377029670500 because target called exit() +Exiting @ tick 2379921906500 because exiting with last active thread context diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 11790cc5e..fd3a8134b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,682 +1,682 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.379922 # Number of seconds simulated -sim_ticks 2379921906500 # Number of ticks simulated -final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1526036 # Simulator instruction rate (inst/s) -host_op_rate 1644518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2360243305 # Simulator tick rate (ticks/s) -host_mem_usage 271808 # Number of bytes of host memory used -host_seconds 1008.34 # Real time elapsed on the host -sim_insts 1538759602 # Number of instructions simulated -sim_ops 1658228915 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126077056 # Number of bytes read from this memory -system.physmem.bytes_read::total 126116480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66029376 # Number of bytes written to this memory -system.physmem.bytes_written::total 66029376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1969954 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1970570 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1031709 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1031709 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52975291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52991856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27744346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27744346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27744346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52975291 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80736202 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 4759843813 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1538759602 # Number of instructions committed -system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses -system.cpu.num_func_calls 27330256 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls -system.cpu.num_int_insts 1477900422 # number of integer instructions -system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 2601860297 # number of times the integer registers were read -system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written -system.cpu.num_fp_register_reads 24 # number of times the floating registers were read -system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6356387678 # number of times the CC registers were read -system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written -system.cpu.num_mem_refs 633153380 # number of memory refs -system.cpu.num_load_insts 458306334 # Number of load instructions -system.cpu.num_store_insts 174847046 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4759843812.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 213462427 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction -system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::MemRead 458306322 27.54% 89.49% # Class of executed instruction -system.cpu.op_class::MemWrite 174847022 10.51% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 12 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1664032481 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.747199 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25232837500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.747199 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997009 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997009 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2648 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits -system.cpu.dcache.overall_hits::total 618379947 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses -system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 152766688500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 152766688500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64243803000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64243803000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 217010491500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 217010491500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 217010491500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 217010491500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21141.000605 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21141.000605 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.742189 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.742189 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23807.448903 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23807.448903 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23807.446291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23807.446291 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3667054 # number of writebacks -system.cpu.dcache.writebacks::total 3667054 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145540602500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 145540602500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62354654000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 62354654000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207895256500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 207895256500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207895318500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 207895318500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20141.000605 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20141.000605 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.742189 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.742189 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22807.448903 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22807.448903 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22807.453203 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22807.453203 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.169434 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.169434 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.251548 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.251548 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses -system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1544564953 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1544564953 # number of overall hits -system.cpu.icache.overall_hits::total 1544564953 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses -system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39132000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39132000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39132000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39132000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39132000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39132000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1544565591 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1544565591 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1544565591 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61335.423197 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61335.423197 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61335.423197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61335.423197 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 7 # number of writebacks -system.cpu.icache.writebacks::total 7 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38494000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38494000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38494000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38494000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38494000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38494000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60335.423197 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60335.423197 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1938113 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31679.342131 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16254769 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1970881 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.247463 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 138952277000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10.111234 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.251326 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31645.979571 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000309 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000710 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.965759 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.966777 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2874 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1739 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27370 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 147777841 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 147777841 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3667054 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3667054 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095453 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095453 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6049829 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6049829 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7145282 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7145304 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7145282 # number of overall hits -system.cpu.l2cache.overall_hits::total 7145304 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 793696 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 793696 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 616 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 616 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1176258 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1176258 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1969954 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1970570 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1969954 # number of overall misses -system.cpu.l2cache.overall_misses::total 1970570 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48018674000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 48018674000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 37281000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 37281000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71177285500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 71177285500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37281000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 119195959500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 119233240500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37281000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 119195959500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 119233240500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3667054 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3667054 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 638 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 638 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7226087 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7226087 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420134 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.420134 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162779 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162779 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.216117 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.216169 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.216117 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.216169 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.083155 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.083155 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60521.103896 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60521.103896 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60511.627126 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60511.627126 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60506.980468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60506.980468 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1031709 # number of writebacks -system.cpu.l2cache.writebacks::total 1031709 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 220 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 220 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793696 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 793696 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176258 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176258 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1969954 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1970570 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1969954 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1970570 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40081714000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40081714000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 31121000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 31121000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59414705500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59414705500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31121000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99496419500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 99527540500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31121000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99496419500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 99527540500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420134 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420134 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162779 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162779 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216169 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.216169 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.083155 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.083155 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50521.103896 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50521.103896 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50511.627126 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50511.627126 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1220 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1220 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4698763 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6350490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818066560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818107840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1938113 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66029376 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11053987 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000215 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.014666 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11051609 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2378 0.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11053987 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12780571500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3907683 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1937205 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1176874 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1031709 # Transaction distribution -system.membus.trans_dist::CleanEvict 905404 # Transaction distribution -system.membus.trans_dist::ReadExReq 793696 # Transaction distribution -system.membus.trans_dist::ReadExResp 793696 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1176874 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878253 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5878253 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192145856 # Cumulative packet size per connected master and slave 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100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1970570 +system.membus.reqLayer0.occupancy 8048170000 +system.membus.reqLayer0.utilization 0.3 +system.membus.respLayer1.occupancy 9852850000 +system.membus.respLayer1.utilization 0.4 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 3f64cee84..2dc49338c 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=bzip2 input.source 1 cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/bzip2 +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 715860400..c93c64d50 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -3,20 +3,16 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atom gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18539 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:24 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87211 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2846007227500 because target called exit() +Exiting @ tick 2846007227500 because exiting with last active thread context diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 213b5c5af..3d3e0703d 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846007 # Number of seconds simulated -sim_ticks 2846007227500 # Number of ticks simulated -final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1654731 # Simulator instruction rate (inst/s) -host_op_rate 2578221 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1565575242 # Simulator tick rate (ticks/s) -host_mem_usage 262288 # Number of bytes of host memory used -host_seconds 1817.87 # Real time elapsed on the host -sim_insts 3008081022 # Number of instructions simulated -sim_ops 4686862596 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory -system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory -system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1239184746 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5252417628 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory -system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11281019509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13046253376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11281019509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11281019509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5692014456 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 3008081022 # Number of instructions committed -system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 33534539 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4684368009 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read -system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read -system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written -system.cpu.num_mem_refs 1677713084 # number of memory refs -system.cpu.num_load_insts 1239184746 # Number of load instructions -system.cpu.num_store_insts 438528338 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5692014455.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 248500691 # Number of branches fetched -system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction -system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction -system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction -system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 4686862596 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution -system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution -system.membus.trans_dist::WriteReq 438528338 # Transaction distribution -system.membus.trans_dist::WriteResp 438528338 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5690945966 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5690945966 # Request fanout histogram +sim_seconds 2.846007 +sim_ticks 2846007227500 +final_tick 2846007227500 +sim_freq 1000000000000 +host_inst_rate 877028 +host_op_rate 1366490 +host_tick_rate 829774485 +host_mem_usage 274188 +host_seconds 3429.86 +sim_insts 3008081022 +sim_ops 4686862596 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.physmem.bytes_read::cpu.inst 32105863056 +system.physmem.bytes_read::cpu.data 5023868345 +system.physmem.bytes_read::total 37129731401 +system.physmem.bytes_inst_read::cpu.inst 32105863056 +system.physmem.bytes_inst_read::total 32105863056 +system.physmem.bytes_written::cpu.data 1544656792 +system.physmem.bytes_written::total 1544656792 +system.physmem.num_reads::cpu.inst 4013232882 +system.physmem.num_reads::cpu.data 1239184746 +system.physmem.num_reads::total 5252417628 +system.physmem.num_writes::cpu.data 438528338 +system.physmem.num_writes::total 438528338 +system.physmem.bw_read::cpu.inst 11281019509 +system.physmem.bw_read::cpu.data 1765233867 +system.physmem.bw_read::total 13046253376 +system.physmem.bw_inst_read::cpu.inst 11281019509 +system.physmem.bw_inst_read::total 11281019509 +system.physmem.bw_write::cpu.data 542745211 +system.physmem.bw_write::total 542745211 +system.physmem.bw_total::cpu.inst 11281019509 +system.physmem.bw_total::cpu.data 2307979078 +system.physmem.bw_total::total 13588998587 +system.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.cpu.workload.numSyscalls 46 +system.cpu.pwrStateResidencyTicks::ON 2846007227500 +system.cpu.numCycles 5692014456 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 3008081022 +system.cpu.committedOps 4686862596 +system.cpu.num_int_alu_accesses 4684368009 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 33534539 +system.cpu.num_conditional_control_insts 182173300 +system.cpu.num_int_insts 4684368009 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10688755601 +system.cpu.num_int_register_writes 3999841477 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 1226718827 +system.cpu.num_cc_register_writes 1355930461 +system.cpu.num_mem_refs 1677713084 +system.cpu.num_load_insts 1239184746 +system.cpu.num_store_insts 438528338 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5692014456 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 248500691 +system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% +system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% +system.cpu.op_class::IntMult 6215 0.00% 64.20% +system.cpu.op_class::IntDiv 904 0.00% 64.20% +system.cpu.op_class::FloatAdd 0 0.00% 64.20% +system.cpu.op_class::FloatCmp 0 0.00% 64.20% +system.cpu.op_class::FloatCvt 0 0.00% 64.20% +system.cpu.op_class::FloatMult 0 0.00% 64.20% +system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% +system.cpu.op_class::FloatDiv 0 0.00% 64.20% +system.cpu.op_class::FloatMisc 0 0.00% 64.20% +system.cpu.op_class::FloatSqrt 0 0.00% 64.20% +system.cpu.op_class::SimdAdd 0 0.00% 64.20% +system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% +system.cpu.op_class::SimdAlu 0 0.00% 64.20% +system.cpu.op_class::SimdCmp 0 0.00% 64.20% +system.cpu.op_class::SimdCvt 0 0.00% 64.20% +system.cpu.op_class::SimdMisc 0 0.00% 64.20% +system.cpu.op_class::SimdMult 0 0.00% 64.20% +system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% +system.cpu.op_class::SimdShift 0 0.00% 64.20% +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% +system.cpu.op_class::SimdSqrt 0 0.00% 64.20% +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% +system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% +system.cpu.op_class::MemRead 1239184746 26.44% 90.64% +system.cpu.op_class::MemWrite 438528338 9.36% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 4686862596 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.membus.trans_dist::ReadReq 5252417628 +system.membus.trans_dist::ReadResp 5252417628 +system.membus.trans_dist::WriteReq 438528338 +system.membus.trans_dist::WriteResp 438528338 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 +system.membus.pkt_count_system.cpu.icache_port::total 8026465764 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 +system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 +system.membus.pkt_count::total 11381891932 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 +system.membus.pkt_size_system.cpu.icache_port::total 32105863056 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 +system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 +system.membus.pkt_size::total 38674388193 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 5690945966 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 5690945966 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 5690945966 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 1048d999e..136c4396f 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -100,14 +102,14 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +123,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +136,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -187,6 +191,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -199,15 +204,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -274,6 +280,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -286,15 +293,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -330,7 +338,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=bzip2 input.source 1 cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing drivers= @@ -339,14 +347,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/bzip2 +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -370,6 +379,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -381,7 +391,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -389,6 +399,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -397,6 +414,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -404,7 +422,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 0337bc6ef..f2fd8c974 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -3,20 +3,16 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:20 -gem5 executing on e108600-lin, pid 18569 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87163 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 5895947852500 because target called exit() +Exiting @ tick 5898831348500 because exiting with last active thread context diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 4f06487d9..01185a8e0 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,541 +1,541 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.898831 # Number of seconds simulated -sim_ticks 5898831348500 # Number of ticks simulated -final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1175665 # Simulator instruction rate (inst/s) -host_op_rate 1831792 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2305472192 # Simulator tick rate (ticks/s) -host_mem_usage 275096 # Number of bytes of host memory used -host_seconds 2558.62 # Real time elapsed on the host -sim_insts 3008081022 # Number of instructions simulated -sim_ops 4686862596 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory -system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory -system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 11797662697 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 3008081022 # Number of instructions committed -system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 33534539 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4684368009 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read -system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read -system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written -system.cpu.num_mem_refs 1677713084 # number of memory refs -system.cpu.num_load_insts 1239184746 # Number of load instructions -system.cpu.num_store_insts 438528338 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 248500691 # Number of branches fetched -system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction -system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction -system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction -system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 4686862596 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9108581 # number of replacements -system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits -system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses -system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 216956206000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 216956206000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 216956206000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 216956206000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses 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of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3669049 # number of writebacks -system.cpu.dcache.writebacks::total 3669049 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62376124000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 62376124000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 207843529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000 # number of 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mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10 # number of replacements -system.cpu.icache.tags.tagsinuse 555.760511 # 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(read+write) misses -system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses -system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 42528500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 42528500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 42528500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 42528500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 42528500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 42528500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq 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average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63005.185185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63005.185185 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average 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latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1938075 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31745.660470 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16250887 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1970843 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.245653 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 320350195000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11.856683 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.308015 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000362 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000772 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.967666 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.968801 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 435 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 786 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28399 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 147746387 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 147746387 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3669049 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3669049 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095863 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095863 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046986 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6046986 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7142849 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7142849 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7142849 # number of overall hits -system.cpu.l2cache.overall_hits::total 7142849 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 793964 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 793964 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1175864 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1175864 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1969828 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1970503 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1969828 # number of overall misses -system.cpu.l2cache.overall_misses::total 1970503 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48034822000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 48034822000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40839500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 40839500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71139776000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 71139776000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 40839500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 119215437500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 40839500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 119215437500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3669049 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3669049 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 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miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1032938 # number of writebacks -system.cpu.l2cache.writebacks::total 1032938 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 213 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 213 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793964 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 793964 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1175864 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1175864 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1969828 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1970503 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1969828 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1970503 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40095182000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40095182000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34089500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34089500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59381136000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59381136000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34089500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99476318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 99510407500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34089500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99476318000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 99510407500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162798 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162798 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216222 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.216222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1186 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1186 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818074304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1938075 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66108032 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11051427 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000107 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11051427 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3907605 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1937102 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1176539 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1032938 # Transaction distribution -system.membus.trans_dist::CleanEvict 904164 # Transaction distribution -system.membus.trans_dist::ReadExReq 793964 # Transaction distribution -system.membus.trans_dist::ReadExResp 793964 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1176539 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5878108 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192220224 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1970503 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1970503 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1970503 # Request fanout histogram -system.membus.reqLayer0.occupancy 8039359500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9852515000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +sim_seconds 5.898831 +sim_ticks 5898831348500 +final_tick 5898831348500 +sim_freq 1000000000000 +host_inst_rate 712175 +host_op_rate 1109633 +host_tick_rate 1396571526 +host_mem_usage 285208 +host_seconds 4223.79 +sim_insts 3008081022 +sim_ops 4686862596 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 +system.physmem.bytes_read::cpu.inst 43200 +system.physmem.bytes_read::cpu.data 126068992 +system.physmem.bytes_read::total 126112192 +system.physmem.bytes_inst_read::cpu.inst 43200 +system.physmem.bytes_inst_read::total 43200 +system.physmem.bytes_written::writebacks 66108032 +system.physmem.bytes_written::total 66108032 +system.physmem.num_reads::cpu.inst 675 +system.physmem.num_reads::cpu.data 1969828 +system.physmem.num_reads::total 1970503 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+system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 +system.membus.trans_dist::ReadResp 1176539 +system.membus.trans_dist::WritebackDirty 1032938 +system.membus.trans_dist::CleanEvict 904164 +system.membus.trans_dist::ReadExReq 793964 +system.membus.trans_dist::ReadExResp 793964 +system.membus.trans_dist::ReadSharedReq 1176539 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 +system.membus.pkt_count::total 5878108 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 +system.membus.pkt_size::total 192220224 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1970503 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1970503 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1970503 +system.membus.reqLayer0.occupancy 8039359500 +system.membus.reqLayer0.utilization 0.1 +system.membus.respLayer1.occupancy 9852515000 +system.membus.respLayer1.utilization 0.2 ---------- End Simulation Statistics ---------- |