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-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini21
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout10
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt20
3 files changed, 27 insertions, 24 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index b3f283cca..c948b1f36 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -511,6 +511,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@@ -527,7 +528,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
@@ -543,6 +544,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
@@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index fa5d435db..8a302018f 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 21:12:52
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Mar 3 2013 21:21:53
+gem5 started Mar 4 2013 01:41:28
+gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -26,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 506353996500 because target called exit()
+Exiting @ tick 517371024000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index dd9108dcd..8f6283962 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.517371 # Nu
sim_ticks 517371024000 # Number of ticks simulated
final_tick 517371024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 170437 # Simulator instruction rate (inst/s)
-host_op_rate 190135 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 57090080 # Simulator tick rate (ticks/s)
-host_mem_usage 485276 # Number of bytes of host memory used
-host_seconds 9062.36 # Real time elapsed on the host
+host_inst_rate 139447 # Simulator instruction rate (inst/s)
+host_op_rate 155563 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 46709499 # Simulator tick rate (ticks/s)
+host_mem_usage 485516 # Number of bytes of host memory used
+host_seconds 11076.36 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1723073835 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory
@@ -177,13 +177,13 @@ system.physmem.writeRowHits 271156 # Nu
system.physmem.readRowHitRate 36.86 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 24.63 # Row buffer hit rate for writes
system.physmem.avgGap 154562.37 # Average gap between requests
-system.cpu.branchPred.lookups 303290886 # Number of BP lookups
+system.cpu.branchPred.lookups 303290873 # Number of BP lookups
system.cpu.branchPred.condPredicted 249488582 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15222231 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 174596646 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 174596633 # Number of BTB lookups
system.cpu.branchPred.BTBHits 161469311 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 92.481336 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 92.481343 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 17557313 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 202 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
@@ -234,7 +234,7 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 298209547 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2186343540 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 303290886 # Number of branches that fetch encountered
+system.cpu.fetch.Branches 303290873 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 179026624 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 435120674 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 87852250 # Number of cycles fetch has spent squashing
@@ -430,7 +430,7 @@ system.cpu.iew.iewExecSquashedInsts 29996171 # Nu
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 130 # number of nop insts executed
system.cpu.iew.exec_refs 764045166 # number of memory reference insts executed
-system.cpu.iew.exec_branches 238330381 # Number of branches executed
+system.cpu.iew.exec_branches 238330373 # Number of branches executed
system.cpu.iew.exec_stores 190143920 # Number of stores executed
system.cpu.iew.exec_rate 1.921365 # Inst execution rate
system.cpu.iew.wb_sent 1965882705 # cumulative count of insts sent to commit