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-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini240
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr6
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout26
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt315
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini535
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr6
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout26
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt525
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini102
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr6
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout26
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt77
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini205
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr6
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout26
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt266
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini535
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr2
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout27
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt536
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini102
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr2
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout27
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt87
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini205
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr2
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout27
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt280
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini102
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr4
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout27
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt45
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini205
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr4
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout27
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt234
36 files changed, 4873 insertions, 0 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
new file mode 100644
index 000000000..0d09e2e14
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -0,0 +1,240 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=InOrderCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+activity=0
+cachePorts=2
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+cpu_id=0
+dataMemPort=dcache_port
+defer_registration=false
+div16Latency=1
+div16RepeatRate=1
+div24Latency=1
+div24RepeatRate=1
+div32Latency=1
+div32RepeatRate=1
+div8Latency=1
+div8RepeatRate=1
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchBuffSize=4
+fetchMemPort=icache_port
+functionTrace=false
+functionTraceStart=0
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+memBlockSize=64
+multLatency=1
+multRepeatRate=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+stageTracing=false
+stageWidth=4
+system=system
+threadModel=SMT
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
new file mode 100755
index 000000000..8bc14bb8a
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:50
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 1009857089500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
new file mode 100644
index 000000000..bf815a6e1
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -0,0 +1,315 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 1.009857 # Number of seconds simulated
+sim_ticks 1009857089500 # Number of ticks simulated
+final_tick 1009857089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 102085 # Simulator instruction rate (inst/s)
+host_tick_rate 56650413 # Simulator tick rate (ticks/s)
+host_mem_usage 208040 # Number of bytes of host memory used
+host_seconds 17826.12 # Real time elapsed on the host
+sim_insts 1819780127 # Number of instructions simulated
+system.physmem.bytes_read 172617984 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 54912 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 74938304 # Number of bytes written to this memory
+system.physmem.num_reads 2697156 # Number of read requests responded to by this memory
+system.physmem.num_writes 1170911 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 170933081 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 54376 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 74206841 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 245139922 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 444614420 # DTB read hits
+system.cpu.dtb.read_misses 4897078 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 449511498 # DTB read accesses
+system.cpu.dtb.write_hits 160920903 # DTB write hits
+system.cpu.dtb.write_misses 1701304 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 162622207 # DTB write accesses
+system.cpu.dtb.data_hits 605535323 # DTB hits
+system.cpu.dtb.data_misses 6598382 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 612133705 # DTB accesses
+system.cpu.itb.fetch_hits 233080732 # ITB hits
+system.cpu.itb.fetch_misses 22 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 233080754 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 29 # Number of system calls
+system.cpu.numCycles 2019714180 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.contextSwitches 1 # Number of context switches
+system.cpu.threadCycles 1746235830 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled 7533712 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 442869413 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 1576844767 # Number of cycles cpu stages are processed.
+system.cpu.activity 78.072669 # Percentage of cycles cpu is active
+system.cpu.comLoads 444595663 # Number of Load instructions committed
+system.cpu.comStores 160728502 # Number of Store instructions committed
+system.cpu.comBranches 214632552 # Number of Branches instructions committed
+system.cpu.comNops 83736345 # Number of Nop instructions committed
+system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed
+system.cpu.comInts 916086844 # Number of Integer instructions committed
+system.cpu.comFloats 190 # Number of Floating Point instructions committed
+system.cpu.committedInsts 1819780127 # Number of Instructions Simulated (Per-Thread)
+system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total 1819780127 # Number of Instructions Simulated (Total)
+system.cpu.cpi 1.109867 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
+system.cpu.cpi_total 1.109867 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.901009 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
+system.cpu.ipc_total 0.901009 # IPC: Total IPC of All Threads
+system.cpu.branch_predictor.lookups 330376347 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 257464252 # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect 140461747 # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups 220099806 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 142435401 # Number of BTB hits
+system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
+system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.BTBHitPct 64.714006 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 178933469 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 151442878 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 1665721133 # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 3041923750 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File
+system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
+system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards 654640669 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 617252269 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 126684712 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 7178577 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 133863289 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 81336473 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 62.204199 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 1137868323 # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
+system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
+system.cpu.stage0.idleCycles 827214176 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 1192500004 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 59.043008 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 1086300254 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 933413926 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 46.215149 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 1046559994 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 973154186 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 48.182767 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 1609984436 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 409729744 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 20.286521 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 997434545 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 1022279635 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 50.615065 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.tagsinuse 664.479191 # Cycle average of tags in use
+system.cpu.icache.total_refs 233079667 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 271654.623543 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 664.479191 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.324453 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 233079667 # number of ReadReq hits
+system.cpu.icache.demand_hits 233079667 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 233079667 # number of overall hits
+system.cpu.icache.ReadReq_misses 1062 # number of ReadReq misses
+system.cpu.icache.demand_misses 1062 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 1062 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 58337000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 58337000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 58337000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 233080729 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 233080729 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 233080729 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 54931.261770 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 54931.261770 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 54931.261770 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 83500 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333 # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits 204 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits 204 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 204 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 858 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 858 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 858 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 45872500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 45872500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 45872500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53464.452214 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9107352 # number of replacements
+system.cpu.dcache.tagsinuse 4082.611665 # Cycle average of tags in use
+system.cpu.dcache.total_refs 595070081 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 65.310155 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 12612838000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4082.611665 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.996731 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 437271428 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 157798653 # number of WriteReq hits
+system.cpu.dcache.demand_hits 595070081 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 595070081 # number of overall hits
+system.cpu.dcache.ReadReq_misses 7324235 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 2929849 # number of WriteReq misses
+system.cpu.dcache.demand_misses 10254084 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 10254084 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 180892053500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 110288339500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 291180393000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 291180393000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.016474 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.018229 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.016940 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.016940 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 24697.740242 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 37643.011466 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 28396.528934 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 28396.528934 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 10999000 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 8091026500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 208994 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.701557 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 3058572 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 101953 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 1040683 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 1142636 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 1142636 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 7222282 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 1889166 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 9111448 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 9111448 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 156087671000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 59191835500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 215279506500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 215279506500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.015052 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.015052 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.960181 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.257462 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 2686299 # number of replacements
+system.cpu.l2cache.tagsinuse 26355.239368 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7564573 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 223979031000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 15511.274798 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 10843.964569 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.473367 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.330932 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 5414817 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 3058572 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 1000333 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 6415150 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 6415150 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 1807881 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 889275 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 2697156 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 2697156 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 94453509000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 46507390000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 140960899000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 140960899000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 7222698 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 3058572 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 1889608 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 9112306 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 9112306 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.250305 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.470613 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.295990 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.295990 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52245.423786 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.096764 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52262.790510 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52262.790510 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8292.857143 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 1170911 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 1807881 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 889275 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 2697156 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 2697156 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 72354298500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671113500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 108025412000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 108025412000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250305 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470613 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.295990 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.295990 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.604575 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.578786 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
new file mode 100644
index 000000000..4951679e2
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
new file mode 100755
index 000000000..35ea78ab1
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:43:49
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 615292058500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
new file mode 100644
index 000000000..3e098da07
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -0,0 +1,525 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.615292 # Number of seconds simulated
+sim_ticks 615292058500 # Number of ticks simulated
+final_tick 615292058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 151558 # Simulator instruction rate (inst/s)
+host_tick_rate 53715526 # Simulator tick rate (ticks/s)
+host_mem_usage 208624 # Number of bytes of host memory used
+host_seconds 11454.64 # Real time elapsed on the host
+sim_insts 1736043781 # Number of instructions simulated
+system.physmem.bytes_read 173080384 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 60288 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 74996480 # Number of bytes written to this memory
+system.physmem.num_reads 2704381 # Number of read requests responded to by this memory
+system.physmem.num_writes 1171820 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 281297933 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 97983 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 121887612 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 403185545 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 602552271 # DTB read hits
+system.cpu.dtb.read_misses 10614048 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 613166319 # DTB read accesses
+system.cpu.dtb.write_hits 207913538 # DTB write hits
+system.cpu.dtb.write_misses 6806894 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 214720432 # DTB write accesses
+system.cpu.dtb.data_hits 810465809 # DTB hits
+system.cpu.dtb.data_misses 17420942 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 827886751 # DTB accesses
+system.cpu.itb.fetch_hits 385401096 # ITB hits
+system.cpu.itb.fetch_misses 38 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 385401134 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 29 # Number of system calls
+system.cpu.numCycles 1230584118 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.BPredUnit.lookups 368788427 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 284655595 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 19443984 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 335810201 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 329206676 # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS 24336435 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 1745 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 397544739 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3103801885 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 368788427 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 353543111 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 607804339 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 131920976 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 113986099 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 951 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 385401096 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 9585477 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1225061020 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.533590 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.019465 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 617256681 50.39% 50.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 52795543 4.31% 54.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 34983733 2.86% 57.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 53721044 4.39% 61.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 135046011 11.02% 72.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 74719502 6.10% 79.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 51323378 4.19% 83.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 43567102 3.56% 86.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 161648026 13.20% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 1225061020 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.299686 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.522218 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 426009855 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 101612047 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 578250802 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 13464213 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 105724103 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 57118243 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 889 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3023280149 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 1933 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 105724103 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 448226724 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 58166398 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 3444 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 568166155 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 44774196 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2937967281 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 510732 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1525332 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 40266143 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2197783940 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3797275773 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3796267426 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1008347 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 821580977 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 180 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 178 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 93606956 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 663953354 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 248514283 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 54484359 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 31450059 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2647456890 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 154 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2459087861 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1981205 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 899874302 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 377613541 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 125 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1225061020 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.007319 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.938295 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 390052689 31.84% 31.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 197664545 16.14% 47.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 194534552 15.88% 63.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 152397104 12.44% 76.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 138172730 11.28% 87.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 75830053 6.19% 93.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 56958095 4.65% 98.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 14036871 1.15% 99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 5414381 0.44% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1225061020 # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1870870 11.50% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 11042349 67.89% 79.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3352440 20.61% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1607157901 65.36% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 88 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 251 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 149 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 19 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 631365239 25.67% 91.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 220564170 8.97% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total 2459087861 # Type of FU issued
+system.cpu.iq.rate 1.998309 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 16265659 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006615 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6159722029 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3546409355 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2357254024 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1761577 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1006663 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 825129 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2474476437 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 877083 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 54564037 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads 219357691 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 276764 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 87944 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 87785781 # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads 71 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 162830 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles 105724103 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 22305472 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1113476 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2788688851 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 12944530 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 663953354 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 248514283 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 154 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 231462 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 18115 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 87944 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 20335960 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 2039327 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 22375287 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2405013673 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 613166540 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 54074188 # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp 0 # number of swp insts executed
+system.cpu.iew.exec_nop 141231807 # number of nop insts executed
+system.cpu.iew.exec_refs 827886992 # number of memory reference insts executed
+system.cpu.iew.exec_branches 294323253 # Number of branches executed
+system.cpu.iew.exec_stores 214720452 # Number of stores executed
+system.cpu.iew.exec_rate 1.954368 # Inst execution rate
+system.cpu.iew.wb_sent 2384887539 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2358079153 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1347433304 # num instructions producing a value
+system.cpu.iew.wb_consumers 1703552370 # num instructions consuming a value
+system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate 1.916228 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.790955 # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 736139047 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 19443221 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1119336917 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.625766 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.487685 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 586822597 52.43% 52.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 186310200 16.64% 69.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 95274520 8.51% 77.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 53747896 4.80% 82.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 37177452 3.32% 85.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 26985316 2.41% 88.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 21737766 1.94% 90.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 22635146 2.02% 92.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 88646024 7.92% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1119336917 # Number of insts commited each cycle
+system.cpu.commit.count 1819780126 # Number of instructions committed
+system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.refs 605324165 # Number of memory references committed
+system.cpu.commit.loads 444595663 # Number of loads committed
+system.cpu.commit.membars 0 # Number of memory barriers committed
+system.cpu.commit.branches 214632552 # Number of branches committed
+system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
+system.cpu.commit.function_calls 16767440 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 88646024 # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads 3500830866 # The number of ROB reads
+system.cpu.rob.rob_writes 5217723058 # The number of ROB writes
+system.cpu.timesIdled 398057 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5523098 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
+system.cpu.cpi 0.708844 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.708844 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.410748 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.410748 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3237009112 # number of integer regfile reads
+system.cpu.int_regfile_writes 1887111006 # number of integer regfile writes
+system.cpu.fp_regfile_reads 12550 # number of floating regfile reads
+system.cpu.fp_regfile_writes 508 # number of floating regfile writes
+system.cpu.misc_regfile_reads 25 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.tagsinuse 746.155324 # Cycle average of tags in use
+system.cpu.icache.total_refs 385399748 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 942 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 409129.244161 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 746.155324 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.364334 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 385399748 # number of ReadReq hits
+system.cpu.icache.demand_hits 385399748 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 385399748 # number of overall hits
+system.cpu.icache.ReadReq_misses 1348 # number of ReadReq misses
+system.cpu.icache.demand_misses 1348 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 1348 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 47398000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 47398000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 47398000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 385401096 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 385401096 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 385401096 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35161.721068 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35161.721068 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35161.721068 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits 406 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits 406 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 406 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 942 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 942 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 942 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 33448000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 33448000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 33448000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35507.430998 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35507.430998 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35507.430998 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9159821 # number of replacements
+system.cpu.dcache.tagsinuse 4086.961398 # Cycle average of tags in use
+system.cpu.dcache.total_refs 693411949 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9163917 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 75.667637 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 5157991000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4086.961398 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.997793 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 537597174 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 155814773 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits 693411947 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 693411947 # number of overall hits
+system.cpu.dcache.ReadReq_misses 10313435 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 4913729 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses 15227164 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 15227164 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 172073260500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 137521396881 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency 309594657381 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 309594657381 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 547910609 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 708639111 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 708639111 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.018823 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.030572 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate 0.021488 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.021488 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 16684.379210 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27987.175703 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 20331.734615 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 20331.734615 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 119268264 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 2148368000 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 37813 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 65113 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.160315 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 32994.455792 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 3077535 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 3034555 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 3028693 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 6063248 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 6063248 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 7278880 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 1885036 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 9163916 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 9163916 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 81039107500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 38640356536 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 119679464036 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 119679464036 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.013285 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.011728 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.012932 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.012932 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11133.458375 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20498.471401 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 13059.860439 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 13059.860439 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 2693797 # number of replacements
+system.cpu.l2cache.tagsinuse 26669.588705 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7633154 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2718439 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.807918 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 126954186500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 15903.024773 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 10766.563932 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.485322 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.328569 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 5458962 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 3077535 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 1001516 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 6460478 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 6460478 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 1820852 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 883529 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 2704381 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 2704381 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 62524059000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 30450873000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 92974932000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 92974932000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 7279814 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 3077535 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 1885045 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 9164859 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 9164859 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.250123 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.468704 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.295082 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.295082 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34337.803951 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.052081 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34379.376279 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34379.376279 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 17570000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 1704 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10311.032864 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 1171820 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 1820852 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 883529 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 2704381 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 2704381 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 56737753000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 27632234500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 84369987500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 84369987500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250123 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468704 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.295082 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.295082 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31160.002570 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31274.847232 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31197.522649 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31197.522649 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
new file mode 100644
index 000000000..52ac7c920
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
new file mode 100755
index 000000000..3465b9fda
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:45:21
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 913189263000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
new file mode 100644
index 000000000..1f32f6942
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -0,0 +1,77 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.913189 # Number of seconds simulated
+sim_ticks 913189263000 # Number of ticks simulated
+final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 4221832 # Simulator instruction rate (inst/s)
+host_tick_rate 2118570165 # Simulator tick rate (ticks/s)
+host_mem_usage 198896 # Number of bytes of host memory used
+host_seconds 431.04 # Real time elapsed on the host
+sim_insts 1819780127 # Number of instructions simulated
+system.physmem.bytes_read 9280309971 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 7305514036 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 827777307 # Number of bytes written to this memory
+system.physmem.num_reads 2270974172 # Number of read requests responded to by this memory
+system.physmem.num_writes 160728502 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 10162526375 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999999926 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 906468506 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11068994882 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 444595663 # DTB read hits
+system.cpu.dtb.read_misses 4897078 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 449492741 # DTB read accesses
+system.cpu.dtb.write_hits 160728502 # DTB write hits
+system.cpu.dtb.write_misses 1701304 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 162429806 # DTB write accesses
+system.cpu.dtb.data_hits 605324165 # DTB hits
+system.cpu.dtb.data_misses 6598382 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 611922547 # DTB accesses
+system.cpu.itb.fetch_hits 1826378509 # ITB hits
+system.cpu.itb.fetch_misses 18 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 1826378527 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 29 # Number of system calls
+system.cpu.numCycles 1826378527 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 1819780127 # Number of instructions executed
+system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
+system.cpu.num_func_calls 33534877 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1725565901 # number of integer instructions
+system.cpu.num_fp_insts 805526 # number of float instructions
+system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
+system.cpu.num_mem_refs 611922547 # number of memory refs
+system.cpu.num_load_insts 449492741 # Number of load instructions
+system.cpu.num_store_insts 162429806 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1826378527 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
new file mode 100644
index 000000000..b74c06509
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
new file mode 100755
index 000000000..5e40861f7
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:52:43
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 2663443716000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
new file mode 100644
index 000000000..99a911858
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -0,0 +1,266 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 2.663444 # Number of seconds simulated
+sim_ticks 2663443716000 # Number of ticks simulated
+final_tick 2663443716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1948044 # Simulator instruction rate (inst/s)
+host_tick_rate 2851171142 # Simulator tick rate (ticks/s)
+host_mem_usage 207608 # Number of bytes of host memory used
+host_seconds 934.16 # Real time elapsed on the host
+sim_insts 1819780127 # Number of instructions simulated
+system.physmem.bytes_read 172614208 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 51328 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 74939072 # Number of bytes written to this memory
+system.physmem.num_reads 2697097 # Number of read requests responded to by this memory
+system.physmem.num_writes 1170923 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 64808656 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 19271 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 28136158 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 92944814 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 444595663 # DTB read hits
+system.cpu.dtb.read_misses 4897078 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 449492741 # DTB read accesses
+system.cpu.dtb.write_hits 160728502 # DTB write hits
+system.cpu.dtb.write_misses 1701304 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 162429806 # DTB write accesses
+system.cpu.dtb.data_hits 605324165 # DTB hits
+system.cpu.dtb.data_misses 6598382 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 611922547 # DTB accesses
+system.cpu.itb.fetch_hits 1826378510 # ITB hits
+system.cpu.itb.fetch_misses 18 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 1826378528 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 29 # Number of system calls
+system.cpu.numCycles 5326887432 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 1819780127 # Number of instructions executed
+system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
+system.cpu.num_func_calls 33534877 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1725565901 # number of integer instructions
+system.cpu.num_fp_insts 805526 # number of float instructions
+system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
+system.cpu.num_mem_refs 611922547 # number of memory refs
+system.cpu.num_load_insts 449492741 # Number of load instructions
+system.cpu.num_store_insts 162429806 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 5326887432 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.tagsinuse 612.356766 # Cycle average of tags in use
+system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 612.356766 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.299002 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits
+system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 1826377708 # number of overall hits
+system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
+system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 802 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9107638 # number of replacements
+system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use
+system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4079.504248 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.995973 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
+system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 596212431 # number of overall hits
+system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
+system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 9111734 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 177010400000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 63798266000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 240808666000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 240808666000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33767.845574 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 26428.412638 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 26428.412638 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 3058802 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 58130306000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 213473464000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 213473464000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 2686269 # number of replacements
+system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7565346 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2710912 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.790701 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 582065656000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 15312.508302 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 10727.578894 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.467301 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.327380 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 5415352 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 3058802 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 1000087 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 6415439 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 6415439 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 1807864 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 889233 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 2697097 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 2697097 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 94008928000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 46240116000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 140249044000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 140249044000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 3058802 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.250285 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.470663 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.295977 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.295977 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 1170923 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 1807864 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 889233 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 2697097 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 2697097 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 72314560000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 35569320000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 107883880000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 107883880000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250285 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470663 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.295977 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.295977 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..669a8b83b
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..1474108e5
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:36:09
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 483463019500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..bd2b3efef
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,536 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.483463 # Number of seconds simulated
+sim_ticks 483463019500 # Number of ticks simulated
+final_tick 483463019500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 152421 # Simulator instruction rate (inst/s)
+host_tick_rate 42766664 # Simulator tick rate (ticks/s)
+host_mem_usage 220608 # Number of bytes of host memory used
+host_seconds 11304.67 # Real time elapsed on the host
+sim_insts 1723073849 # Number of instructions simulated
+system.physmem.bytes_read 188174592 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 45888 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 77926272 # Number of bytes written to this memory
+system.physmem.num_reads 2940228 # Number of read requests responded to by this memory
+system.physmem.num_writes 1217598 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 389222307 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 94915 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 161183522 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 550405829 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.numCycles 966926040 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.BPredUnit.lookups 298898243 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 243989412 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 18339920 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 264347245 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 238745657 # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS 17668157 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 3423 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 295953389 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2175230772 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 298898243 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 256413814 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 484717826 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 87053301 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 107577195 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 285045078 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 5311594 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 956547645 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.521914 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.026495 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 471829873 49.33% 49.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 35367236 3.70% 53.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 65085859 6.80% 59.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 66860371 6.99% 66.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 46850107 4.90% 71.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 59747954 6.25% 77.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 54343246 5.68% 83.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 17692463 1.85% 85.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 138770536 14.51% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 956547645 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.309122 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.249635 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 322987122 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 92097194 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 459538157 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 13626726 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 68298446 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46874540 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 671 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2352694278 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2235 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 68298446 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 343127088 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 46537686 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 27220 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 451783493 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 46773712 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2295847883 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 19963 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2697037 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 37730930 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2264588148 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 10605407368 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 10605405778 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1590 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 558268197 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 10043 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 10038 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 98804137 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 618742816 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 222099567 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 74239442 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 61602093 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2187718033 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2090 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2018498325 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3274725 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 458502719 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1049949895 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1587 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 956547645 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.110191 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.840946 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 262039584 27.39% 27.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 150878554 15.77% 43.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 168430661 17.61% 60.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 136432052 14.26% 75.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 124835406 13.05% 88.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 73540708 7.69% 95.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 29241453 3.06% 98.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 10225405 1.07% 99.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 923822 0.10% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 956547645 # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 901388 3.68% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 177 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 19016870 77.70% 81.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4557312 18.62% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1238993791 61.38% 61.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1017752 0.05% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 14 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 13 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 2 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 583952461 28.93% 90.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 194534287 9.64% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total 2018498325 # Type of FU issued
+system.cpu.iq.rate 2.087542 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 24475747 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.012126 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5021294480 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2646401011 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1958335598 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 287 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 294 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2042973928 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 55719619 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads 132816045 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 210497 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 180679 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 47252521 # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 451790 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles 68298446 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 22155006 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1213609 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2187738627 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 7300026 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 618742816 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 222099567 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2027 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 219640 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 61277 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 180679 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 18953795 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1821941 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 20775736 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1986087052 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 570299160 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 32411273 # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp 0 # number of swp insts executed
+system.cpu.iew.exec_nop 18504 # number of nop insts executed
+system.cpu.iew.exec_refs 761501875 # number of memory reference insts executed
+system.cpu.iew.exec_branches 238650211 # Number of branches executed
+system.cpu.iew.exec_stores 191202715 # Number of stores executed
+system.cpu.iew.exec_rate 2.054022 # Inst execution rate
+system.cpu.iew.wb_sent 1967277607 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1958335722 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1288034280 # num instructions producing a value
+system.cpu.iew.wb_consumers 2036866160 # num instructions consuming a value
+system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate 2.025321 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.632361 # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 464746992 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 18339818 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 888249200 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.939854 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.672088 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 383075847 43.13% 43.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 200735352 22.60% 65.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 81917807 9.22% 74.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 38649475 4.35% 79.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 19675094 2.22% 81.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 31029952 3.49% 85.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 22284246 2.51% 87.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 12052552 1.36% 88.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 98828875 11.13% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 888249200 # Number of insts commited each cycle
+system.cpu.commit.count 1723073867 # Number of instructions committed
+system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.refs 660773817 # Number of memory references committed
+system.cpu.commit.loads 485926771 # Number of loads committed
+system.cpu.commit.membars 62 # Number of memory barriers committed
+system.cpu.commit.branches 213462365 # Number of branches committed
+system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions.
+system.cpu.commit.function_calls 13665177 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 98828875 # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads 2977240585 # The number of ROB reads
+system.cpu.rob.rob_writes 4444170390 # The number of ROB writes
+system.cpu.timesIdled 920776 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 10378395 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 1723073849 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated
+system.cpu.cpi 0.561163 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.561163 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.782012 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.782012 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 9942029327 # number of integer regfile reads
+system.cpu.int_regfile_writes 1939848996 # number of integer regfile writes
+system.cpu.fp_regfile_reads 117 # number of floating regfile reads
+system.cpu.fp_regfile_writes 59 # number of floating regfile writes
+system.cpu.misc_regfile_reads 2913839911 # number of misc regfile reads
+system.cpu.misc_regfile_writes 126 # number of misc regfile writes
+system.cpu.icache.replacements 10 # number of replacements
+system.cpu.icache.tagsinuse 609.858480 # Cycle average of tags in use
+system.cpu.icache.total_refs 285044064 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 744 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 383123.741935 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 609.858480 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.297782 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 285044064 # number of ReadReq hits
+system.cpu.icache.demand_hits 285044064 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 285044064 # number of overall hits
+system.cpu.icache.ReadReq_misses 1014 # number of ReadReq misses
+system.cpu.icache.demand_misses 1014 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 1014 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 35191500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 35191500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 35191500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 285045078 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 285045078 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 285045078 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 34705.621302 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 34705.621302 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 34705.621302 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 744 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 744 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 744 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 25627000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 25627000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 25627000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34444.892473 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34444.892473 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34444.892473 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9570827 # number of replacements
+system.cpu.dcache.tagsinuse 4087.732038 # Cycle average of tags in use
+system.cpu.dcache.total_refs 666909210 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9574923 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 69.651653 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 3484303000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4087.732038 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.997981 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 499513800 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 167395288 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 60 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits 666909088 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 666909088 # number of overall hits
+system.cpu.dcache.ReadReq_misses 10448466 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 5190759 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses 15639225 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 15639225 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 184465722500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 128555474171 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency 313021196671 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 313021196671 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 509962266 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 63 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 682548313 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 682548313 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.020489 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.030076 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate 0.047619 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate 0.022913 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.022913 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 17654.813874 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 24766.219000 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 20015.134808 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 20015.134808 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 266703683 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 90656 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 2941.930848 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 16333.333333 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 3128328 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 2766203 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 3298099 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 6064302 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 6064302 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 7682263 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 1892660 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 9574923 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 9574923 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 92044930000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 45262385908 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 137307315908 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 137307315908 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.015064 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010966 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.014028 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.014028 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11981.486445 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23914.694614 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 14340.304972 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 14340.304972 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 2927819 # number of replacements
+system.cpu.l2cache.tagsinuse 26780.774124 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7851022 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2955142 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.656733 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 102041743500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 15984.490640 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 10796.283484 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.487808 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.329476 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 5655252 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 3128328 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 980176 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 6635428 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 6635428 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 2027753 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 912486 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 2940239 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 2940239 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 69614113000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 31648901500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 101263014500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 101263014500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 7683005 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 3128328 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 1892662 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 9575667 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 9575667 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.263927 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.482118 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.307053 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.307053 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34330.666999 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34684.259813 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34440.402464 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34440.402464 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 56231500 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 6603 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8516.053309 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 1217598 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 2027742 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 912486 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 2940228 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 2940228 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 63235914500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 28815026500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 92050941000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 92050941000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263926 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482118 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.307052 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.307052 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.384778 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31578.595726 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31307.415955 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31307.415955 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..bbede2479
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..e599bde0b
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:37:28
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 861538205000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..e23300649
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,87 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.861538 # Number of seconds simulated
+sim_ticks 861538205000 # Number of ticks simulated
+final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3027828 # Simulator instruction rate (inst/s)
+host_tick_rate 1513916118 # Simulator tick rate (ticks/s)
+host_mem_usage 210380 # Number of bytes of host memory used
+host_seconds 569.08 # Real time elapsed on the host
+sim_insts 1723073862 # Number of instructions simulated
+system.physmem.bytes_read 7759650064 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 6178262392 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 624158392 # Number of bytes written to this memory
+system.physmem.num_reads 2026949786 # Number of read requests responded to by this memory
+system.physmem.num_writes 172586108 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 9006739363 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7171199555 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 724469778 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9731209141 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.numCycles 1723076411 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 1723073862 # Number of instructions executed
+system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
+system.cpu.num_func_calls 27330134 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1536941850 # number of integer instructions
+system.cpu.num_fp_insts 36 # number of float instructions
+system.cpu.num_int_register_reads 7861284536 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
+system.cpu.num_mem_refs 660773816 # number of memory refs
+system.cpu.num_load_insts 485926770 # Number of load instructions
+system.cpu.num_store_insts 174847046 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1723076411 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..71abd898d
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..8198567b7
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:45:39
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 2431419954000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..04e3122e6
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,280 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 2.431420 # Number of seconds simulated
+sim_ticks 2431419954000 # Number of ticks simulated
+final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1410228 # Simulator instruction rate (inst/s)
+host_tick_rate 1996689457 # Simulator tick rate (ticks/s)
+host_mem_usage 219344 # Number of bytes of host memory used
+host_seconds 1217.73 # Real time elapsed on the host
+sim_insts 1717270343 # Number of instructions simulated
+system.physmem.bytes_read 172766016 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 75006720 # Number of bytes written to this memory
+system.physmem.num_reads 2699469 # Number of read requests responded to by this memory
+system.physmem.num_writes 1171980 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 71055605 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 16214 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 30848937 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 101904542 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.numCycles 4862839908 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 1717270343 # Number of instructions executed
+system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
+system.cpu.num_func_calls 27330134 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1536941850 # number of integer instructions
+system.cpu.num_fp_insts 36 # number of float instructions
+system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
+system.cpu.num_mem_refs 660773816 # number of memory refs
+system.cpu.num_load_insts 485926770 # Number of load instructions
+system.cpu.num_store_insts 174847046 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 4862839908 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 7 # number of replacements
+system.cpu.icache.tagsinuse 514.872896 # Cycle average of tags in use
+system.cpu.icache.total_refs 1544564961 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 514.872896 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.251403 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 1544564961 # number of ReadReq hits
+system.cpu.icache.demand_hits 1544564961 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 1544564961 # number of overall hits
+system.cpu.icache.ReadReq_misses 638 # number of ReadReq misses
+system.cpu.icache.demand_misses 638 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 638 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 34804000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 34804000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 34804000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 1544565599 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 1544565599 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 1544565599 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 54551.724138 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 54551.724138 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 54551.724138 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 638 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 638 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 638 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 32890000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 32890000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 32890000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9111140 # number of replacements
+system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use
+system.cpu.dcache.total_refs 645855060 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4083.719979 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.997002 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 475158040 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 170696898 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 61 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits 61 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits 645854938 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 645854938 # number of overall hits
+system.cpu.dcache.ReadReq_misses 7226087 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 1889149 # number of WriteReq misses
+system.cpu.dcache.demand_misses 9115236 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 9115236 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 177140908000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 63824222000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 240965130000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 240965130000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 482384127 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 61 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses 61 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 654970174 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 654970174 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.014980 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.010946 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.013917 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.013917 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 24514.084594 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 26435.424162 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 26435.424162 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 3061985 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 7226087 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 1889149 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 9115236 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 9115236 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 155462647000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 58156775000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 213619422000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 213619422000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.014980 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.013917 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.013917 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.084594 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23435.424162 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 2687066 # number of replacements
+system.cpu.l2cache.tagsinuse 26134.517233 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7569171 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2714383 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.788542 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 538044123000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 15027.621217 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 11106.896016 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.458607 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.338956 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 5417164 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 3061985 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 999241 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 6416405 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 6416405 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 1809561 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 889908 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 2699469 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 2699469 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 94097172000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 46275216000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 140372388000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 140372388000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 7226725 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 3061985 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 1889149 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 9115874 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 9115874 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.250398 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.471063 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.296128 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.296128 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 1171980 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 1809561 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 889908 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 2699469 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 2699469 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 72382440000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 35596320000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 107978760000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 107978760000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250398 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471063 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.296128 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.296128 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..fe30d10a3
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
new file mode 100755
index 000000000..a5a0064e6
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:13:31
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 2846007259500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..6725100b8
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 2.846007 # Number of seconds simulated
+sim_ticks 2846007259500 # Number of ticks simulated
+final_tick 2846007259500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2006575 # Simulator instruction rate (inst/s)
+host_tick_rate 1218454030 # Simulator tick rate (ticks/s)
+host_mem_usage 204704 # Number of bytes of host memory used
+host_seconds 2335.75 # Real time elapsed on the host
+sim_insts 4686862651 # Number of instructions simulated
+system.physmem.bytes_read 37129731755 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 32105863408 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 1544656790 # Number of bytes written to this memory
+system.physmem.num_reads 5252417675 # Number of read requests responded to by this memory
+system.physmem.num_writes 438528337 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 13046253354 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 11281019506 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 542745204 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 13588998558 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.numCycles 5692014520 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 4686862651 # Number of instructions executed
+system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4686862580 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
+system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 1677713086 # number of memory refs
+system.cpu.num_load_insts 1239184749 # Number of load instructions
+system.cpu.num_store_insts 438528337 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 5692014520 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
new file mode 100644
index 000000000..e57f67518
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
new file mode 100755
index 000000000..5d5232885
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:30:19
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 5923548078000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..94c5d24c6
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -0,0 +1,234 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 5.923548 # Number of seconds simulated
+sim_ticks 5923548078000 # Number of ticks simulated
+final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1176749 # Simulator instruction rate (inst/s)
+host_tick_rate 1487248019 # Simulator tick rate (ticks/s)
+host_mem_usage 213688 # Number of bytes of host memory used
+host_seconds 3982.89 # Real time elapsed on the host
+sim_insts 4686862651 # Number of instructions simulated
+system.physmem.bytes_read 173910080 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 43200 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 75176384 # Number of bytes written to this memory
+system.physmem.num_reads 2717345 # Number of read requests responded to by this memory
+system.physmem.num_writes 1174631 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 29359107 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7293 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 12691107 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 42050214 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.numCycles 11847096156 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 4686862651 # Number of instructions executed
+system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4686862580 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
+system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 1677713086 # number of memory refs
+system.cpu.num_load_insts 1239184749 # Number of load instructions
+system.cpu.num_store_insts 438528337 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 11847096156 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 10 # number of replacements
+system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use
+system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits
+system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 4013232252 # number of overall hits
+system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
+system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 675 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9108581 # number of replacements
+system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 436638510 # number of WriteReq hits
+system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 1668600409 # number of overall hits
+system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses
+system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 9112677 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 63869078000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.004309 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 3053391 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 214339587000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.005432 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 2706631 # number of replacements
+system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 999077 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 6396007 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 890750 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 2717345 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 94982940000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 3053391 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 1174631 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 108693800000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.298172 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------