diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
7 files changed, 1363 insertions, 1324 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 46df80677..617d9f369 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.208801 # Nu sim_ticks 1208800797500 # Number of ticks simulated final_tick 1208800797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239332 # Simulator instruction rate (inst/s) -host_op_rate 239332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158403619 # Simulator tick rate (ticks/s) -host_mem_usage 291552 # Number of bytes of host memory used -host_seconds 7631.14 # Real time elapsed on the host +host_inst_rate 309355 # Simulator instruction rate (inst/s) +host_op_rate 309355 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 204748768 # Simulator tick rate (ticks/s) +host_mem_usage 299532 # Number of bytes of host memory used +host_seconds 5903.82 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -703,6 +703,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68146.812957 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77658.597897 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.938429 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18249028 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121989 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1267 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1267 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7239716 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4708732 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6334139 # Transaction distribution @@ -718,15 +724,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 820072320 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1920882 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20169910 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095235 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293539 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000063 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.007925 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18249028 90.48% 90.48% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1920882 9.52% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20168643 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1267 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20169910 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12811105000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index cb7ba764c..bb4922b1c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.669557 # Nu sim_ticks 669556582000 # Number of ticks simulated final_tick 669556582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125035 # Simulator instruction rate (inst/s) -host_op_rate 125035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48223337 # Simulator tick rate (ticks/s) -host_mem_usage 292576 # Number of bytes of host memory used -host_seconds 13884.49 # Real time elapsed on the host +host_inst_rate 160543 # Simulator instruction rate (inst/s) +host_op_rate 160543 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61918292 # Simulator tick rate (ticks/s) +host_mem_usage 299292 # Number of bytes of host memory used +host_seconds 10813.55 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1026,6 +1026,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72271.293375 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79676.114069 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79672.524401 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18419494 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207224 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1279 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7333064 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4752054 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6384201 # Transaction distribution @@ -1041,15 +1047,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 828161152 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1929031 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20348525 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.094800 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.292938 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000063 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.007928 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18419494 90.52% 90.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1929031 9.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20347246 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1279 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20348525 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12937495000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 018ebe8b0..d971ffdfc 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.623057 # Nu sim_ticks 2623057163500 # Number of ticks simulated final_tick 2623057163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1251674 # Simulator instruction rate (inst/s) -host_op_rate 1251674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1804181213 # Simulator tick rate (ticks/s) -host_mem_usage 294596 # Number of bytes of host memory used -host_seconds 1453.88 # Real time elapsed on the host +host_inst_rate 1405944 # Simulator instruction rate (inst/s) +host_op_rate 1405944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2026548224 # Simulator tick rate (ticks/s) +host_mem_usage 297224 # Number of bytes of host memory used +host_seconds 1294.35 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -478,6 +478,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42556.733167 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4701388 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution @@ -493,15 +499,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 818685568 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1919524 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20139699 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095310 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293643 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000056 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.007464 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18220175 90.47% 90.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1919524 9.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20138577 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20139699 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12789513500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index bd1131ae5..766f60b6c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.116876 # Number of seconds simulated -sim_ticks 1116876142500 # Number of ticks simulated -final_tick 1116876142500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.116866 # Number of seconds simulated +sim_ticks 1116865669500 # Number of ticks simulated +final_tick 1116865669500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161785 # Simulator instruction rate (inst/s) -host_op_rate 174299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116987267 # Simulator tick rate (ticks/s) -host_mem_usage 309392 # Number of bytes of host memory used -host_seconds 9546.99 # Real time elapsed on the host +host_inst_rate 226280 # Simulator instruction rate (inst/s) +host_op_rate 243783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 163622006 # Simulator tick rate (ticks/s) +host_mem_usage 317884 # Number of bytes of host memory used +host_seconds 6825.89 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130931520 # Number of bytes read from this memory -system.physmem.bytes_read::total 130981888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130931456 # Number of bytes read from this memory +system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67207936 # Number of bytes written to this memory -system.physmem.bytes_written::total 67207936 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory +system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2045805 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2046592 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050124 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050124 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117230116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117275213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60174923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60174923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60174923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117230116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177450137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2046592 # Number of read requests accepted -system.physmem.writeReqs 1050124 # Number of write requests accepted -system.physmem.readBursts 2046592 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1050124 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 130897216 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84672 # Total number of bytes read from write queue -system.physmem.bytesWritten 67206464 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130981888 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67207936 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1323 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 2045804 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 45098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117231158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45098 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45098 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45098 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117231158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2046591 # Number of read requests accepted +system.physmem.writeReqs 1050123 # Number of write requests accepted +system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 130897024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 84800 # Total number of bytes read from write queue +system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1325 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127284 # Per bank write bursts -system.physmem.perBankRdBursts::1 124662 # Per bank write bursts -system.physmem.perBankRdBursts::2 121597 # Per bank write bursts +system.physmem.perBankRdBursts::0 127282 # Per bank write bursts +system.physmem.perBankRdBursts::1 124660 # Per bank write bursts +system.physmem.perBankRdBursts::2 121599 # Per bank write bursts system.physmem.perBankRdBursts::3 123658 # Per bank write bursts -system.physmem.perBankRdBursts::4 122617 # Per bank write bursts +system.physmem.perBankRdBursts::4 122616 # Per bank write bursts system.physmem.perBankRdBursts::5 122675 # Per bank write bursts system.physmem.perBankRdBursts::6 123246 # Per bank write bursts -system.physmem.perBankRdBursts::7 123759 # Per bank write bursts +system.physmem.perBankRdBursts::7 123764 # Per bank write bursts system.physmem.perBankRdBursts::8 131397 # Per bank write bursts -system.physmem.perBankRdBursts::9 133511 # Per bank write bursts -system.physmem.perBankRdBursts::10 132080 # Per bank write bursts -system.physmem.perBankRdBursts::11 133309 # Per bank write bursts -system.physmem.perBankRdBursts::12 133252 # Per bank write bursts -system.physmem.perBankRdBursts::13 133368 # Per bank write bursts -system.physmem.perBankRdBursts::14 129308 # Per bank write bursts -system.physmem.perBankRdBursts::15 129546 # Per bank write bursts +system.physmem.perBankRdBursts::9 133514 # Per bank write bursts +system.physmem.perBankRdBursts::10 132084 # Per bank write bursts +system.physmem.perBankRdBursts::11 133304 # Per bank write bursts +system.physmem.perBankRdBursts::12 133248 # Per bank write bursts +system.physmem.perBankRdBursts::13 133365 # Per bank write bursts +system.physmem.perBankRdBursts::14 129309 # Per bank write bursts +system.physmem.perBankRdBursts::15 129545 # Per bank write bursts system.physmem.perBankWrBursts::0 66136 # Per bank write bursts system.physmem.perBankWrBursts::1 64410 # Per bank write bursts system.physmem.perBankWrBursts::2 62576 # Per bank write bursts @@ -71,34 +71,34 @@ system.physmem.perBankWrBursts::3 63006 # Pe system.physmem.perBankWrBursts::4 63000 # Per bank write bursts system.physmem.perBankWrBursts::5 63100 # Per bank write bursts system.physmem.perBankWrBursts::6 64443 # Per bank write bursts -system.physmem.perBankWrBursts::7 65435 # Per bank write bursts -system.physmem.perBankWrBursts::8 67311 # Per bank write bursts -system.physmem.perBankWrBursts::9 67795 # Per bank write bursts -system.physmem.perBankWrBursts::10 67548 # Per bank write bursts -system.physmem.perBankWrBursts::11 67883 # Per bank write bursts -system.physmem.perBankWrBursts::12 67328 # Per bank write bursts +system.physmem.perBankWrBursts::7 65436 # Per bank write bursts +system.physmem.perBankWrBursts::8 67310 # Per bank write bursts +system.physmem.perBankWrBursts::9 67797 # Per bank write bursts +system.physmem.perBankWrBursts::10 67549 # Per bank write bursts +system.physmem.perBankWrBursts::11 67882 # Per bank write bursts +system.physmem.perBankWrBursts::12 67326 # Per bank write bursts system.physmem.perBankWrBursts::13 67793 # Per bank write bursts -system.physmem.perBankWrBursts::14 66483 # Per bank write bursts +system.physmem.perBankWrBursts::14 66482 # Per bank write bursts system.physmem.perBankWrBursts::15 65854 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1116876049000 # Total gap between requests +system.physmem.totGap 1116865575000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2046592 # Read request sizes (log2) +system.physmem.readPktSize::6 2046591 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1050124 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1916546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128705 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1050123 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1916631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128617 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 78 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see @@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1910492 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.692259 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.833601 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.494474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485528 77.76% 77.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305524 15.99% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52470 2.75% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20903 1.09% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13406 0.70% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7575 0.40% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5481 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5100 0.27% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14505 0.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1910492 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61132 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.413630 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.636391 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61087 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1910448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.693777 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.830782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.503425 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1485607 77.76% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305343 15.98% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52494 2.75% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20883 1.09% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13429 0.70% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7609 0.40% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5497 0.29% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5095 0.27% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14491 0.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1910448 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61128 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.415767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.633753 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61083 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 20 0.03% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes @@ -220,76 +220,76 @@ system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61132 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61132 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.177599 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.142637 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.096979 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 26963 44.11% 44.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1122 1.84% 45.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28754 47.04% 92.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3885 6.36% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 352 0.58% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 46 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61128 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61128 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.178707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.143614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.099153 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 26983 44.14% 44.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1095 1.79% 45.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28688 46.93% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3942 6.45% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 361 0.59% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 8 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61132 # Writes before turning the bus around for reads -system.physmem.totQLat 38139021250 # Total ticks spent queuing -system.physmem.totMemAccLat 76487815000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10226345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18647.44 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 61128 # Writes before turning the bus around for reads +system.physmem.totQLat 38113681000 # Total ticks spent queuing +system.physmem.totMemAccLat 76462418500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10226330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18635.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37397.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37385.07 # Average memory access latency per DRAM burst system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.17 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.39 # Data bus utilization in percentage system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing -system.physmem.readRowHits 773003 # Number of row buffer hits during reads -system.physmem.writeRowHits 411872 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes -system.physmem.avgGap 360664.67 # Average gap between requests +system.physmem.readRowHits 773150 # Number of row buffer hits during reads +system.physmem.writeRowHits 411758 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.80 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.21 # Row buffer hit rate for writes +system.physmem.avgGap 360661.52 # Average gap between requests system.physmem.pageHitRate 38.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7041119400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3841880625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7718053200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3318446880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 420554384415 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 301217964750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 816640712790 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.183278 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 498392390000 # Time in different power states -system.physmem_0.memoryStateTime::REF 37294920000 # Time in different power states +system.physmem_0.actEnergy 7040439000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3841509375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7717788000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 420410239110 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301335056250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 816611331495 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.167175 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 498591665750 # Time in different power states +system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 581188236250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 580976292250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7402200120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4038898875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8234990400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3486207600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 429475728015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 293392224750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 818979113280 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.276976 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 485326311500 # Time in different power states -system.physmem_1.memoryStateTime::REF 37294920000 # Time in different power states +system.physmem_1.actEnergy 7402532760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4039080375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8234920200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 429557025690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 293311559250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 818979159315 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.287251 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 485194866750 # Time in different power states +system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 594254742500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 594372992750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 239639069 # Number of BP lookups -system.cpu.branchPred.condPredicted 186342280 # Number of conditional branches predicted +system.cpu.branchPred.lookups 239639075 # Number of BP lookups +system.cpu.branchPred.condPredicted 186342287 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14526140 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 130646098 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122079384 # Number of BTB hits +system.cpu.branchPred.BTBLookups 130646101 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122079387 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 93.442809 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15657029 # Number of times the RAS was used to get a target. @@ -412,68 +412,68 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2233752285 # number of cpu cycles simulated +system.cpu.numCycles 2233731339 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41470092 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41470082 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446203 # CPI: cycles per instruction -system.cpu.ipc 0.691466 # IPC: instructions per cycle -system.cpu.tickCycles 1834122948 # Number of cycles that the object actually ticked -system.cpu.idleCycles 399629337 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.446190 # CPI: cycles per instruction +system.cpu.ipc 0.691472 # IPC: instructions per cycle +system.cpu.tickCycles 1834124286 # Number of cycles that the object actually ticked +system.cpu.idleCycles 399607053 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 9221039 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.616333 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624218905 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4085.616235 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624218894 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9225135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.665016 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.665015 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616333 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616235 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 245 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 253 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1229 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276841915 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276841915 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453887721 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453887721 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331061 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331061 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276841917 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276841917 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453887722 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453887722 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331049 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331049 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624218782 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624218782 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624218783 # number of overall hits -system.cpu.dcache.overall_hits::total 624218783 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 624218771 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624218771 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624218772 # number of overall hits +system.cpu.dcache.overall_hits::total 624218772 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7334497 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7334497 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254986 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254986 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254998 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254998 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9589483 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9589483 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9589485 # number of overall misses -system.cpu.dcache.overall_misses::total 9589485 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 190949826000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 190949826000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060330000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109060330000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 300010156000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 300010156000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 300010156000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 300010156000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461222218 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461222218 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9589495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9589495 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9589497 # number of overall misses +system.cpu.dcache.overall_misses::total 9589497 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 190935436500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 190935436500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060065500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109060065500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 299995502000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 299995502000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 299995502000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 299995502000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461222219 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461222219 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -482,10 +482,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633808265 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633808265 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633808268 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633808268 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633808266 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633808266 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633808269 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633808269 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses @@ -496,14 +496,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26034.481438 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26034.481438 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48364.082970 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48364.082970 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.331649 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31285.331649 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.325124 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31285.325124 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26032.519544 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26032.519544 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48363.708305 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48363.708305 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31283.764369 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31283.764369 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31283.757845 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31283.757845 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,12 +516,12 @@ system.cpu.dcache.writebacks::writebacks 3684564 # nu system.cpu.dcache.writebacks::total 3684564 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364134 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364134 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364349 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364349 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364349 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364349 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364146 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364146 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364361 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364361 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364361 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364361 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334282 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7334282 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890852 # number of WriteReq MSHR misses @@ -532,16 +532,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9225134 system.cpu.dcache.demand_mshr_misses::total 9225134 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9225135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9225135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183609818500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 183609818500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84766639000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84766639000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183595384500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 183595384500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84757207500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84757207500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268376457500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 268376457500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268376531500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 268376531500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268352592000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 268352592000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268352666000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 268352666000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -552,24 +552,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25034.463973 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25034.463973 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44829.864527 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44829.864527 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25032.495955 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25032.495955 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44824.876564 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44824.876564 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.876335 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.876335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.881203 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.881203 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29089.289326 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29089.289326 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29089.294195 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29089.294195 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.386126 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 465281345 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 661.385274 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 465281545 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567416.274390 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567416.518293 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.386126 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 661.385274 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.322942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.322942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id @@ -577,44 +577,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 32 system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 930565150 # Number of tag accesses -system.cpu.icache.tags.data_accesses 930565150 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 465281345 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 465281345 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 465281345 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 465281345 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 465281345 # number of overall hits -system.cpu.icache.overall_hits::total 465281345 # number of overall hits +system.cpu.icache.tags.tag_accesses 930565550 # Number of tag accesses +system.cpu.icache.tags.data_accesses 930565550 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 465281545 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 465281545 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 465281545 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 465281545 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 465281545 # number of overall hits +system.cpu.icache.overall_hits::total 465281545 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses system.cpu.icache.overall_misses::total 820 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62363500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62363500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62363500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62363500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62363500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62363500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 465282165 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 465282165 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 465282165 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 465282165 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 465282165 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 465282165 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62174000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62174000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62174000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62174000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62174000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62174000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465282365 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465282365 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465282365 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465282365 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465282365 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465282365 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76053.048780 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76053.048780 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76053.048780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76053.048780 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75821.951220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75821.951220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75821.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75821.951220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -629,35 +629,35 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 820 system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61543500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 61543500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61543500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 61543500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61543500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 61543500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61354000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 61354000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61354000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 61354000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61354000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61354000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75053.048780 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75053.048780 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74821.951220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74821.951220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2013891 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31258.308104 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14509189 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2043666 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.099589 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2013890 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31258.297879 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14509190 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2043665 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.099593 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14832.412998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588444 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.306662 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.452649 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14832.420356 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588666 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.288857 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.452650 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000811 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.500467 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.953928 # Average percentage of cache occupancy @@ -668,46 +668,46 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15557 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 151497950 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 151497950 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 151497949 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 151497949 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 3684564 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 3684564 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1089696 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1089696 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1089697 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1089697 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 32 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 32 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7179326 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7179358 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7179327 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7179359 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7179326 # 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number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 108661637000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 59976000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 179092270500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179152246500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 59976000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 179092270500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179152246500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 2045808 # number of overall misses +system.cpu.l2cache.overall_misses::total 2046596 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70421216500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70421216500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59756500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 59756500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108645799000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 108645799000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 59756500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 179067015500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 179126772000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 59756500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 179067015500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 179126772000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 3684564 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3684564 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890852 # number of ReadExReq accesses(hits+misses) @@ -734,18 +734,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.221830 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960976 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87911.260104 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87911.260104 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76111.675127 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76111.675127 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87302.755869 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87302.755869 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87536.650596 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87536.650596 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87899.615555 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87899.615555 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75833.121827 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75833.121827 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87290.031037 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87290.031037 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87524.246114 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87524.246114 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -754,8 +754,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050124 # number of writebacks -system.cpu.l2cache.writebacks::total 1050124 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks +system.cpu.l2cache.writebacks::total 1050123 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits @@ -768,30 +768,30 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 4 system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 243 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 243 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801156 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 801156 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801155 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 801155 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 787 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 787 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2045805 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2046592 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2045804 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2046591 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2045805 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2046592 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62419073500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62419073500 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158608712000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158660583000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51871000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158608712000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158660583000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423701 # mshr miss rate for ReadExReq accesses @@ -806,21 +806,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77911.260104 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77911.260104 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66188.691233 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66188.691233 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77302.824732 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77302.824732 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77899.615555 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77899.615555 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65909.783990 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65909.783990 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77290.099859 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77290.099859 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18447023 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221080 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1287 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1281 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4734688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4734687 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6498677 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1890852 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1890852 # Transaction distribution @@ -832,18 +838,18 @@ system.cpu.toL2Bus.pkt_count::total 27671384 # Pa system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220736 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 826273216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2013891 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20460914 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.098426 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.297890 # Request fanout histogram +system.cpu.toL2Bus.snoops 2013890 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20460913 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000220 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.014837 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18447023 90.16% 90.16% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2013891 9.84% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20456426 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4481 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20460914 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 20460913 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12908075500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1230499 # Layer occupancy (ticks) @@ -851,29 +857,29 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L system.cpu.toL2Bus.respLayer1.occupancy 13837704496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 1245436 # Transaction distribution -system.membus.trans_dist::Writeback 1050124 # Transaction distribution +system.membus.trans_dist::Writeback 1050123 # Transaction distribution system.membus.trans_dist::CleanEvict 962723 # Transaction distribution -system.membus.trans_dist::ReadExReq 801156 # Transaction distribution -system.membus.trans_dist::ReadExResp 801156 # Transaction distribution +system.membus.trans_dist::ReadExReq 801155 # Transaction distribution +system.membus.trans_dist::ReadExResp 801155 # Transaction distribution system.membus.trans_dist::ReadSharedReq 1245436 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106031 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6106031 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198189824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6106028 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4059439 # Request fanout histogram +system.membus.snoop_fanout::samples 4059437 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4059439 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4059437 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4059439 # Request fanout histogram -system.membus.reqLayer0.occupancy 8663029500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4059437 # Request fanout histogram +system.membus.reqLayer0.occupancy 8662977500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11191724000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11191643250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index d6d64bb1d..09d71d56d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.770368 # Number of seconds simulated -sim_ticks 770368138000 # Number of ticks simulated -final_tick 770368138000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.770336 # Number of seconds simulated +sim_ticks 770336310500 # Number of ticks simulated +final_tick 770336310500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139680 # Simulator instruction rate (inst/s) -host_op_rate 150484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69667014 # Simulator tick rate (ticks/s) -host_mem_usage 312136 # Number of bytes of host memory used -host_seconds 11057.86 # Real time elapsed on the host +host_inst_rate 130811 # Simulator instruction rate (inst/s) +host_op_rate 140929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65240720 # Simulator tick rate (ticks/s) +host_mem_usage 314688 # Number of bytes of host memory used +host_seconds 11807.60 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 65792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 238160448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63905024 # Number of bytes read from this memory -system.physmem.bytes_read::total 302131264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104870272 # Number of bytes written to this memory -system.physmem.bytes_written::total 104870272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3721257 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 998516 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4720801 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1638598 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1638598 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 85403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309151477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82953877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 392190758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 85403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136130074 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136130074 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136130074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 85403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309151477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82953877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 528320833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4720801 # Number of read requests accepted -system.physmem.writeReqs 1638598 # Number of write requests accepted -system.physmem.readBursts 4720801 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1638598 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 301683008 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448256 # Total number of bytes read from write queue -system.physmem.bytesWritten 104867648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 302131264 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104870272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7004 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 12 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 66496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238054976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63977600 # Number of bytes read from this memory +system.physmem.bytes_read::total 302099072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104804160 # Number of bytes written to this memory +system.physmem.bytes_written::total 104804160 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1039 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3719609 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 999650 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4720298 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1637565 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1637565 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 86321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309027334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 83051518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 392165172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 86321 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86321 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136049877 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136049877 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136049877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 86321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309027334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 83051518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 528215049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4720298 # Number of read requests accepted +system.physmem.writeReqs 1637565 # Number of write requests accepted +system.physmem.readBursts 4720298 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1637565 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301639360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 459712 # Total number of bytes read from write queue +system.physmem.bytesWritten 104801536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 302099072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104804160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7183 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 296472 # Per bank write bursts -system.physmem.perBankRdBursts::1 294660 # Per bank write bursts -system.physmem.perBankRdBursts::2 288575 # Per bank write bursts -system.physmem.perBankRdBursts::3 292960 # Per bank write bursts -system.physmem.perBankRdBursts::4 290749 # Per bank write bursts -system.physmem.perBankRdBursts::5 289530 # Per bank write bursts -system.physmem.perBankRdBursts::6 284828 # Per bank write bursts -system.physmem.perBankRdBursts::7 280913 # Per bank write bursts -system.physmem.perBankRdBursts::8 297084 # Per bank write bursts -system.physmem.perBankRdBursts::9 304004 # Per bank write bursts -system.physmem.perBankRdBursts::10 295272 # Per bank write bursts -system.physmem.perBankRdBursts::11 301446 # Per bank write bursts -system.physmem.perBankRdBursts::12 303554 # Per bank write bursts -system.physmem.perBankRdBursts::13 302544 # Per bank write bursts -system.physmem.perBankRdBursts::14 297853 # Per bank write bursts -system.physmem.perBankRdBursts::15 293353 # Per bank write bursts -system.physmem.perBankWrBursts::0 103842 # Per bank write bursts -system.physmem.perBankWrBursts::1 101847 # Per bank write bursts -system.physmem.perBankWrBursts::2 99335 # Per bank write bursts -system.physmem.perBankWrBursts::3 100097 # Per bank write bursts -system.physmem.perBankWrBursts::4 99287 # Per bank write bursts -system.physmem.perBankWrBursts::5 99035 # Per bank write bursts -system.physmem.perBankWrBursts::6 102669 # Per bank write bursts -system.physmem.perBankWrBursts::7 104576 # Per bank write bursts -system.physmem.perBankWrBursts::8 105230 # Per bank write bursts -system.physmem.perBankWrBursts::9 104522 # Per bank write bursts -system.physmem.perBankWrBursts::10 102176 # Per bank write bursts -system.physmem.perBankWrBursts::11 103126 # Per bank write bursts -system.physmem.perBankWrBursts::12 103102 # Per bank write bursts -system.physmem.perBankWrBursts::13 102725 # Per bank write bursts -system.physmem.perBankWrBursts::14 104361 # Per bank write bursts -system.physmem.perBankWrBursts::15 102627 # Per bank write bursts +system.physmem.perBankRdBursts::0 296850 # Per bank write bursts +system.physmem.perBankRdBursts::1 294498 # Per bank write bursts +system.physmem.perBankRdBursts::2 288916 # Per bank write bursts +system.physmem.perBankRdBursts::3 292682 # Per bank write bursts +system.physmem.perBankRdBursts::4 290729 # Per bank write bursts +system.physmem.perBankRdBursts::5 289596 # Per bank write bursts +system.physmem.perBankRdBursts::6 284483 # Per bank write bursts +system.physmem.perBankRdBursts::7 281209 # Per bank write bursts +system.physmem.perBankRdBursts::8 297427 # Per bank write bursts +system.physmem.perBankRdBursts::9 303552 # Per bank write bursts +system.physmem.perBankRdBursts::10 295336 # Per bank write bursts +system.physmem.perBankRdBursts::11 302232 # Per bank write bursts +system.physmem.perBankRdBursts::12 303231 # Per bank write bursts +system.physmem.perBankRdBursts::13 302345 # Per bank write bursts +system.physmem.perBankRdBursts::14 297342 # Per bank write bursts +system.physmem.perBankRdBursts::15 292687 # Per bank write bursts +system.physmem.perBankWrBursts::0 104014 # Per bank write bursts +system.physmem.perBankWrBursts::1 101992 # Per bank write bursts +system.physmem.perBankWrBursts::2 99263 # Per bank write bursts +system.physmem.perBankWrBursts::3 99947 # Per bank write bursts +system.physmem.perBankWrBursts::4 99433 # Per bank write bursts +system.physmem.perBankWrBursts::5 98879 # Per bank write bursts +system.physmem.perBankWrBursts::6 102579 # Per bank write bursts +system.physmem.perBankWrBursts::7 104318 # Per bank write bursts +system.physmem.perBankWrBursts::8 105363 # Per bank write bursts +system.physmem.perBankWrBursts::9 104471 # Per bank write bursts +system.physmem.perBankWrBursts::10 102169 # Per bank write bursts +system.physmem.perBankWrBursts::11 102930 # Per bank write bursts +system.physmem.perBankWrBursts::12 102920 # Per bank write bursts +system.physmem.perBankWrBursts::13 102581 # Per bank write bursts +system.physmem.perBankWrBursts::14 104115 # Per bank write bursts +system.physmem.perBankWrBursts::15 102550 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 770367991500 # Total gap between requests +system.physmem.totGap 770336158500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4720801 # Read request sizes (log2) +system.physmem.readPktSize::6 4720298 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1638598 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2785137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1045602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 327608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 232677 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 151173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 83865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 38451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23803 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1637565 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2783946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1045590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 328353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 232144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 151285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 83614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 38578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 25057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 60199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 75747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 106693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 114123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 105280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 101866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 23160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 60100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 75642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 106708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 114322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 105421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,115 +197,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4291005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.744514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.906714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 101.391830 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3416666 79.62% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 676199 15.76% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96816 2.26% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35217 0.82% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22960 0.54% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11971 0.28% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7013 0.16% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5097 0.12% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19066 0.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4291005 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98697 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.759952 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 32.369236 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 98.446894 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 96231 97.50% 97.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1192 1.21% 98.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 746 0.76% 99.47% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 392 0.40% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 102 0.10% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 22 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4289513 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.751761 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.903148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.431882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3416049 79.64% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 675171 15.74% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96645 2.25% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35451 0.83% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23003 0.54% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12074 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6995 0.16% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5025 0.12% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19100 0.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4289513 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98662 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.769871 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.372187 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98.540692 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 96215 97.52% 97.52% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1195 1.21% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 729 0.74% 99.47% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 403 0.41% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 87 0.09% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-3839 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98697 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98697 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.601893 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.567781 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.107607 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 72640 73.60% 73.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1756 1.78% 75.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18593 18.84% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3904 3.96% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1031 1.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 392 0.40% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 184 0.19% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 91 0.09% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 55 0.06% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 31 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 17 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98662 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98662 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.597312 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.563431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.103098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 72815 73.80% 73.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1780 1.80% 75.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18354 18.60% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3927 3.98% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 986 1.00% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 404 0.41% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 201 0.20% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 116 0.12% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 44 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 22 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 12 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98697 # Writes before turning the bus around for reads -system.physmem.totQLat 131099404549 # Total ticks spent queuing -system.physmem.totMemAccLat 219483098299 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23568985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27811.85 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 98662 # Writes before turning the bus around for reads +system.physmem.totQLat 131160021238 # Total ticks spent queuing +system.physmem.totMemAccLat 219530927488 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23565575000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27828.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46561.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 391.61 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 136.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 392.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.13 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46578.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 391.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 136.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 392.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.12 # Data bus utilization in percentage system.physmem.busUtilRead 3.06 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing -system.physmem.readRowHits 1707890 # Number of row buffer hits during reads -system.physmem.writeRowHits 353447 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.57 # Row buffer hit rate for writes -system.physmem.avgGap 121138.49 # Average gap between requests -system.physmem.pageHitRate 32.45 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16077957840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8772695250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18085189200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5253161040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50316417840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 410294660580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 102310835250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 611110917000 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.275483 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 167665323859 # Time in different power states -system.physmem_0.memoryStateTime::REF 25724140000 # Time in different power states +system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing +system.physmem.readRowHits 1707273 # Number of row buffer hits during reads +system.physmem.writeRowHits 353841 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.61 # Row buffer hit rate for writes +system.physmem.avgGap 121162.75 # Average gap between requests +system.physmem.pageHitRate 32.46 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16082924760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8775405375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18087474600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5251508640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50314383600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 409609386630 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102893262750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 611014346355 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.182199 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 168633417027 # Time in different power states +system.physmem_0.memoryStateTime::REF 25723100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 576975365641 # Time in different power states +system.physmem_0.memoryStateTime::ACT 575976400473 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16361828280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8927584875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18681803400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5364480960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50316417840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 411044339970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 101653218750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 612349674075 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.883504 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 166565047661 # Time in different power states -system.physmem_1.memoryStateTime::REF 25724140000 # Time in different power states +system.physmem_1.actEnergy 16345687680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8918778000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18674323200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5359543200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50314383600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 410844304170 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 101810001750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 612267021600 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.808347 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 166829398639 # Time in different power states +system.physmem_1.memoryStateTime::REF 25723100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 578076556839 # Time in different power states +system.physmem_1.memoryStateTime::ACT 577780670361 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286273758 # Number of BP lookups -system.cpu.branchPred.condPredicted 223402774 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14629982 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157694112 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150348271 # Number of BTB hits +system.cpu.branchPred.lookups 286278310 # Number of BP lookups +system.cpu.branchPred.condPredicted 223407435 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14630059 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158227088 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150348964 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.341715 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16640713 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.021002 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16641238 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -424,128 +424,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1540736277 # number of cpu cycles simulated +system.cpu.numCycles 1540672622 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13925194 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067435227 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286273758 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166988984 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1512088964 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29284609 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 664 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656921798 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 960 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1540658157 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.437628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228937 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13926355 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067514794 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286278310 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166990202 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1512022873 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29284737 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 188 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1021 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656940964 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 966 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1540592805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.437738 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228920 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 458280922 29.75% 29.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465413379 30.21% 59.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101412163 6.58% 66.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515551693 33.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 458181319 29.74% 29.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465421558 30.21% 59.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101422593 6.58% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515567335 33.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1540658157 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185803 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.341849 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74641640 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 543291473 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849963258 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58120186 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14641600 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42202380 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 756 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037144212 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52474408 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14641600 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139712786 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 462567620 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14938 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837837029 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 85884184 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976322026 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26747258 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45146985 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125259 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1471751 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25027790 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985779948 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127891240 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432801848 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 139 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1540592805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185814 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.341956 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74646858 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 543216907 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849967493 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58119883 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14641664 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42201795 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 757 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037179352 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52470113 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14641664 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139717275 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 462450514 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13916 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837848883 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 85920553 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976355004 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26745374 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45156757 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125486 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1486003 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25049006 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985823032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128033727 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432836892 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 151 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310881003 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 157 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 151 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111429534 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542545285 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199304809 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26862690 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28866621 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947900293 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857514523 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13512332 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283868093 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647012526 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1540658157 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.205663 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150942 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310924087 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 156 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 148 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111428528 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542554069 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199305704 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26941972 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29270810 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947933260 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 215 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857474146 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13497185 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283901059 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647116126 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1540592805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.205688 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150881 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 587771265 38.15% 38.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326011747 21.16% 59.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378176386 24.55% 83.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219651217 14.26% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29041357 1.88% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6185 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 587702275 38.15% 38.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325996808 21.16% 59.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378232244 24.55% 83.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219639231 14.26% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29016078 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6169 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1540658157 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1540592805 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166072420 40.95% 40.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2002 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191493456 47.22% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47936528 11.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166081126 41.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1996 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191505284 47.27% 88.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47530605 11.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138226056 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801017 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138242397 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801060 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -567,90 +567,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 32 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532163815 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186323583 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532116023 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186314612 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857514523 # Type of FU issued -system.cpu.iq.rate 1.205602 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405504406 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218305 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5674703700 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231781287 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805692489 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 241 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 71 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2263018794 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17823551 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857474146 # Type of FU issued +system.cpu.iq.rate 1.205625 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405119011 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218102 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5674157044 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231847189 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805703414 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 266 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262593018 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17811740 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84238951 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66626 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13177 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24457764 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84247735 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66708 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13149 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24458659 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4548930 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4887285 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4504401 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4884981 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14641600 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25334604 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1297189 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947900591 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14641664 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25329983 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1325123 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947933556 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542545285 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199304809 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 154 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159299 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1136868 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13177 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7700706 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8703944 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16404650 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827845280 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516985272 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29669243 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542554069 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199305704 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 153 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159005 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1165002 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13149 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7699177 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8705456 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16404633 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827812064 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516937908 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29662082 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 82 # number of nop insts executed -system.cpu.iew.exec_refs 698740184 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542491 # Number of branches executed -system.cpu.iew.exec_stores 181754912 # Number of stores executed -system.cpu.iew.exec_rate 1.186345 # Inst execution rate -system.cpu.iew.wb_sent 1808718850 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805692560 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169243952 # num instructions producing a value -system.cpu.iew.wb_consumers 1689620594 # num instructions consuming a value +system.cpu.iew.exec_nop 81 # number of nop insts executed +system.cpu.iew.exec_refs 698690935 # number of memory reference insts executed +system.cpu.iew.exec_branches 229542500 # Number of branches executed +system.cpu.iew.exec_stores 181753027 # Number of stores executed +system.cpu.iew.exec_rate 1.186373 # Inst execution rate +system.cpu.iew.wb_sent 1808734068 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805703486 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169239698 # num instructions producing a value +system.cpu.iew.wb_consumers 1689624086 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.171967 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692016 # average fanout of values written-back +system.cpu.iew.wb_rate 1.172023 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692012 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 257974948 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 258007667 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14629278 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1501179372 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.108483 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.025812 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14629355 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1501111622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.108533 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.025633 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 920919616 61.35% 61.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250623048 16.70% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110074231 7.33% 85.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55314266 3.68% 89.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29240414 1.95% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34051194 2.27% 93.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24724968 1.65% 94.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18102388 1.21% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58129247 3.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 920819202 61.34% 61.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250634053 16.70% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110061016 7.33% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55281373 3.68% 89.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29321487 1.95% 91.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34081425 2.27% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24716781 1.65% 94.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18131809 1.21% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58064476 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1501179372 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1501111622 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -696,76 +696,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58129247 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3365056908 # The number of ROB reads -system.cpu.rob.rob_writes 3883498749 # The number of ROB writes -system.cpu.timesIdled 826 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 78120 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58064476 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3365086648 # The number of ROB reads +system.cpu.rob.rob_writes 3883566462 # The number of ROB writes +system.cpu.timesIdled 859 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79817 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.997522 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.997522 # CPI: Total CPI of All Threads -system.cpu.ipc 1.002484 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.002484 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175832090 # number of integer regfile reads -system.cpu.int_regfile_writes 1261554579 # number of integer regfile writes -system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.fp_regfile_writes 53 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965806989 # number of cc regfile reads -system.cpu.cc_regfile_writes 551858746 # number of cc regfile writes -system.cpu.misc_regfile_reads 675847493 # number of misc regfile reads +system.cpu.cpi 0.997481 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.997481 # CPI: Total CPI of All Threads +system.cpu.ipc 1.002525 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.002525 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175803949 # number of integer regfile reads +system.cpu.int_regfile_writes 1261568723 # number of integer regfile writes +system.cpu.fp_regfile_reads 40 # number of floating regfile reads +system.cpu.fp_regfile_writes 54 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965710140 # number of cc regfile reads +system.cpu.cc_regfile_writes 551865181 # number of cc regfile writes +system.cpu.misc_regfile_reads 675846539 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17004655 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964606 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638048144 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17005167 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.520840 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 78823500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964606 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17004606 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964973 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638063275 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17005118 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.521838 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 77839500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964973 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 419 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 420 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335675523 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335675523 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469328921 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469328921 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168719105 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168719105 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335698850 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335698850 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469343498 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469343498 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168719659 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168719659 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638048026 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638048026 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638048026 # number of overall hits -system.cpu.dcache.overall_hits::total 638048026 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17420086 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17420086 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3866942 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3866942 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638063157 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638063157 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638063157 # number of overall hits +system.cpu.dcache.overall_hits::total 638063157 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17417197 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17417197 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3866388 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3866388 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21287028 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21287028 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21287030 # number of overall misses -system.cpu.dcache.overall_misses::total 21287030 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 415615381500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 415615381500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149888945711 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149888945711 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 398000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 398000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 565504327211 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 565504327211 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 565504327211 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 565504327211 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486749007 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486749007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21283585 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21283585 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21283587 # number of overall misses +system.cpu.dcache.overall_misses::total 21283587 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 415522893500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 415522893500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149855935942 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149855935942 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 216000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 565378829442 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 565378829442 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 565378829442 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 565378829442 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486760695 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486760695 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -774,74 +774,74 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659335054 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659335054 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659335056 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659335056 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035789 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035789 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022406 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022406 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659346742 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659346742 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659346744 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659346744 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035782 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035782 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022403 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022403 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23858.400096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23858.400096 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38761.622417 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38761.622417 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26565.677802 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26565.677802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26565.675306 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26565.675306 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20779473 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3451346 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 944816 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67198 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.993143 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51.360844 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032280 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032280 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032280 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032280 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23857.047348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23857.047348 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38758.638797 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38758.638797 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26564.078817 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26564.078817 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26564.076320 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26564.076320 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20755892 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3446894 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 946527 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67143 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.928473 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51.336610 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4837348 # number of writebacks -system.cpu.dcache.writebacks::total 4837348 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3152457 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3152457 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1129405 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4835415 # number of writebacks +system.cpu.dcache.writebacks::total 4835415 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3149636 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3149636 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1128832 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1128832 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4281862 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4281862 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4281862 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4281862 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267629 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14267629 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737537 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737537 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4278468 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4278468 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4278468 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4278468 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267561 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14267561 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737556 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737556 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17005166 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17005166 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17005167 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17005167 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335438494000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 335438494000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116411117573 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116411117573 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17005117 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17005117 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17005118 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17005118 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335383172000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 335383172000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116381847286 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116381847286 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451849611573 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 451849611573 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451849679573 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 451849679573 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029312 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029312 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451765019286 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 451765019286 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451765087286 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 451765087286 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029311 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses @@ -850,361 +850,364 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025791 system.cpu.dcache.demand_mshr_miss_rate::total 0.025791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23510.458115 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23510.458115 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42524.034405 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42524.034405 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23506.692700 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23506.692700 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42513.047144 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42513.047144 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26571.314363 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26571.314363 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26571.316799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26571.316799 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26566.416408 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26566.416408 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26566.418844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26566.418844 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 582 # number of replacements -system.cpu.icache.tags.tagsinuse 445.815002 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656920172 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1070 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 613944.085981 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 592 # number of replacements +system.cpu.icache.tags.tagsinuse 446.127099 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656939322 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1080 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 608277.150000 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 445.815002 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.870732 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.870732 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 446.127099 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.871342 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.871342 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313844660 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313844660 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656920172 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656920172 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656920172 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656920172 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656920172 # number of overall hits -system.cpu.icache.overall_hits::total 656920172 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1623 # 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number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76771987 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 76771987 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76771987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 76771987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76771987 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 76771987 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70737.839252 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70737.839252 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70737.839252 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70737.839252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70737.839252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70737.839252 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71085.173148 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71085.173148 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71085.173148 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71085.173148 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71085.173148 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71085.173148 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 11618797 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11638031 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 14266 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 11620529 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11640215 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 14721 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3341.064863 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.319243 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001141 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.460185 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.203922 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.984492 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 811 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 615 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 195 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 503 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2303 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9259 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1857 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.049500 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.922607 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 551304223 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 551304223 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 4837348 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 4837348 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1752512 # 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average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72311.770428 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89715.963671 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89711.218265 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72311.770428 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89715.963671 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89711.218265 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 552 # number of cycles access was blocked +system.cpu.l2cache.prefetcher.pfSpanPage 4656609 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 4712362 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16129.977996 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 27367770 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4728288 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 5.788093 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 29479829000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 5227.936161 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.488571 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7534.908085 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3348.645178 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.319088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001128 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.459894 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.204385 # 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mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.218695 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.277745 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72631.323770 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72631.323770 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95406.487057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95406.487057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66311.770428 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66311.770428 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79944.046391 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79944.046391 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66311.770428 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84021.520924 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84016.629278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66311.770428 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84021.520924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72631.323770 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81602.334417 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.277660 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72781.087835 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95408.043397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95408.043397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66550.529355 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66550.529355 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79942.612843 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79942.612843 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66550.529355 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84020.103572 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84015.224275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66550.529355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84020.103572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81631.427256 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 14268653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 6475946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 15220389 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1280497 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1070 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267583 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993396 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50996114 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397921024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1397989504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 5993194 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 40004669 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.149812 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.356887 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 34011398 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17005208 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21592 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 111772 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 111653 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 14268599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 6472980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 15222988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1281199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1080 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267519 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2748 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50996002 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397794112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1397863232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 5993561 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 40004959 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.003877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.062190 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 34011476 85.02% 85.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 5993193 14.98% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 39849994 99.61% 99.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 154846 0.39% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 119 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 40004669 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 21843087497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 40004959 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21841114998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1605000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1620000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25507754991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25507681990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3739456 # Transaction distribution -system.membus.trans_dist::Writeback 1638598 # Transaction distribution -system.membus.trans_dist::CleanEvict 3064906 # Transaction distribution -system.membus.trans_dist::ReadExReq 981345 # Transaction distribution -system.membus.trans_dist::ReadExResp 981345 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3739456 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14145106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14145106 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407001536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 407001536 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3739654 # Transaction distribution +system.membus.trans_dist::Writeback 1637565 # Transaction distribution +system.membus.trans_dist::CleanEvict 3065415 # Transaction distribution +system.membus.trans_dist::ReadExReq 980644 # Transaction distribution +system.membus.trans_dist::ReadExResp 980644 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3739654 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14143576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14143576 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406903232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 406903232 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9424305 # Request fanout histogram +system.membus.snoop_fanout::samples 9423278 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9424305 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9423278 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9424305 # Request fanout histogram -system.membus.reqLayer0.occupancy 17323735553 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9423278 # Request fanout histogram +system.membus.reqLayer0.occupancy 17318873513 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25676323677 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25673835894 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 939603453..3fad64f8d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.363367 # Number of seconds simulated -sim_ticks 2363367211500 # Number of ticks simulated -final_tick 2363367211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.363368 # Number of seconds simulated +sim_ticks 2363368369500 # Number of ticks simulated +final_tick 2363368369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1091670 # Simulator instruction rate (inst/s) -host_op_rate 1176427 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1676685643 # Simulator tick rate (ticks/s) -host_mem_usage 312924 # Number of bytes of host memory used -host_seconds 1409.55 # Real time elapsed on the host +host_inst_rate 1008024 # Simulator instruction rate (inst/s) +host_op_rate 1086287 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1548215415 # Simulator tick rate (ticks/s) +host_mem_usage 315828 # Number of bytes of host memory used +host_seconds 1526.51 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,16 +26,16 @@ system.physmem.num_reads::total 1951712 # Nu system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 16681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52835693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52852374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52835667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52852348 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 16681 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 16681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27652126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27652126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27652126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 27652112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27652112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27652112 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 16681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52835693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80504500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52835667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80504461 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4726734423 # number of cpu cycles simulated +system.cpu.numCycles 4726736739 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759602 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4726734422.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4726736738.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462427 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.732137 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.732103 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164659500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732137 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 25164683500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732103 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143051795500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143051795500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143052931500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143052931500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 57408921000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 57408921000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200460716500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200460716500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200460716500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200460716500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200461852500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200461852500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200461852500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200461852500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.580818 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.580818 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.738027 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.738027 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.773464 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.773464 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.831971 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21991.831971 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.829559 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21991.829559 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.956598 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21991.956598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.954185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21991.954185 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135825709500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 135825709500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135826845500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 135826845500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55519772000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 55519772000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191345481500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191345481500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191345535500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191345535500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191346617500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191346617500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191346671500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191346671500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.580818 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.580818 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.738027 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.738027 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.773464 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.773464 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.831971 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.831971 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.835593 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.835593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.956598 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.956598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.960219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.960219 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.003161 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.003151 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.003161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 515.003151 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.251466 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.251466 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id @@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34212000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34212000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34212000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34212000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34212000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34212000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34234000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34234000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34234000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34234000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34234000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34234000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses @@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53623.824451 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53623.824451 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53623.824451 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53623.824451 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53658.307210 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53658.307210 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53658.307210 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53658.307210 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -411,34 +411,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33574000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33574000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33574000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33574000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33574000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33574000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33596000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33596000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33596000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33596000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33596000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33596000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52623.824451 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52623.824451 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52658.307210 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52658.307210 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1919018 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31008.198929 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31008.199290 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14386233 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1948786 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 7.382151 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 150067845000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15515.969324 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734669 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494937 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 150067869000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15515.970631 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734659 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494001 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.473510 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000724 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.472061 # Average percentage of cache occupancy @@ -482,14 +482,14 @@ system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41062370000 system.cpu.l2cache.ReadExReq_miss_latency::total 41062370000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 32383000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 32383000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386841500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386841500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386933500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386933500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 32383000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 102449211500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 102481594500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102449303500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102481686500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 32383000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 102449211500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 102481594500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102449303500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102481686500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 3681379 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3681379 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) @@ -520,14 +520,14 @@ system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.562565 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.562565 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52569.805195 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52569.805195 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.885372 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.885372 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.964074 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.964074 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52508.564020 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52508.611158 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52508.564020 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52508.611158 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -556,14 +556,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33241050000 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33241050000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26223000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26223000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697201500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697201500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697293500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697293500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26223000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938251500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 82964474500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938343500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 82964566500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26223000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938251500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 82964474500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938343500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 82964566500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414013 # mshr miss rate for ReadExReq accesses @@ -582,15 +582,21 @@ system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.562565 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.562565 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42569.805195 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42569.805195 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.885372 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.885372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.964074 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.964074 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4702506 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6326508 # Transaction distribution @@ -606,15 +612,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 819024192 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1919018 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20146039 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095255 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293567 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18227021 90.47% 90.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1919018 9.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20142667 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3372 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20146039 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12794889500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 6d8265542..c34bcec93 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.882285 # Nu sim_ticks 5882284743500 # Number of ticks simulated final_tick 5882284743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 724530 # Simulator instruction rate (inst/s) -host_op_rate 1128884 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1416814365 # Simulator tick rate (ticks/s) -host_mem_usage 314268 # Number of bytes of host memory used -host_seconds 4151.77 # Real time elapsed on the host +host_inst_rate 704974 # Simulator instruction rate (inst/s) +host_op_rate 1098413 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1378571885 # Simulator tick rate (ticks/s) +host_mem_usage 317252 # Number of bytes of host memory used +host_seconds 4266.94 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42523.703704 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4705009 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6322744 # Transaction distribution @@ -464,15 +470,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 818948672 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1919162 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20141105 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095286 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293609 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000050 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.007053 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18221943 90.47% 90.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1919162 9.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20140103 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1002 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20141105 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12793692500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |