diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
3 files changed, 1899 insertions, 1423 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 0c8fe7df6..77212a74e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,217 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.983203 # Number of seconds simulated -sim_ticks 983202553500 # Number of ticks simulated -final_tick 983202553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.998096 # Number of seconds simulated +sim_ticks 998095972500 # Number of ticks simulated +final_tick 998095972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119503 # Simulator instruction rate (inst/s) -host_op_rate 119503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64565869 # Simulator tick rate (ticks/s) -host_mem_usage 212872 # Number of bytes of host memory used -host_seconds 15227.90 # Real time elapsed on the host +host_inst_rate 135518 # Simulator instruction rate (inst/s) +host_op_rate 135518 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74327611 # Simulator tick rate (ticks/s) +host_mem_usage 465236 # Number of bytes of host memory used +host_seconds 13428.33 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137579776 # Number of bytes read from this memory -system.physmem.bytes_read::total 137634752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137579264 # Number of bytes read from this memory +system.physmem.bytes_read::total 137634240 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory -system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67104640 # Number of bytes written to this memory +system.physmem.bytes_written::total 67104640 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2149684 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2150543 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 139930247 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139986162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55915 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55915 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 68251540 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 68251540 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 68251540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 139930247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 208237702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 2149676 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2150535 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048510 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048510 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 137841718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 137896799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55081 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55081 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 67232653 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 67232653 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 67232653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 137841718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 205129452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2150535 # Total number of read requests seen +system.physmem.writeReqs 1048510 # Total number of write requests seen +system.physmem.cpureqs 3199045 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 137634240 # Total number of bytes read from memory +system.physmem.bytesWritten 67104640 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 137634240 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67104640 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1104 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 134750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 134519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 135461 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 133443 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 134821 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 134519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 135107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 134152 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 133438 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 134313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 134956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 130690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 131784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 134689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 137104 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 135685 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 65615 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 65313 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 65943 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 64961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 65149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 64711 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 65179 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 65010 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 64600 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 65119 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 65708 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64486 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 65220 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 66941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 67682 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 66873 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 998095934500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 2150535 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 1048510 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 1835130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 153641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 24246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 14808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 43501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 45551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 45580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 45588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 45587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 19730119710 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 92821713710 # Sum of mem lat for all requests +system.physmem.totBusLat 8597724000 # Total cycles spent in databus access +system.physmem.totBankLat 64493870000 # Total cycles spent in bank access +system.physmem.avgQLat 9179.23 # Average queueing delay per request +system.physmem.avgBankLat 30005.09 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 43184.32 # Average memory access latency +system.physmem.avgRdBW 137.90 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 67.23 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 137.90 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 67.23 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 1.28 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.09 # Average read queue length over time +system.physmem.avgWrQLen 11.29 # Average write queue length over time +system.physmem.readRowHits 884898 # Number of row buffer hits during reads +system.physmem.writeRowHits 338451 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.28 # Row buffer hit rate for writes +system.physmem.avgGap 311998.09 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444615529 # DTB read hits +system.cpu.dtb.read_hits 444628016 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449512607 # DTB read accesses -system.cpu.dtb.write_hits 160920414 # DTB write hits +system.cpu.dtb.read_accesses 449525094 # DTB read accesses +system.cpu.dtb.write_hits 160917908 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162621718 # DTB write accesses -system.cpu.dtb.data_hits 605535943 # DTB hits +system.cpu.dtb.write_accesses 162619212 # DTB write accesses +system.cpu.dtb.data_hits 605545924 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612134325 # DTB accesses -system.cpu.itb.fetch_hits 232170189 # ITB hits +system.cpu.dtb.data_accesses 612144306 # DTB accesses +system.cpu.itb.fetch_hits 232077768 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232170211 # ITB accesses +system.cpu.itb.fetch_accesses 232077790 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1966405108 # number of cpu cycles simulated +system.cpu.numCycles 1996191946 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328916467 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253806684 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140065896 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 232656738 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138122512 # Number of BTB hits +system.cpu.branch_predictor.lookups 328934492 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253834142 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140072594 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 232648931 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138176846 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.367510 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175157469 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153758998 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669786412 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.392857 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175181145 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153753347 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669765696 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045989029 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3045968313 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 650997764 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617989099 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121287494 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12179944 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133467438 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81732764 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.020127 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139628962 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651043890 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617989866 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121337623 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12136513 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133474136 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81726090 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.023232 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139616626 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746556255 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746553256 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7516835 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 389335212 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1577069896 # Number of cycles cpu stages are processed. -system.cpu.activity 80.200661 # Percentage of cycles cpu is active +system.cpu.timesIdled 7548952 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 419177402 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1577014544 # Number of cycles cpu stages are processed. +system.cpu.activity 79.001148 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -114,144 +272,144 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.080573 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.096941 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.080573 # CPI: Total CPI of All Threads -system.cpu.ipc 0.925435 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.096941 # CPI: Total CPI of All Threads +system.cpu.ipc 0.911626 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.925435 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 775560339 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190844769 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.559483 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1034052370 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932352738 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 47.414072 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 992429233 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973975875 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.530784 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1556696076 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409709032 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.835434 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 943449824 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022955284 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.021594 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.911626 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 805412484 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190779462 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.652553 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1063871870 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932320076 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.704931 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1022192992 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973998954 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.792851 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1586493403 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409698543 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.524005 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 973220385 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022971561 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.246152 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 666.559426 # Cycle average of tags in use -system.cpu.icache.total_refs 232169108 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 667.791202 # Cycle average of tags in use +system.cpu.icache.total_refs 232076694 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270278.356228 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270170.772992 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 666.559426 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325468 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325468 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232169108 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232169108 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232169108 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232169108 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232169108 # number of overall hits -system.cpu.icache.overall_hits::total 232169108 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1077 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1077 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1077 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1077 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1077 # number of overall misses -system.cpu.icache.overall_misses::total 1077 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58736500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58736500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58736500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58736500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58736500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58736500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232170185 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232170185 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232170185 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232170185 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232170185 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232170185 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 667.791202 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.326070 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.326070 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232076694 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232076694 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232076694 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232076694 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232076694 # number of overall hits +system.cpu.icache.overall_hits::total 232076694 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses +system.cpu.icache.overall_misses::total 1072 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56100000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56100000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56100000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56100000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56100000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56100000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232077766 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232077766 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232077766 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232077766 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232077766 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232077766 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54537.140204 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54537.140204 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54537.140204 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54537.140204 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52332.089552 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52332.089552 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52332.089552 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52332.089552 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52332.089552 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52332.089552 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 210 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 99 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 52.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 218 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 218 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 218 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 218 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 218 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 213 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 213 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 213 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47121000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47121000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47121000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47121000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47121000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47121000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45656000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45656000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45656000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45656000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45656000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45656000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54855.646100 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54855.646100 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.174622 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.174622 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.174622 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.174622 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.174622 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.174622 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107371 # number of replacements -system.cpu.dcache.tagsinuse 4082.143149 # Cycle average of tags in use -system.cpu.dcache.total_refs 595063275 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111467 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.309272 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12675157000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.143149 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996617 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996617 # Average percentage of cache occupancy +system.cpu.dcache.replacements 9107316 # number of replacements +system.cpu.dcache.tagsinuse 4082.375203 # Cycle average of tags in use +system.cpu.dcache.total_refs 595069266 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111412 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.310324 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12653266000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.375203 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996674 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996674 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437271434 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437271434 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157791841 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157791841 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595063275 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595063275 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595063275 # number of overall hits -system.cpu.dcache.overall_hits::total 595063275 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 157797832 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157797832 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595069266 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595069266 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595069266 # number of overall hits +system.cpu.dcache.overall_hits::total 595069266 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7324229 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7324229 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2936661 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2936661 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10260890 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10260890 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10260890 # number of overall misses -system.cpu.dcache.overall_misses::total 10260890 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 153812326500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 153812326500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 102755788500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 102755788500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 256568115000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 256568115000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 256568115000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 256568115000 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 2930670 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2930670 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10254899 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10254899 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10254899 # number of overall misses +system.cpu.dcache.overall_misses::total 10254899 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 169482879500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 169482879500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 114253006500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 114253006500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 283735886000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 283735886000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 283735886000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 283735886000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -262,54 +420,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.018271 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016951 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016951 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016951 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21000.480255 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21000.480255 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34990.687893 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34990.687893 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25004.469885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25004.469885 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 52857 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15792734 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4352 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 208446 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.145450 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 75.764150 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018234 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016941 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016941 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016941 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016941 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23140.030097 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23140.030097 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38985.285447 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38985.285447 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27668.325744 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27668.325744 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27668.325744 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27668.325744 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 791552 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 14185855 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 26512 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 205984 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.856367 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 68.868723 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389692 # number of writebacks -system.cpu.dcache.writebacks::total 3389692 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101949 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101949 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1047474 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1047474 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1149423 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1149423 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1149423 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1149423 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889187 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889187 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111467 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111467 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111467 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111467 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137359214000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 137359214000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55152222500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 55152222500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192511436500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 192511436500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 192511436500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 192511436500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3389638 # number of writebacks +system.cpu.dcache.writebacks::total 3389638 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101954 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101954 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1041533 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1041533 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1143487 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1143487 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1143487 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1143487 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222275 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222275 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889137 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889137 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111412 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111412 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111412 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111412 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 153198656000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 153198656000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69357589500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 69357589500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 222556245500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 222556245500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 222556245500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 222556245500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -318,149 +476,149 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19018.815942 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19018.815942 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29193.628000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29193.628000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21128.478707 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21128.478707 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21128.478707 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21128.478707 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21211.966589 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21211.966589 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36713.901374 # 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Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14439.033310 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.753993 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16055.786176 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440644 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001061 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.489984 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.931689 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5860987 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5860987 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3389692 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3389692 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1100796 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16152.444929 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.438705 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001042 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.492934 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.932680 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5860981 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5860981 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3389638 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3389638 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1100755 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1100755 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6961736 # 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number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111467 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112326 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111412 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112271 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111467 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112326 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111412 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112271 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188436 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.188532 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417454 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.417454 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417460 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.417460 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.235932 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.236004 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.235932 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.236004 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53849.243306 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52491.863915 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52492.720183 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53282.323382 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53282.323382 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52782.351713 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52782.351713 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1081 # number of cycles access was blocked +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52143.771828 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64128.858245 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 64121.297764 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71355.252249 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71355.252249 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52143.771828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66780.584842 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66774.738379 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52143.771828 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66780.584842 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66774.738379 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 438308 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 3445 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 25.738095 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 127.230189 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1048517 # number of writebacks -system.cpu.l2cache.writebacks::total 1048517 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1048510 # number of writebacks +system.cpu.l2cache.writebacks::total 1048510 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360851 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1361710 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788833 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 788833 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360852 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1361711 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788824 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 788824 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2149684 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2150543 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2149676 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2150535 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2149684 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2150543 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35788000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54811327000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54847115000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32423383500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32423383500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35788000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87234710500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 87270498500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35788000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87234710500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 87270498500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 2149676 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2150535 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33924935 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 69917631981 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 69951556916 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46302511646 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46302511646 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33924935 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116220143627 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 116254068562 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33924935 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116220143627 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 116254068562 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417454 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417454 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417460 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417460 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41662.398137 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40277.243431 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40278.117220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41102.975535 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41102.975535 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41662.398137 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40580.248306 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40580.680554 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41662.398137 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40580.248306 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40580.680554 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39493.521537 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51377.836812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51370.339900 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58698.152751 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58698.152751 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39493.521537 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54064.028080 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54058.208103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39493.521537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54064.028080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54058.208103 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index d7e4bc3be..4dd96e908 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,217 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.601742 # Number of seconds simulated -sim_ticks 601741522500 # Number of ticks simulated -final_tick 601741522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.622687 # Number of seconds simulated +sim_ticks 622686686500 # Number of ticks simulated +final_tick 622686686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165987 # Simulator instruction rate (inst/s) -host_op_rate 165987 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57533745 # Simulator tick rate (ticks/s) -host_mem_usage 213900 # Number of bytes of host memory used -host_seconds 10458.93 # Real time elapsed on the host +host_inst_rate 130099 # Simulator instruction rate (inst/s) +host_op_rate 130099 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46664017 # Simulator tick rate (ticks/s) +host_mem_usage 466244 # Number of bytes of host memory used +host_seconds 13344.04 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138172352 # Number of bytes read from this memory -system.physmem.bytes_read::total 138234112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67207424 # Number of bytes written to this memory -system.physmem.bytes_written::total 67207424 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2158943 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2159908 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050116 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050116 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 102635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 229620770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 229723406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 102635 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 102635 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 111688194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 111688194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 111688194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 102635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 229620770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 341411600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138173120 # Number of bytes read from this memory +system.physmem.bytes_read::total 138234624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67206720 # Number of bytes written to this memory +system.physmem.bytes_written::total 67206720 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2158955 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2159916 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050105 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050105 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 98772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 221898305 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 221997077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 98772 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 98772 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 107930234 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 107930234 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 107930234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 98772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 221898305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 329927311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2159916 # Total number of read requests seen +system.physmem.writeReqs 1050105 # Total number of write requests seen +system.physmem.cpureqs 3210021 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 138234624 # Total number of bytes read from memory +system.physmem.bytesWritten 67206720 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 138234624 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67206720 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1101 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 135516 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 134944 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 135958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 133984 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 135382 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 135012 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 135645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 134678 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 134063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 135260 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 135483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 131205 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 132348 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 135290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 137712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 136335 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 65727 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 65366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 66027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 65044 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 65255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 64804 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 65281 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 65090 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 64712 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 65264 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 65787 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64601 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 65333 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 67038 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 67805 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 66971 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 622686634000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 2159916 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 1050105 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 1715217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 265103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 37466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 21744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 13852 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 9060 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 6661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 42630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 45641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 45652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 45656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 45657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 45657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 45657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 45657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 45657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 45656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 45656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 45656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 45656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 45656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 45656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 22793561782 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 94682781782 # Sum of mem lat for all requests +system.physmem.totBusLat 8635260000 # Total cycles spent in databus access +system.physmem.totBankLat 63253960000 # Total cycles spent in bank access +system.physmem.avgQLat 10558.37 # Average queueing delay per request +system.physmem.avgBankLat 29300.32 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 43858.68 # Average memory access latency +system.physmem.avgRdBW 222.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 107.93 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 222.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 107.93 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.06 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 10.91 # Average write queue length over time +system.physmem.readRowHits 893342 # Number of row buffer hits during reads +system.physmem.writeRowHits 340237 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.40 # Row buffer hit rate for writes +system.physmem.avgGap 193982.11 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 610863506 # DTB read hits -system.cpu.dtb.read_misses 10801691 # DTB read misses +system.cpu.dtb.read_hits 610476386 # DTB read hits +system.cpu.dtb.read_misses 10761875 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 621665197 # DTB read accesses -system.cpu.dtb.write_hits 207455295 # DTB write hits -system.cpu.dtb.write_misses 6623437 # DTB write misses +system.cpu.dtb.read_accesses 621238261 # DTB read accesses +system.cpu.dtb.write_hits 207269464 # DTB write hits +system.cpu.dtb.write_misses 6561537 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 214078732 # DTB write accesses -system.cpu.dtb.data_hits 818318801 # DTB hits -system.cpu.dtb.data_misses 17425128 # DTB misses +system.cpu.dtb.write_accesses 213831001 # DTB write accesses +system.cpu.dtb.data_hits 817745850 # DTB hits +system.cpu.dtb.data_misses 17323412 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 835743929 # DTB accesses -system.cpu.itb.fetch_hits 399244233 # ITB hits -system.cpu.itb.fetch_misses 57 # ITB misses +system.cpu.dtb.data_accesses 835069262 # DTB accesses +system.cpu.itb.fetch_hits 398378101 # ITB hits +system.cpu.itb.fetch_misses 55 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 399244290 # ITB accesses +system.cpu.itb.fetch_accesses 398378156 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,145 +225,145 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1203483046 # number of cpu cycles simulated +system.cpu.numCycles 1245373374 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 378630674 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 290853975 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18842896 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 264245889 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 260518236 # Number of BTB hits +system.cpu.BPredUnit.lookups 378146140 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 290510585 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18737073 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 264395160 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 259999350 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25134989 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6201 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 410689836 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3138690905 # Number of instructions fetch has processed -system.cpu.fetch.Branches 378630674 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 285653225 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 572677806 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 132533954 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 108403122 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1285 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 399244233 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10255002 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1198760050 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.618281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.169328 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25131917 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6182 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 409812987 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3135210650 # Number of instructions fetch has processed +system.cpu.fetch.Branches 378146140 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 285131267 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 571966611 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 132239561 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 126137605 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1394 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 398378101 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10155921 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1214707352 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.581042 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.162326 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 626082244 52.23% 52.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42560367 3.55% 55.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22212227 1.85% 57.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40796625 3.40% 61.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 126320083 10.54% 71.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63645436 5.31% 76.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40565089 3.38% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30205669 2.52% 82.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 206372310 17.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 642740741 52.91% 52.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42508733 3.50% 56.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22198972 1.83% 58.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40683898 3.35% 61.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 126205169 10.39% 71.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63532228 5.23% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40428272 3.33% 80.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30073881 2.48% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 206335458 16.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1198760050 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.314612 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.608006 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438814843 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95153182 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542714056 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15090918 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 106987051 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60150241 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1010 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3059802509 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2177 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 106987051 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 459387866 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50448288 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 536142849 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45788849 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2978016816 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 421943 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1715322 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 41464029 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2227365150 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3845813324 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3844419965 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1393359 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1214707352 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.303641 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.517486 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 437634335 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 113109865 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542282236 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 14893078 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 106787838 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60009942 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1008 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3056719356 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2151 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 106787838 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 458205445 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 68879857 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5925 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535635557 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45192730 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2974950452 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 455085 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1725044 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40939895 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2225174239 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3842201349 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3840803931 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1397418 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 851162187 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 215 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 214 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 95471202 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 674494217 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 250159031 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59771171 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 34263403 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2674166611 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 189 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2477607357 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3173205 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 927397839 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 394299937 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 160 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1198760050 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.066808 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.969624 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 848971276 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 208 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 208 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 94220163 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 674209051 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 250003668 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 60248313 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34574137 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2672716058 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2475684354 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3185220 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 926051369 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 394490469 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1214707352 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.038091 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971432 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 374466356 31.24% 31.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 190640446 15.90% 47.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 181417957 15.13% 62.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153622544 12.82% 75.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 136730069 11.41% 86.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80254846 6.69% 93.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 61695164 5.15% 98.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14563469 1.21% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5369199 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 391612222 32.24% 32.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 190116739 15.65% 47.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 180710183 14.88% 62.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153608021 12.65% 75.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 136709031 11.25% 86.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80377873 6.62% 93.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 61799975 5.09% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14388617 1.18% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5384691 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1198760050 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1214707352 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2251857 11.87% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12201284 64.32% 76.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4515049 23.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2236018 11.81% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12183595 64.36% 76.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4510642 23.83% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1617068630 65.27% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1615926808 65.27% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 102 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 297 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 171 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 41 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.27% # Type of FU issued @@ -228,84 +386,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.27% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 639258763 25.80% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 221279320 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 638812583 25.80% 91.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 220944337 8.92% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2477607357 # Type of FU issued -system.cpu.iq.rate 2.058697 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18968190 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007656 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6174132781 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3600319262 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2375945234 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1983378 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1347629 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 869060 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2495600765 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 974782 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 56278777 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2475684354 # Type of FU issued +system.cpu.iq.rate 1.987905 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18930255 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007646 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6186206687 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3597520072 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2374361589 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1984848 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1351695 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 870010 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2493639169 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 975440 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 56324993 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 229898554 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 250139 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 103830 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 89430529 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 229613388 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 251555 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 105716 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 89275166 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 234 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 81236 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 232 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 90239 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 106987051 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18488263 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 963433 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2816062244 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17529415 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 674494217 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 250159031 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 189 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 221508 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12923 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 103830 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13260228 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8848776 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22109004 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2426798028 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 621666775 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 50809329 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 106787838 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30509174 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1004696 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2814392916 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16951249 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 674209051 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 250003668 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 211284 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14280 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 105716 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13148912 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8849149 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 21998061 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2424970447 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 621239857 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 50713907 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 141895444 # number of nop insts executed -system.cpu.iew.exec_refs 835745555 # number of memory reference insts executed -system.cpu.iew.exec_branches 297016780 # Number of branches executed -system.cpu.iew.exec_stores 214078780 # Number of stores executed -system.cpu.iew.exec_rate 2.016479 # Inst execution rate -system.cpu.iew.wb_sent 2405369179 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2376814294 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1361493757 # num instructions producing a value -system.cpu.iew.wb_consumers 1724612513 # num instructions consuming a value +system.cpu.iew.exec_nop 141676677 # number of nop insts executed +system.cpu.iew.exec_refs 835070896 # number of memory reference insts executed +system.cpu.iew.exec_branches 296780799 # Number of branches executed +system.cpu.iew.exec_stores 213831039 # Number of stores executed +system.cpu.iew.exec_rate 1.947183 # Inst execution rate +system.cpu.iew.wb_sent 2403689836 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2375231599 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1360982490 # num instructions producing a value +system.cpu.iew.wb_consumers 1724379175 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.974946 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789449 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907245 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789259 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 756436478 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 754743358 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18841975 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1091772999 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.666812 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.514787 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 18736187 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1107919514 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.642520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.504559 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 565636558 51.81% 51.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181878211 16.66% 68.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 91372107 8.37% 76.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53285897 4.88% 81.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36714852 3.36% 85.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28908245 2.65% 87.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22459323 2.06% 89.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22999009 2.11% 91.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 88518797 8.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 582245438 52.55% 52.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 181606604 16.39% 68.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90875132 8.20% 77.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53034266 4.79% 81.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36917610 3.33% 85.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 29689254 2.68% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22142026 2.00% 89.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22921878 2.07% 92.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 88487306 7.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1091772999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1107919514 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +474,70 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 88518797 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 88487306 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3493691606 # The number of ROB reads -system.cpu.rob.rob_writes 5259524652 # The number of ROB writes -system.cpu.timesIdled 273067 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4722996 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3508176492 # The number of ROB reads +system.cpu.rob.rob_writes 5255937619 # The number of ROB writes +system.cpu.timesIdled 768601 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30666022 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.693233 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.693233 # CPI: Total CPI of All Threads -system.cpu.ipc 1.442516 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.442516 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3262496367 # number of integer regfile reads -system.cpu.int_regfile_writes 1906751993 # number of integer regfile writes -system.cpu.fp_regfile_reads 51073 # number of floating regfile reads -system.cpu.fp_regfile_writes 575 # number of floating regfile writes +system.cpu.cpi 0.717363 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.717363 # CPI: Total CPI of All Threads +system.cpu.ipc 1.393995 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.393995 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3260141632 # number of integer regfile reads +system.cpu.int_regfile_writes 1905484731 # number of integer regfile writes +system.cpu.fp_regfile_reads 51179 # number of floating regfile reads +system.cpu.fp_regfile_writes 563 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 769.815211 # Cycle average of tags in use -system.cpu.icache.total_refs 399242763 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 965 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 413723.070466 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 770.400860 # Cycle average of tags in use +system.cpu.icache.total_refs 398376643 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 414543.853278 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 769.815211 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.375886 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.375886 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 399242763 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 399242763 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 399242763 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 399242763 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 399242763 # number of overall hits -system.cpu.icache.overall_hits::total 399242763 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1470 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1470 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1470 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1470 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1470 # number of overall misses -system.cpu.icache.overall_misses::total 1470 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50742000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50742000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50742000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50742000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50742000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50742000 # 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number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 398376643 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 398376643 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 398376643 # number of overall hits +system.cpu.icache.overall_hits::total 398376643 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1458 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1458 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1458 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1458 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1458 # number of overall misses +system.cpu.icache.overall_misses::total 1458 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 53978500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 53978500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 53978500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 53978500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 53978500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 53978500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 398378101 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 398378101 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 398378101 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 398378101 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 398378101 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 398378101 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34518.367347 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34518.367347 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34518.367347 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34518.367347 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34518.367347 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34518.367347 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37022.290809 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37022.290809 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37022.290809 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37022.290809 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37022.290809 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37022.290809 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,299 +546,301 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36236500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36236500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36236500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36236500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36236500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36236500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 497 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 497 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 497 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 497 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 497 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 497 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 961 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 961 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 961 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37991000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37991000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37991000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37991000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37991000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37991000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37550.777202 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37550.777202 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37550.777202 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37550.777202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37550.777202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37550.777202 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39532.778356 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39532.778356 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39532.778356 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39532.778356 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39532.778356 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39532.778356 # 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number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155839486 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 700520055 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 700520055 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 700520055 # number of overall hits -system.cpu.dcache.overall_hits::total 700520055 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9891173 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9891173 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4889016 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4889016 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # 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Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997690 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997690 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 544376569 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 544376569 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156015231 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156015231 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 700391800 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 700391800 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 700391800 # number of overall hits +system.cpu.dcache.overall_hits::total 700391800 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9752930 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9752930 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4713271 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4713271 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 14466201 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 14466201 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 14466201 # number of overall misses +system.cpu.dcache.overall_misses::total 14466201 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 164485394500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 164485394500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 131300824319 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 131300824319 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 62500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 62500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 295786218819 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 295786218819 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 295786218819 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 295786218819 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 554129499 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 554129499 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 715300244 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 715300244 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 715300244 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 715300244 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017836 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017836 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030418 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.030418 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.020663 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.020663 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.020663 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.020663 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13685.593003 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13685.593003 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26280.760054 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26280.760054 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 42500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 42500 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 8 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 714858001 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 714858001 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 714858001 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 714858001 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017600 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017600 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029324 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029324 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.020236 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.020236 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.020236 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.020236 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16865.228654 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16865.228654 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27857.686163 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27857.686163 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20446.710150 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20446.710150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20446.710150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20446.710150 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 200506 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3116753 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 10498 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65116 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.099448 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 47.864626 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3416489 # number of writebacks -system.cpu.dcache.writebacks::total 3416489 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2594561 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2594561 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3005264 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3005264 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5599825 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5599825 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5599825 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5599825 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296612 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296612 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883752 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883752 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3416510 # number of writebacks +system.cpu.dcache.writebacks::total 3416510 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2456183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2456183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2829474 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2829474 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 5285657 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5285657 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5285657 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 63655163500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 32590773423 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 32590773423 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 40500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 40500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96245936923 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 96245936923 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96245936923 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 96245936923 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013157 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180544 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180544 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180544 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180544 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 83795715500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 83795715500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 42424545344 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 42424545344 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 28500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 28500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126220260844 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126220260844 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126220260844 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126220260844 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013168 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013168 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012834 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012834 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012834 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012834 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8723.934273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8723.934273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17300.989421 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17300.989421 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 40500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 40500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10483.891153 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10483.891153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10483.891153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10483.891153 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.125000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.125000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012842 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012842 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36332.202112 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36539.378238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36332.109509 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36332.202112 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 47300 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.235166 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.235246 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 38526.014568 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50677.063990 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50668.586142 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49614.172001 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49614.172001 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 38526.014568 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50291.804137 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50286.569246 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38526.014568 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50291.804137 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50286.569246 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 138175 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 3906 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 4214 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 12.109575 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 32.789511 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050116 # number of writebacks -system.cpu.l2cache.writebacks::total 1050116 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376432 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1377397 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782511 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 64739404387 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36015294954 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36015294954 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33564956 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 100721134385 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 100754699341 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33564956 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 100721134385 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 100754699341 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188640 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188747 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415398 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415398 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188634 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188741 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415406 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415406 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235170 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235250 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235166 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.235246 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235170 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235250 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33372.020725 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32733.649392 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32734.096633 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33823.259993 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33823.259993 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33372.020725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33128.579819 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33128.688583 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33372.020725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33128.579819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33128.688583 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235166 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.235246 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34927.113424 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47010.516786 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 47002.086136 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46023.406962 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46023.406962 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34927.113424 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46652.725224 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 46647.508209 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34927.113424 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46652.725224 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46647.508209 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 2519af40e..a3e0cc680 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,197 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.454149 # Number of seconds simulated -sim_ticks 454149445000 # Number of ticks simulated -final_tick 454149445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.473434 # Number of seconds simulated +sim_ticks 473433799500 # Number of ticks simulated +final_tick 473433799500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 251011 # Simulator instruction rate (inst/s) -host_op_rate 280022 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73805166 # Simulator tick rate (ticks/s) -host_mem_usage 228580 # Number of bytes of host memory used -host_seconds 6153.36 # Real time elapsed on the host -sim_insts 1544563043 # Number of instructions simulated -sim_ops 1723073855 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156265984 # Number of bytes read from this memory -system.physmem.bytes_read::total 156314240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71930048 # Number of bytes written to this memory -system.physmem.bytes_written::total 71930048 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2441656 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2442410 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1123907 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1123907 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 344084939 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 344191195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 106256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 106256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 158384093 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 158384093 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 158384093 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 344084939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 502575288 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 169995 # Simulator instruction rate (inst/s) +host_op_rate 189642 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52106394 # Simulator tick rate (ticks/s) +host_mem_usage 499160 # Number of bytes of host memory used +host_seconds 9085.91 # Real time elapsed on the host +sim_insts 1544563083 # Number of instructions simulated +sim_ops 1723073895 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156296704 # Number of bytes read from this memory +system.physmem.bytes_read::total 156345088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71931712 # Number of bytes written to this memory +system.physmem.bytes_written::total 71931712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2442136 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2442892 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1123933 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1123933 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 102198 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330134232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 330236430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 102198 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 102198 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 151936157 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 151936157 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 151936157 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 102198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330134232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 482172587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2442892 # Total number of read requests seen +system.physmem.writeReqs 1123933 # Total number of write requests seen +system.physmem.cpureqs 3566825 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 156345088 # Total number of bytes read from memory +system.physmem.bytesWritten 71931712 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 156345088 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 71931712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1286 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 151934 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 156031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 154856 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 153024 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 150249 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 152372 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 153472 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 154746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 153379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 151879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 152199 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 152305 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 150118 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 153271 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 150713 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 151058 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 70393 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 72288 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 71658 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 69978 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 69490 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 69799 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 70024 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 70449 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 69754 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 69615 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 69971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 69698 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 68976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 71736 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 70217 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69887 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 473433771000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 2442892 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 1123933 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 1613567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 411043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 122672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 76227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 63723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 50754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 36534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 28949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 23035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 15102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 43358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 46512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 48422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 48759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 48833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 48858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 48865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 48866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 48867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 48867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 48867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 48867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 48867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 48867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 48866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 48866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 48866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 48866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 48866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 48866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 48866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 39045821973 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 121584903973 # Sum of mem lat for all requests +system.physmem.totBusLat 9766424000 # Total cycles spent in databus access +system.physmem.totBankLat 72772658000 # Total cycles spent in bank access +system.physmem.avgQLat 15991.86 # Average queueing delay per request +system.physmem.avgBankLat 29805.24 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 49797.10 # Average memory access latency +system.physmem.avgRdBW 330.24 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 151.94 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 330.24 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 151.94 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.01 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.26 # Average read queue length over time +system.physmem.avgWrQLen 10.90 # Average write queue length over time +system.physmem.readRowHits 966664 # Number of row buffer hits during reads +system.physmem.writeRowHits 336338 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.59 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.93 # Row buffer hit rate for writes +system.physmem.avgGap 132732.55 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,140 +235,140 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 908298891 # number of cpu cycles simulated +system.cpu.numCycles 946867600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 299221505 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 245089393 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16036207 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 167476566 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155260747 # Number of BTB hits +system.cpu.BPredUnit.lookups 299593765 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 245452602 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16045022 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 170764551 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155662191 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18353715 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 235 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 291143927 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2147541842 # Number of instructions fetch has processed -system.cpu.fetch.Branches 299221505 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 173614462 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 427042376 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 81995589 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 117912816 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 18346296 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 201 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 291830558 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2150759454 # Number of instructions fetch has processed +system.cpu.fetch.Branches 299593765 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174008487 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 427702866 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 82463506 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 122599229 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 94 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 282188311 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5315637 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 901821520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.649341 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.246532 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 88 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 282801731 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5377782 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 908156186 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.634401 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.243337 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 474779291 52.65% 52.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 22710427 2.52% 55.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38716038 4.29% 59.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47664478 5.29% 64.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40313573 4.47% 69.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46765093 5.19% 74.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38987797 4.32% 78.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 17988591 1.99% 80.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 173896232 19.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 480453401 52.90% 52.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 22859151 2.52% 55.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38736937 4.27% 59.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47688218 5.25% 64.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40498646 4.46% 69.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46746329 5.15% 74.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38999717 4.29% 78.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18064778 1.99% 80.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174109009 19.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 901821520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.329431 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.364356 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 319221723 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98997420 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 402809489 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15071254 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 65721634 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46024947 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 700 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2336308946 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2514 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 65721634 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 340227863 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 45083280 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12690 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 395699548 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55076505 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2280327240 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18280 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4628387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42035635 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2254967875 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10525732443 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10525728121 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4322 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 548647913 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1655 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1650 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 127333779 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 622133622 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 217936550 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85018666 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 64907509 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2181155194 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1636 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2010118619 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4778350 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 453891413 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1054915735 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1462 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 901821520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.228954 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.928169 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 908156186 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316405 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.271447 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 320351849 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 103310609 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403372314 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15098642 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 66022772 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46034722 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 704 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2339352792 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2529 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 66022772 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 341796573 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 48717971 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14906 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 395855837 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55748127 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2282794185 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 39847 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4611517 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42695661 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2257537981 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10537280026 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10537275559 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4467 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706320026 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 551217955 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 838 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 835 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 129599333 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 622569059 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 218142237 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 84983278 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 64739003 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2182778805 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 865 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2010794421 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4810108 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 455220170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1060725588 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 683 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 908156186 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.214150 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.929063 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 241649201 26.80% 26.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 133398569 14.79% 41.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 156277076 17.33% 58.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 115862389 12.85% 71.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125673548 13.94% 85.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75895678 8.42% 94.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39700475 4.40% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10713373 1.19% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2651211 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 247277493 27.23% 27.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 133932127 14.75% 41.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 156228000 17.20% 59.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 116195915 12.79% 71.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125706835 13.84% 85.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75923793 8.36% 94.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39533015 4.35% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10697910 1.18% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2661098 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 901821520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 908156186 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 707951 2.82% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4768 0.02% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19054904 75.97% 78.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5315511 21.19% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 703286 2.81% 2.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4771 0.02% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19012865 76.06% 78.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5274676 21.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1230445204 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 929764 0.05% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1230823853 61.21% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 930532 0.05% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued @@ -233,163 +391,163 @@ system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Ty system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 30 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 585105545 29.11% 90.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193637984 9.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 585374477 29.11% 90.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193665439 9.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2010118619 # Type of FU issued -system.cpu.iq.rate 2.213059 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25083134 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012478 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4951919807 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2635232712 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1952804452 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 778 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 167 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2035201532 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63665905 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2010794421 # Type of FU issued +system.cpu.iq.rate 2.123628 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24995598 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4959550302 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2638184259 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1953078988 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2035789802 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 217 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63764603 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 136206849 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 286531 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 188011 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43089501 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 136642278 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 284566 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 187935 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43295180 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 117367 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 386993 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 65721634 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 20156212 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1080802 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2181156911 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5548348 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 622133622 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 217936550 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1571 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 177848 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 42316 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 188011 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8591764 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10177079 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18768843 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1980852010 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 570685009 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29266609 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 66022772 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23145640 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1044628 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2182779773 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5713944 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 622569059 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 218142237 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 173655 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 44651 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 187935 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8601247 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10177350 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18778597 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1981378382 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 570935022 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29416039 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 81 # number of nop insts executed -system.cpu.iew.exec_refs 761345389 # number of memory reference insts executed -system.cpu.iew.exec_branches 237537296 # Number of branches executed -system.cpu.iew.exec_stores 190660380 # Number of stores executed -system.cpu.iew.exec_rate 2.180837 # Inst execution rate -system.cpu.iew.wb_sent 1961817327 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1952804619 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1293399468 # num instructions producing a value -system.cpu.iew.wb_consumers 2065182627 # num instructions consuming a value +system.cpu.iew.exec_nop 103 # number of nop insts executed +system.cpu.iew.exec_refs 761630934 # number of memory reference insts executed +system.cpu.iew.exec_branches 237544754 # Number of branches executed +system.cpu.iew.exec_stores 190695912 # Number of stores executed +system.cpu.iew.exec_rate 2.092561 # Inst execution rate +system.cpu.iew.wb_sent 1962075581 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1953079152 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1293757962 # num instructions producing a value +system.cpu.iew.wb_consumers 2065123050 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.149958 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626288 # average fanout of values written-back +system.cpu.iew.wb_rate 2.062674 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626480 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 458146610 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16035536 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 836099887 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.060847 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.764107 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 459769347 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 182 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16044351 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 842133415 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.046082 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.757625 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 346421369 41.43% 41.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193942009 23.20% 64.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73849330 8.83% 73.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35339477 4.23% 77.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18485791 2.21% 79.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30991807 3.71% 83.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19654660 2.35% 85.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10738938 1.28% 87.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106676506 12.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 351966566 41.79% 41.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 194208080 23.06% 64.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73932281 8.78% 73.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35396184 4.20% 77.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18675547 2.22% 80.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 31087553 3.69% 83.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19760319 2.35% 86.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10744228 1.28% 87.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106362657 12.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 836099887 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563061 # Number of instructions committed -system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 842133415 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563101 # Number of instructions committed +system.cpu.commit.committedOps 1723073913 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773822 # Number of memory references committed -system.cpu.commit.loads 485926773 # Number of loads committed +system.cpu.commit.refs 660773838 # Number of memory references committed +system.cpu.commit.loads 485926781 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462430 # Number of branches committed +system.cpu.commit.branches 213462438 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941889 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106676506 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106362657 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2910643265 # The number of ROB reads -system.cpu.rob.rob_writes 4428322151 # The number of ROB writes -system.cpu.timesIdled 678500 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6477371 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563043 # Number of Instructions Simulated -system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated -system.cpu.cpi 0.588062 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.588062 # CPI: Total CPI of All Threads -system.cpu.ipc 1.700501 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.700501 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9924419417 # number of integer regfile reads -system.cpu.int_regfile_writes 1932830839 # number of integer regfile writes -system.cpu.fp_regfile_reads 180 # number of floating regfile reads -system.cpu.fp_regfile_writes 196 # number of floating regfile writes -system.cpu.misc_regfile_reads 2885680755 # number of misc regfile reads -system.cpu.misc_regfile_writes 132 # number of misc regfile writes -system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 628.471657 # Cycle average of tags in use -system.cpu.icache.total_refs 282187157 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 785 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 359474.085350 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2918613419 # The number of ROB reads +system.cpu.rob.rob_writes 4431868415 # The number of ROB writes +system.cpu.timesIdled 795856 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 38711414 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563083 # Number of Instructions Simulated +system.cpu.committedOps 1723073895 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563083 # Number of Instructions Simulated +system.cpu.cpi 0.613033 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.613033 # CPI: Total CPI of All Threads +system.cpu.ipc 1.631234 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.631234 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9926647662 # number of integer regfile reads +system.cpu.int_regfile_writes 1933066427 # number of integer regfile writes +system.cpu.fp_regfile_reads 168 # number of floating regfile reads +system.cpu.fp_regfile_writes 190 # number of floating regfile writes +system.cpu.misc_regfile_reads 2888912367 # number of misc regfile reads +system.cpu.misc_regfile_writes 148 # number of misc regfile writes +system.cpu.icache.replacements 20 # number of replacements +system.cpu.icache.tagsinuse 632.636403 # Cycle average of tags in use +system.cpu.icache.total_refs 282800594 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 786 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 359797.193384 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 628.471657 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.306871 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.306871 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 282187157 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 282187157 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 282187157 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 282187157 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 282187157 # number of overall hits -system.cpu.icache.overall_hits::total 282187157 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses -system.cpu.icache.overall_misses::total 1154 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39417000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39417000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39417000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39417000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39417000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39417000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 282188311 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 282188311 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 282188311 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 282188311 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 282188311 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 282188311 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 632.636403 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.308904 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.308904 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 282800594 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 282800594 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 282800594 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 282800594 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 282800594 # number of overall hits +system.cpu.icache.overall_hits::total 282800594 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1137 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1137 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1137 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1137 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1137 # number of overall misses +system.cpu.icache.overall_misses::total 1137 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39598000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39598000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39598000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39598000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39598000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39598000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 282801731 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 282801731 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 282801731 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 282801731 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 282801731 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 282801731 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34156.845754 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34156.845754 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34156.845754 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34156.845754 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34156.845754 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34156.845754 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34826.737027 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34826.737027 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34826.737027 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34826.737027 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34826.737027 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34826.737027 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,309 +556,309 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 369 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 369 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 369 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 369 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 785 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 785 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 785 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 785 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28514500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28514500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28514500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28514500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28514500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28514500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 351 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 351 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 351 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 786 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 786 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 786 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 786 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 786 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28796000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28796000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28796000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28796000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28796000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28796000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36324.203822 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36324.203822 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36324.203822 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36324.203822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36324.203822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36324.203822 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36636.132316 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36636.132316 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36636.132316 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36636.132316 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36636.132316 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36636.132316 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9616145 # number of replacements -system.cpu.dcache.tagsinuse 4087.425286 # Cycle average of tags in use -system.cpu.dcache.total_refs 659915514 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9620241 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.596568 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3361698000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.425286 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997907 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997907 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 492504705 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 492504705 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167410650 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167410650 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # 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Cycle average of tags in use +system.cpu.dcache.total_refs 660505517 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9620999 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.652488 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3324501000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.861296 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998013 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998013 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 492433938 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 492433938 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168071407 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168071407 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 99 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 99 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 73 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 73 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 660505345 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 660505345 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 660505345 # number of overall hits +system.cpu.dcache.overall_hits::total 660505345 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10054191 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10054191 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4514640 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4514640 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15279890 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15279890 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15279890 # number of overall misses -system.cpu.dcache.overall_misses::total 15279890 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151975224500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151975224500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119867822584 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119867822584 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 111500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 111500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 271843047084 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 271843047084 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 271843047084 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 271843047084 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 502609198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 502609198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 14568831 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 14568831 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 14568831 # number of overall misses +system.cpu.dcache.overall_misses::total 14568831 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 192605585000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 192605585000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 133759941491 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 133759941491 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 146500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 146500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 326365526491 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 326365526491 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 326365526491 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 326365526491 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 502488129 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 502488129 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 675195245 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 675195245 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 675195245 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 675195245 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020104 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020104 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029987 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029987 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022630 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.022630 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022630 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.022630 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15040.361204 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15040.361204 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23161.087465 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23161.087465 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17790.903409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17790.903409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 547911 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 306 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 59951 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.139314 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 102 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 102 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 73 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 73 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 675074176 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 675074176 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 675074176 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 675074176 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020009 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026159 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026159 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.029412 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.029412 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021581 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021581 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021581 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021581 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19156.746177 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19156.746177 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29628.041547 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29628.041547 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22401.627591 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22401.627591 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22401.627591 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22401.627591 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1880438 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 248831 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 88187 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1969 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.323302 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 126.374302 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3473179 # number of writebacks -system.cpu.dcache.writebacks::total 3473179 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2378385 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2378385 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3281264 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3281264 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3473899 # number of writebacks +system.cpu.dcache.writebacks::total 3473899 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2327206 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2327206 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2620625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2620625 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5659649 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5659649 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5659649 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5659649 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7726108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7726108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894133 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1894133 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9620241 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9620241 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9620241 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9620241 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75134366500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75134366500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 39443717607 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 39443717607 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114578084107 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114578084107 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114578084107 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114578084107 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015372 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015372 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014248 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014248 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9724.736763 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9724.736763 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20824.154168 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20824.154168 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11910.105382 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11910.105382 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11910.105382 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11910.105382 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 4947831 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4947831 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4947831 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4947831 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7726985 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7726985 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894015 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1894015 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9621000 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9621000 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9621000 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9621000 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100672222000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 100672222000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58875647012 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58875647012 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 159547869012 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 159547869012 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 159547869012 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 159547869012 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014252 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014252 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014252 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014252 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13028.655032 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13028.655032 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31085.100705 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31085.100705 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16583.293734 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16583.293734 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16583.293734 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16583.293734 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2426778 # number of replacements -system.cpu.l2cache.tagsinuse 31133.069432 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8743063 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2456493 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.559165 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 77443387000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14066.378954 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 15.908545 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17050.781934 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.429272 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000485 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.520349 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.950106 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6115252 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6115280 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3473179 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3473179 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1063326 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1063326 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7178578 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7178606 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7178578 # number of overall hits -system.cpu.l2cache.overall_hits::total 7178606 # number of overall hits +system.cpu.l2cache.replacements 2427272 # number of replacements +system.cpu.l2cache.tagsinuse 31171.716737 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8744168 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2456984 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.558903 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 80002919000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14002.042506 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 15.065518 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17154.608713 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.427308 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000460 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.523517 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.951285 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6115863 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6115892 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3473899 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3473899 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1062992 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1062992 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7178855 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7178884 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7178855 # number of overall hits +system.cpu.l2cache.overall_hits::total 7178884 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1610856 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1611613 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 830807 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35737.459927 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 756 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611113 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1611869 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 831023 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 831023 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 756 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2442136 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2442892 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 756 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25190143 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131407022048 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 131432212191 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208505 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208581 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438763 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438763 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253834 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.253892 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253834 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.253892 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33320.294974 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49115.419876 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49108.011634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62906.237957 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62906.237957 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33320.294974 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53808.232649 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53801.892262 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33320.294974 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53808.232649 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53801.892262 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |