diff options
Diffstat (limited to 'tests/long/se/60.bzip2')
6 files changed, 2384 insertions, 2383 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 77212a74e..9335161f5 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.998096 # Number of seconds simulated -sim_ticks 998095972500 # Number of ticks simulated -final_tick 998095972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.987579 # Number of seconds simulated +sim_ticks 987579062500 # Number of ticks simulated +final_tick 987579062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135518 # Simulator instruction rate (inst/s) -host_op_rate 135518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74327611 # Simulator tick rate (ticks/s) -host_mem_usage 465236 # Number of bytes of host memory used -host_seconds 13428.33 # Real time elapsed on the host +host_inst_rate 79028 # Simulator instruction rate (inst/s) +host_op_rate 79028 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42888030 # Simulator tick rate (ticks/s) +host_mem_usage 458304 # Number of bytes of host memory used +host_seconds 23026.92 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137579264 # Number of bytes read from this memory -system.physmem.bytes_read::total 137634240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125364928 # Number of bytes read from this memory +system.physmem.bytes_read::total 125419904 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67104640 # Number of bytes written to this memory -system.physmem.bytes_written::total 67104640 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory +system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2149676 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2150535 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048510 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048510 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 137841718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 137896799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55081 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55081 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 67232653 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 67232653 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 67232653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 137841718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 205129452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2150535 # Total number of read requests seen -system.physmem.writeReqs 1048510 # Total number of write requests seen -system.physmem.cpureqs 3199045 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 137634240 # Total number of bytes read from memory -system.physmem.bytesWritten 67104640 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 137634240 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67104640 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1104 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 1958827 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959686 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 126941662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 126997330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55667 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55667 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 65974991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 65974991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 65974991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 126941662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 192972321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959686 # Total number of read requests seen +system.physmem.writeReqs 1018055 # Total number of write requests seen +system.physmem.cpureqs 2977741 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125419904 # Total number of bytes read from memory +system.physmem.bytesWritten 65155520 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125419904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65155520 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 577 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 134750 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 134519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 135461 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 133443 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 134821 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 134519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 135107 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 134152 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 133438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 134313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 134956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 130690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 131784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 134689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 137104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 135685 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 65615 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 65313 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 65943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 64961 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 65149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 64711 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 65179 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 64600 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65708 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64486 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 65220 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 66941 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 67682 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 66873 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 122432 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 123238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 122861 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 121276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 122601 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 124477 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 123481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121547 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122168 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 122611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 120103 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 120483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 121941 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 124488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123178 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63120 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 63437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63830 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63407 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 63139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 62716 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63395 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63432 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 62525 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63278 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 63327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 63976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64713 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 65307 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64492 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 998095934500 # Total gap between requests +system.physmem.totGap 987579010500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2150535 # Categorize read packet sizes +system.physmem.readPktSize::6 1959686 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1048510 # categorize write packet sizes +system.physmem.writePktSize::6 1018055 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1835130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 153641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 61976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 24246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 14808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1651837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 192315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 82006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 19730119710 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 92821713710 # Sum of mem lat for all requests -system.physmem.totBusLat 8597724000 # Total cycles spent in databus access -system.physmem.totBankLat 64493870000 # Total cycles spent in bank access -system.physmem.avgQLat 9179.23 # Average queueing delay per request -system.physmem.avgBankLat 30005.09 # Average bank access latency per request +system.physmem.totQLat 19599583947 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 85189869947 # Sum of mem lat for all requests +system.physmem.totBusLat 7836436000 # Total cycles spent in databus access +system.physmem.totBankLat 57753850000 # Total cycles spent in bank access +system.physmem.avgQLat 10004.34 # Average queueing delay per request +system.physmem.avgBankLat 29479.65 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43184.32 # Average memory access latency -system.physmem.avgRdBW 137.90 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 67.23 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 137.90 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 67.23 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 43483.99 # Average memory access latency +system.physmem.avgRdBW 127.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 65.97 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 127.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 65.97 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.28 # Data bus utilization in percentage +system.physmem.busUtil 1.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.09 # Average read queue length over time -system.physmem.avgWrQLen 11.29 # Average write queue length over time -system.physmem.readRowHits 884898 # Number of row buffer hits during reads -system.physmem.writeRowHits 338451 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.28 # Row buffer hit rate for writes -system.physmem.avgGap 311998.09 # Average gap between requests +system.physmem.avgWrQLen 10.28 # Average write queue length over time +system.physmem.readRowHits 834542 # Number of row buffer hits during reads +system.physmem.writeRowHits 194109 # Number of row buffer hits during writes +system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes +system.physmem.avgGap 331653.76 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444628016 # DTB read hits +system.cpu.dtb.read_hits 444784364 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449525094 # DTB read accesses -system.cpu.dtb.write_hits 160917908 # DTB write hits +system.cpu.dtb.read_accesses 449681442 # DTB read accesses +system.cpu.dtb.write_hits 160833165 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162619212 # DTB write accesses -system.cpu.dtb.data_hits 605545924 # DTB hits +system.cpu.dtb.write_accesses 162534469 # DTB write accesses +system.cpu.dtb.data_hits 605617529 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612144306 # DTB accesses -system.cpu.itb.fetch_hits 232077768 # ITB hits +system.cpu.dtb.data_accesses 612215911 # DTB accesses +system.cpu.itb.fetch_hits 232120860 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232077790 # ITB accesses +system.cpu.itb.fetch_accesses 232120882 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1996191946 # number of cpu cycles simulated +system.cpu.numCycles 1975158126 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328934492 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253834142 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140072594 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 232648931 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138176846 # Number of BTB hits +system.cpu.branch_predictor.lookups 328916009 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253846257 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140045817 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 232481413 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138136467 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.392857 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175181145 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153753347 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669765696 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.418284 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175138589 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153777420 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669811898 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045968313 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3046014515 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651043890 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617989866 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121337623 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12136513 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133474136 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81726090 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.023232 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139616626 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 650984890 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617988746 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121313944 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12133415 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133447359 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81752917 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.010775 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139622793 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746553256 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746581569 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7548952 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 419177402 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1577014544 # Number of cycles cpu stages are processed. -system.cpu.activity 79.001148 # Percentage of cycles cpu is active +system.cpu.timesIdled 7474420 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 398305853 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576852273 # Number of cycles cpu stages are processed. +system.cpu.activity 79.834230 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -272,144 +272,144 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.096941 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.085383 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.096941 # CPI: Total CPI of All Threads -system.cpu.ipc 0.911626 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.085383 # CPI: Total CPI of All Threads +system.cpu.ipc 0.921334 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.911626 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 805412484 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190779462 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.652553 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1063871870 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932320076 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.704931 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1022192992 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973998954 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.792851 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1586493403 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409698543 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.524005 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 973220385 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022971561 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.246152 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.921334 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 784384186 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190773940 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.287525 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1042820423 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932337703 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 47.203193 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1001198544 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973959582 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.310461 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1565492748 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409665378 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.740890 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 952315389 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022842737 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.785360 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 667.791202 # Cycle average of tags in use -system.cpu.icache.total_refs 232076694 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 667.497042 # Cycle average of tags in use +system.cpu.icache.total_refs 232119756 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270170.772992 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270220.903376 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 667.791202 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.326070 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.326070 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232076694 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232076694 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232076694 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232076694 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232076694 # number of overall hits -system.cpu.icache.overall_hits::total 232076694 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses -system.cpu.icache.overall_misses::total 1072 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56100000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56100000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56100000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56100000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56100000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56100000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232077766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232077766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232077766 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232077766 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232077766 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232077766 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 667.497042 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325926 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325926 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232119756 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232119756 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232119756 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232119756 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232119756 # number of overall hits +system.cpu.icache.overall_hits::total 232119756 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1104 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1104 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1104 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1104 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1104 # number of overall misses +system.cpu.icache.overall_misses::total 1104 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58767000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58767000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58767000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58767000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58767000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58767000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232120860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232120860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232120860 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232120860 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232120860 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232120860 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52332.089552 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52332.089552 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52332.089552 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52332.089552 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52332.089552 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52332.089552 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 99 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53230.978261 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53230.978261 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53230.978261 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53230.978261 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 213 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 213 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 213 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45656000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45656000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45656000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45656000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45656000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45656000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46993000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46993000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46993000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46993000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46993000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46993000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.174622 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.174622 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.174622 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.174622 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.174622 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.174622 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54706.635623 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54706.635623 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107316 # number of replacements -system.cpu.dcache.tagsinuse 4082.375203 # Cycle average of tags in use -system.cpu.dcache.total_refs 595069266 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111412 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310324 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12653266000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.375203 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996674 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996674 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271434 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271434 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157797832 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157797832 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595069266 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595069266 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595069266 # number of overall hits -system.cpu.dcache.overall_hits::total 595069266 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324229 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324229 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2930670 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2930670 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10254899 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10254899 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10254899 # number of overall misses -system.cpu.dcache.overall_misses::total 10254899 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 169482879500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 169482879500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 114253006500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 114253006500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 283735886000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 283735886000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 283735886000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 283735886000 # number of overall miss cycles +system.cpu.dcache.replacements 9107377 # number of replacements +system.cpu.dcache.tagsinuse 4082.124534 # Cycle average of tags in use +system.cpu.dcache.total_refs 593539067 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111473 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.141944 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12681076000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.124534 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996612 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996612 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437268755 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268755 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156270312 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156270312 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593539067 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593539067 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593539067 # number of overall hits +system.cpu.dcache.overall_hits::total 593539067 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326908 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326908 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4458190 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4458190 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 11785098 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11785098 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11785098 # number of overall misses +system.cpu.dcache.overall_misses::total 11785098 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 160313092500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 160313092500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 195290221000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 195290221000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 355603313500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 355603313500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 355603313500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 355603313500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -418,56 +418,56 @@ system.cpu.dcache.demand_accesses::cpu.data 605324165 # system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018234 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.018234 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016941 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016941 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016941 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016941 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23140.030097 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23140.030097 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38985.285447 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38985.285447 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27668.325744 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27668.325744 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27668.325744 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27668.325744 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 791552 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14185855 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 26512 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 205984 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.856367 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 68.868723 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027737 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027737 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019469 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019469 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019469 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019469 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21880.047149 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21880.047149 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43804.822361 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43804.822361 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30173.980182 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30173.980182 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30173.980182 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30173.980182 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9234267 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4818811 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 358092 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65601 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.787415 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 73.456365 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389638 # number of writebacks -system.cpu.dcache.writebacks::total 3389638 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101954 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101954 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1041533 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1041533 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1143487 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1143487 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1143487 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1143487 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222275 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222275 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889137 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889137 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111412 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111412 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111412 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111412 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 153198656000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 153198656000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69357589500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 69357589500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 222556245500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 222556245500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 222556245500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 222556245500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3693297 # number of writebacks +system.cpu.dcache.writebacks::total 3693297 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104632 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104632 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2568993 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2568993 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2673625 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2673625 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2673625 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2673625 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222276 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222276 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889197 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889197 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111473 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111473 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111473 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111473 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144007395000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 144007395000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67943434500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 67943434500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211950829500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211950829500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211950829500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211950829500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -476,149 +476,149 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21211.966589 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21211.966589 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36713.901374 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36713.901374 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24426.098337 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24426.098337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24426.098337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24426.098337 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19939.336990 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19939.336990 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35964.187165 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35964.187165 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23261.971967 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23261.971967 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23261.971967 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23261.971967 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2133754 # number of replacements -system.cpu.l2cache.tagsinuse 30562.068421 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8448353 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2163445 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.905046 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 183967255500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14375.476614 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.146879 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16152.444929 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.438705 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001042 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.492934 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.932680 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5860981 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5860981 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3389638 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3389638 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1100755 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1100755 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6961736 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6961736 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6961736 # number of overall hits -system.cpu.l2cache.overall_hits::total 6961736 # number of overall hits +system.cpu.l2cache.replacements 1926955 # number of replacements +system.cpu.l2cache.tagsinuse 30885.794112 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8958711 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1956748 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.578367 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 67633900002 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15038.473814 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 35.309498 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15812.010801 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.458938 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001078 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.482544 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.942560 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6044303 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044303 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693297 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3693297 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108343 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108343 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7152646 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7152646 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7152646 # number of overall hits +system.cpu.l2cache.overall_hits::total 7152646 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1360852 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1361711 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 788824 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 788824 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1177531 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1178390 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 781296 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 781296 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2149676 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2150535 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1958827 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1959686 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2149676 # number of overall misses -system.cpu.l2cache.overall_misses::total 2150535 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44791500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 87269885000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 87314676500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56286735500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56286735500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44791500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 143556620500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 143601412000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44791500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 143556620500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 143601412000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958827 # number of overall misses +system.cpu.l2cache.overall_misses::total 1959686 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46130000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76211329000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 76257459000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 54802656500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 54802656500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 46130000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 131013985500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 131060115500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 46130000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 131013985500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 131060115500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7221833 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222692 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3389638 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3389638 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889579 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889579 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221834 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222693 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3693297 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3693297 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889639 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889639 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111412 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112271 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111473 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112332 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111412 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112271 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111473 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112332 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188436 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.188532 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417460 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.417460 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413463 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413463 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235932 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.236004 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214985 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.215059 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235932 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.236004 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52143.771828 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64128.858245 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 64121.297764 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71355.252249 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71355.252249 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52143.771828 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66780.584842 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66774.738379 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52143.771828 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66780.584842 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66774.738379 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 438308 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53701.979045 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64721.293112 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 64713.260466 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70143.270284 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70143.270284 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66878.120015 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66878.120015 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 3445 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 127.230189 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1048510 # number of writebacks -system.cpu.l2cache.writebacks::total 1048510 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks +system.cpu.l2cache.writebacks::total 1018055 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360852 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1361711 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788824 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 788824 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177531 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178390 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2149676 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2150535 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958827 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1959686 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2149676 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2150535 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33924935 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 69917631981 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 69951556916 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46302511646 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46302511646 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33924935 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116220143627 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 116254068562 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33924935 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116220143627 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 116254068562 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958827 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959686 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35264420 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 61190782598 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 61226047018 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44920930070 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44920930070 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35264420 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106111712668 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 106146977088 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35264420 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106111712668 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 106146977088 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417460 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417460 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413463 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39493.521537 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51377.836812 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51370.339900 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58698.152751 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58698.152751 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39493.521537 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54064.028080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54058.208103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39493.521537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54064.028080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54058.208103 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41052.875437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51965.326261 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51957.371514 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57495.405160 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57495.405160 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 4dd96e908..4dfb5e529 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.622687 # Number of seconds simulated -sim_ticks 622686686500 # Number of ticks simulated -final_tick 622686686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.676099 # Number of seconds simulated +sim_ticks 676099363500 # Number of ticks simulated +final_tick 676099363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130099 # Simulator instruction rate (inst/s) -host_op_rate 130099 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46664017 # Simulator tick rate (ticks/s) -host_mem_usage 466244 # Number of bytes of host memory used -host_seconds 13344.04 # Real time elapsed on the host +host_inst_rate 178127 # Simulator instruction rate (inst/s) +host_op_rate 178127 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69371375 # Simulator tick rate (ticks/s) +host_mem_usage 459324 # Number of bytes of host memory used +host_seconds 9746.09 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138173120 # Number of bytes read from this memory -system.physmem.bytes_read::total 138234624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67206720 # Number of bytes written to this memory -system.physmem.bytes_written::total 67206720 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2158955 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2159916 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050105 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050105 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 98772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 221898305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 221997077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 98772 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 98772 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 107930234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 107930234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 107930234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 98772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 221898305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 329927311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2159916 # Total number of read requests seen -system.physmem.writeReqs 1050105 # Total number of write requests seen -system.physmem.cpureqs 3210021 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 138234624 # Total number of bytes read from memory -system.physmem.bytesWritten 67206720 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 138234624 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67206720 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1101 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125805120 # Number of bytes read from this memory +system.physmem.bytes_read::total 125866688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65265216 # Number of bytes written to this memory +system.physmem.bytes_written::total 65265216 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965705 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966667 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019769 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019769 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 91064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 186074898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 186165961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96531989 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96531989 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96531989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 186074898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 282697950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966667 # Total number of read requests seen +system.physmem.writeReqs 1019769 # Total number of write requests seen +system.physmem.cpureqs 2986436 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125866688 # Total number of bytes read from memory +system.physmem.bytesWritten 65265216 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125866688 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65265216 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 625 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 135516 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 134944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 135958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 133984 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 135382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 135012 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 135645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 134678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 134063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 135260 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 135483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 131205 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 132348 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 135290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 137712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 136335 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 65727 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 65366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 66027 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 65044 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 65255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 64804 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 65281 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65090 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 64712 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65787 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64601 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 65333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 67038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 67805 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 66971 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 123034 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 123551 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 123227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 121682 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123042 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122572 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 124906 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 123907 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121965 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122878 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 123012 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 120476 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 120832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 122358 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 124956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123644 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 63494 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63931 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63515 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 63255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 62796 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63537 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 62612 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63480 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 64069 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 63419 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64057 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64815 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 65441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64562 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 622686634000 # Total gap between requests +system.physmem.totGap 676099295000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2159916 # Categorize read packet sizes +system.physmem.readPktSize::6 1966667 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1050105 # categorize write packet sizes +system.physmem.writePktSize::6 1019769 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1715217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 265103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 85338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 37466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 21744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13852 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9060 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1634338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 235140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 26277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 43276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 22793561782 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 94682781782 # Sum of mem lat for all requests -system.physmem.totBusLat 8635260000 # Total cycles spent in databus access -system.physmem.totBankLat 63253960000 # Total cycles spent in bank access -system.physmem.avgQLat 10558.37 # Average queueing delay per request -system.physmem.avgBankLat 29300.32 # Average bank access latency per request +system.physmem.totQLat 20663639504 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 85829737504 # Sum of mem lat for all requests +system.physmem.totBusLat 7864168000 # Total cycles spent in databus access +system.physmem.totBankLat 57301930000 # Total cycles spent in bank access +system.physmem.avgQLat 10510.27 # Average queueing delay per request +system.physmem.avgBankLat 29145.83 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43858.68 # Average memory access latency -system.physmem.avgRdBW 222.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 107.93 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 222.00 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 107.93 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 43656.11 # Average memory access latency +system.physmem.avgRdBW 186.17 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 96.53 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 186.17 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 96.53 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.06 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.91 # Average write queue length over time -system.physmem.readRowHits 893342 # Number of row buffer hits during reads -system.physmem.writeRowHits 340237 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.40 # Row buffer hit rate for writes -system.physmem.avgGap 193982.11 # Average gap between requests +system.physmem.busUtil 1.77 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.13 # Average read queue length over time +system.physmem.avgWrQLen 11.69 # Average write queue length over time +system.physmem.readRowHits 840809 # Number of row buffer hits during reads +system.physmem.writeRowHits 193935 # Number of row buffer hits during writes +system.physmem.readRowHitRate 42.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 19.02 # Row buffer hit rate for writes +system.physmem.avgGap 226390.02 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 610476386 # DTB read hits -system.cpu.dtb.read_misses 10761875 # DTB read misses +system.cpu.dtb.read_hits 623300287 # DTB read hits +system.cpu.dtb.read_misses 11248161 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 621238261 # DTB read accesses -system.cpu.dtb.write_hits 207269464 # DTB write hits -system.cpu.dtb.write_misses 6561537 # DTB write misses +system.cpu.dtb.read_accesses 634548448 # DTB read accesses +system.cpu.dtb.write_hits 212126260 # DTB write hits +system.cpu.dtb.write_misses 7156273 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 213831001 # DTB write accesses -system.cpu.dtb.data_hits 817745850 # DTB hits -system.cpu.dtb.data_misses 17323412 # DTB misses +system.cpu.dtb.write_accesses 219282533 # DTB write accesses +system.cpu.dtb.data_hits 835426547 # DTB hits +system.cpu.dtb.data_misses 18404434 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 835069262 # DTB accesses -system.cpu.itb.fetch_hits 398378101 # ITB hits -system.cpu.itb.fetch_misses 55 # ITB misses +system.cpu.dtb.data_accesses 853830981 # DTB accesses +system.cpu.itb.fetch_hits 409165317 # ITB hits +system.cpu.itb.fetch_misses 53 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398378156 # ITB accesses +system.cpu.itb.fetch_accesses 409165370 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,245 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1245373374 # number of cpu cycles simulated +system.cpu.numCycles 1352198728 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 378146140 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 290510585 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18737073 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 264395160 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 259999350 # Number of BTB hits +system.cpu.BPredUnit.lookups 392126599 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 302845458 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 19199722 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 274650283 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 270818962 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25131917 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6182 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 409812987 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3135210650 # Number of instructions fetch has processed -system.cpu.fetch.Branches 378146140 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 285131267 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 571966611 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 132239561 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 126137605 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1394 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 398378101 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10155921 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1214707352 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.581042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.162326 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25776268 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6145 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 421462775 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3238747115 # Number of instructions fetch has processed +system.cpu.fetch.Branches 392126599 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 296595230 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 591261083 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 148936596 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 163448952 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1316 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 409165317 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10196267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1298229870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494741 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.143526 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 642740741 52.91% 52.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42508733 3.50% 56.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22198972 1.83% 58.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40683898 3.35% 61.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 126205169 10.39% 71.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63532228 5.23% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40428272 3.33% 80.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30073881 2.48% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 206335458 16.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 706968787 54.46% 54.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 44358932 3.42% 57.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22743833 1.75% 59.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 41944085 3.23% 62.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 132056857 10.17% 73.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 64435006 4.96% 77.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41239075 3.18% 81.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30635006 2.36% 83.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 213848289 16.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1214707352 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.303641 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.517486 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 437634335 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 113109865 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542282236 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 14893078 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 106787838 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60009942 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1008 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3056719356 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2151 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 106787838 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 458205445 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 68879857 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5925 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535635557 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45192730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2974950452 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 455085 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1725044 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40939895 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2225174239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3842201349 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3840803931 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1397418 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1298229870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.289992 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.395171 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 455239490 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 145264666 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 557656082 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18015537 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 122054095 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 61382914 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1012 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3154733525 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2110 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 122054095 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 478678718 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 92924622 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7988 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 549590922 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 54973525 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3070816575 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 560752 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1743859 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 49056518 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2295520192 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3973370931 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3971968228 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1402703 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 848971276 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 208 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 208 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 94220163 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 674209051 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 250003668 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 60248313 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 34574137 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2672716058 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2475684354 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3185220 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 926051369 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 394490469 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1214707352 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.038091 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971432 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 919317229 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 211 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 118384405 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 691487195 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 258255800 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68719353 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37210437 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2756294295 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 187 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2536632821 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3950694 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1007358741 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 432150244 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 158 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1298229870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.953917 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.961710 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 391612222 32.24% 32.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 190116739 15.65% 47.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 180710183 14.88% 62.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153608021 12.65% 75.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 136709031 11.25% 86.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80377873 6.62% 93.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 61799975 5.09% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14388617 1.18% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5384691 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 442263739 34.07% 34.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 208903385 16.09% 50.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 191557841 14.76% 64.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 152463661 11.74% 76.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 137672348 10.60% 87.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81203098 6.25% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 63863451 4.92% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15081593 1.16% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5220754 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1214707352 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1298229870 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2236018 11.81% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12183595 64.36% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4510642 23.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2156518 11.37% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12254343 64.62% 76.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4551680 24.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1615926808 65.27% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 102 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 171 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 638812583 25.80% 91.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 220944337 8.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1658475044 65.38% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 273 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 652209568 25.71% 91.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 225947593 8.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2475684354 # Type of FU issued -system.cpu.iq.rate 1.987905 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18930255 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007646 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6186206687 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3597520072 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2374361589 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1984848 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1351695 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 870010 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2493639169 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 975440 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 56324993 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2536632821 # Type of FU issued +system.cpu.iq.rate 1.875932 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18962541 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007475 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6392425036 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3762406457 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2431792022 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1983711 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1351957 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 870252 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2554620629 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 974733 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62690136 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 229613388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 251555 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 105716 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 89275166 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 246891532 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263108 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 106999 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 97527298 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 232 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 90239 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 177 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1449625 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 106787838 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30509174 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1004696 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2814392916 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16951249 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 674209051 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 250003668 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 211284 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14280 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 105716 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13148912 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8849149 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 21998061 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2424970447 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 621239857 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 50713907 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 122054095 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 42236040 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1169448 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2901607263 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 18449890 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 691487195 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 258255800 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 187 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 295034 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19978 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 106999 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13433299 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8961049 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22394348 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2485079596 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 634549945 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 51553225 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 141676677 # number of nop insts executed -system.cpu.iew.exec_refs 835070896 # number of memory reference insts executed -system.cpu.iew.exec_branches 296780799 # Number of branches executed -system.cpu.iew.exec_stores 213831039 # Number of stores executed -system.cpu.iew.exec_rate 1.947183 # Inst execution rate -system.cpu.iew.wb_sent 2403689836 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2375231599 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1360982490 # num instructions producing a value -system.cpu.iew.wb_consumers 1724379175 # num instructions consuming a value +system.cpu.iew.exec_nop 145312781 # number of nop insts executed +system.cpu.iew.exec_refs 853832523 # number of memory reference insts executed +system.cpu.iew.exec_branches 304694140 # Number of branches executed +system.cpu.iew.exec_stores 219282578 # Number of stores executed +system.cpu.iew.exec_rate 1.837806 # Inst execution rate +system.cpu.iew.wb_sent 2461943508 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2432662274 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1394848463 # num instructions producing a value +system.cpu.iew.wb_consumers 1766930878 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907245 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789259 # average fanout of values written-back +system.cpu.iew.wb_rate 1.799042 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789419 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 754743358 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 860868467 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18736187 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1107919514 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.642520 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504559 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 19198826 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1176175775 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.547201 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.484504 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 582245438 52.55% 52.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181606604 16.39% 68.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90875132 8.20% 77.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53034266 4.79% 81.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36917610 3.33% 85.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 29689254 2.68% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22142026 2.00% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22921878 2.07% 92.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 88487306 7.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 658247718 55.97% 55.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175915600 14.96% 70.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90578875 7.70% 78.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53177308 4.52% 83.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35329719 3.00% 86.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23851430 2.03% 88.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 23326017 1.98% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23350140 1.99% 92.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 92398968 7.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1107919514 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1176175775 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,373 +475,371 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 88487306 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 92398968 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3508176492 # The number of ROB reads -system.cpu.rob.rob_writes 5255937619 # The number of ROB writes -system.cpu.timesIdled 768601 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30666022 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3678646200 # The number of ROB reads +system.cpu.rob.rob_writes 5483460601 # The number of ROB writes +system.cpu.timesIdled 829567 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53968858 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.717363 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.717363 # CPI: Total CPI of All Threads -system.cpu.ipc 1.393995 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.393995 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3260141632 # number of integer regfile reads -system.cpu.int_regfile_writes 1905484731 # number of integer regfile writes -system.cpu.fp_regfile_reads 51179 # number of floating regfile reads -system.cpu.fp_regfile_writes 563 # number of floating regfile writes +system.cpu.cpi 0.778897 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.778897 # CPI: Total CPI of All Threads +system.cpu.ipc 1.283867 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.283867 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3341460388 # number of integer regfile reads +system.cpu.int_regfile_writes 1950187380 # number of integer regfile writes +system.cpu.fp_regfile_reads 51936 # number of floating regfile reads +system.cpu.fp_regfile_writes 538 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 770.400860 # Cycle average of tags in use -system.cpu.icache.total_refs 398376643 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 414543.853278 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 771.801258 # Cycle average of tags in use +system.cpu.icache.total_refs 409163812 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 962 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 425326.207900 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 770.400860 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.376172 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.376172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 398376643 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 398376643 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 398376643 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 398376643 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 398376643 # number of overall hits -system.cpu.icache.overall_hits::total 398376643 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1458 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1458 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1458 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1458 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1458 # number of overall misses -system.cpu.icache.overall_misses::total 1458 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 53978500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 53978500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 53978500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 53978500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 53978500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 53978500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 398378101 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 398378101 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 398378101 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 398378101 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 398378101 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 398378101 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 771.801258 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.376856 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.376856 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 409163812 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 409163812 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 409163812 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 409163812 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 409163812 # number of overall hits +system.cpu.icache.overall_hits::total 409163812 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1504 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1504 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1504 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1504 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1504 # number of overall misses +system.cpu.icache.overall_misses::total 1504 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 80548999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 80548999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 80548999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 80548999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 80548999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 80548999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 409165316 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 409165316 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 409165316 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 409165316 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 409165316 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 409165316 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37022.290809 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37022.290809 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37022.290809 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37022.290809 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37022.290809 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37022.290809 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53556.515293 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53556.515293 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53556.515293 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53556.515293 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53556.515293 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53556.515293 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1029 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 147 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 497 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 497 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 497 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 497 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 497 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 497 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 961 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 961 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 961 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37991000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37991000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37991000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37991000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 542 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 542 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 542 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 542 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 542 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 542 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 962 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 962 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 962 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57069999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 57069999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57069999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 57069999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57069999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 57069999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39532.778356 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39532.778356 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39532.778356 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39532.778356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39532.778356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39532.778356 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59324.323285 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59324.323285 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59324.323285 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59324.323285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59324.323285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59324.323285 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176449 # number of replacements -system.cpu.dcache.tagsinuse 4086.538678 # Cycle average of tags in use -system.cpu.dcache.total_refs 700391806 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180545 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.290874 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5478544000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.538678 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997690 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997690 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 544376569 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 544376569 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156015231 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156015231 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 700391800 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 700391800 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 700391800 # number of overall hits -system.cpu.dcache.overall_hits::total 700391800 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9752930 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9752930 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4713271 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4713271 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 14466201 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 14466201 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 14466201 # number of overall misses -system.cpu.dcache.overall_misses::total 14466201 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 164485394500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 164485394500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 131300824319 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 131300824319 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 62500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 62500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 295786218819 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 295786218819 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 295786218819 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 295786218819 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 554129499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 554129499 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 9177397 # number of replacements +system.cpu.dcache.tagsinuse 4086.580271 # Cycle average of tags in use +system.cpu.dcache.total_refs 703801568 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9181493 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.654371 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5761373000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.580271 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997700 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997700 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 548148518 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 548148518 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155653046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155653046 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 703801564 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 703801564 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 703801564 # number of overall hits +system.cpu.dcache.overall_hits::total 703801564 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11295128 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11295128 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5075456 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5075456 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 16370584 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16370584 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16370584 # number of overall misses +system.cpu.dcache.overall_misses::total 16370584 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 280321207500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 280321207500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 216815235389 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 216815235389 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 51500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 51500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 497136442889 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 497136442889 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 497136442889 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 497136442889 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 559443646 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 559443646 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 8 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 8 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 714858001 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 714858001 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 714858001 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 714858001 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017600 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017600 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029324 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.020236 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.020236 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.020236 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.020236 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16865.228654 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16865.228654 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27857.686163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27857.686163 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20446.710150 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20446.710150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20446.710150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20446.710150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 200506 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3116753 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 10498 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65116 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.099448 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 47.864626 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 720172148 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 720172148 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 720172148 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 720172148 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020190 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020190 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031578 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031578 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.022731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022731 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022731 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24817.886747 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24817.886747 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42718.375529 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42718.375529 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30367.666962 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30367.666962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30367.666962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30367.666962 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10443209 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5645556 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 732857 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.249996 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 86.680014 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3416510 # number of writebacks -system.cpu.dcache.writebacks::total 3416510 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2456183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2456183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2829474 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2829474 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5285657 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5285657 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5285657 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5285657 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296747 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296747 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883797 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883797 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725010 # number of writebacks +system.cpu.dcache.writebacks::total 3725010 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3997316 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3997316 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3191776 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3191776 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7189092 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7189092 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7189092 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7189092 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7297812 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7297812 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883680 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883680 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180544 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180544 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180544 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180544 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 83795715500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 83795715500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 42424545344 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 42424545344 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 28500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 28500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126220260844 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126220260844 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126220260844 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126220260844 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013168 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013168 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9181492 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9181492 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9181492 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9181492 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 149509028500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 149509028500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65361082800 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 65361082800 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 49500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 49500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214870111300 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 214870111300 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214870111300 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 214870111300 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013045 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013045 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.125000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.125000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012842 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012842 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11483.982588 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11483.982588 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22520.762770 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22520.762770 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 28500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 28500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13748.669016 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13748.669016 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13748.669016 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13748.669016 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012749 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012749 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012749 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012749 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20486.829272 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20486.829272 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34698.612716 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34698.612716 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 49500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 49500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23402.526659 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23402.526659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23402.526659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23402.526659 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2143493 # number of replacements -system.cpu.l2cache.tagsinuse 30938.495436 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8540491 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2173189 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.929935 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 108738439000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14386.053768 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 29.461670 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16522.979998 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.439028 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000899 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.504241 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.944168 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5920330 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5920330 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3416510 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3416510 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1101260 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1101260 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7021590 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7021590 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7021590 # number of overall hits -system.cpu.l2cache.overall_hits::total 7021590 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 961 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1376412 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1377373 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 782543 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 782543 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 961 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2158955 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2159916 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 961 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2158955 # number of overall misses -system.cpu.l2cache.overall_misses::total 2159916 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37023500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 69752519000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 69789542500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 38825223000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 38825223000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37023500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 108577742000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 108614765500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37023500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 108577742000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 108614765500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 961 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296742 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297703 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3416510 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3416510 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883803 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883803 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 961 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180545 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181506 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 961 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180545 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181506 # number of overall (read+write) accesses +system.cpu.l2cache.replacements 1933961 # number of replacements +system.cpu.l2cache.tagsinuse 31328.043846 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9059502 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1963742 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.613387 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 30942494502 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14698.563987 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 28.777983 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16600.701877 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.448565 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000878 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.506613 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.956056 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6107231 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6107231 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3725010 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3725010 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108557 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108557 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7215788 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7215788 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7215788 # number of overall hits +system.cpu.l2cache.overall_hits::total 7215788 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1190572 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1191534 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 775133 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 775133 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 962 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1965705 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1966667 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 962 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1965705 # number of overall misses +system.cpu.l2cache.overall_misses::total 1966667 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 56098500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 80363331500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 80419430000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 51942474500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 51942474500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 56098500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 132305806000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 132361904500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 56098500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 132305806000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 132361904500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 962 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7297803 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7298765 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3725010 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3725010 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883690 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883690 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 962 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9181493 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9182455 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 962 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9181493 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9182455 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188634 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.188741 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415406 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.415406 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163141 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163251 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411497 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.411497 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235166 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.235246 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214094 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235166 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.235246 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 38526.014568 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50677.063990 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 50668.586142 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49614.172001 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49614.172001 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 38526.014568 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50291.804137 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50286.569246 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38526.014568 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50291.804137 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50286.569246 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 138175 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214094 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58314.449064 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67499.766079 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67492.350197 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67011.047781 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67011.047781 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58314.449064 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67307.050651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67302.651898 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58314.449064 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67307.050651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67302.651898 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 4214 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 32.789511 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050105 # number of writebacks -system.cpu.l2cache.writebacks::total 1050105 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376412 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1377373 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782543 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782543 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2158955 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2159916 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2158955 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2159916 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33564956 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 64705839431 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 64739404387 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36015294954 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36015294954 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33564956 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 100721134385 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 100754699341 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33564956 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 100721134385 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 100754699341 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019769 # number of writebacks +system.cpu.l2cache.writebacks::total 1019769 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190572 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191534 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775133 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775133 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965705 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966667 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965705 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966667 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 43990994 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 65246294234 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 65290285228 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 42161089674 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 42161089674 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43990994 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107407383908 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 107451374902 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43990994 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107407383908 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 107451374902 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188741 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415406 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415406 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163141 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163251 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411497 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411497 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235166 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235246 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214094 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235166 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235246 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34927.113424 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47010.516786 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 47002.086136 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46023.406962 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46023.406962 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34927.113424 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46652.725224 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 46647.508209 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34927.113424 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46652.725224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46647.508209 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214094 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45728.683992 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54802.476653 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54795.150812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54392.071650 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54392.071650 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45728.683992 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54640.642369 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54636.283063 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45728.683992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54640.642369 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54636.283063 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 78e7b43f1..3a71ce0c3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.631385 # Number of seconds simulated -sim_ticks 2631384990000 # Number of ticks simulated -final_tick 2631384990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.623386 # Number of seconds simulated +sim_ticks 2623386226000 # Number of ticks simulated +final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1011793 # Simulator instruction rate (inst/s) -host_op_rate 1011793 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1463043658 # Simulator tick rate (ticks/s) -host_mem_usage 219388 # Number of bytes of host memory used -host_seconds 1798.57 # Real time elapsed on the host +host_inst_rate 1789114 # Simulator instruction rate (inst/s) +host_op_rate 1789114 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2579177735 # Simulator tick rate (ticks/s) +host_mem_usage 217052 # Number of bytes of host memory used +host_seconds 1017.14 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137580288 # Number of bytes read from this memory -system.physmem.bytes_read::total 137631616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125367104 # Number of bytes read from this memory +system.physmem.bytes_read::total 125418432 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67105600 # Number of bytes written to this memory -system.physmem.bytes_written::total 67105600 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65156928 # Number of bytes written to this memory +system.physmem.bytes_written::total 65156928 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2149692 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2150494 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048525 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048525 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52284363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52303869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 25502008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 25502008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 25502008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52284363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77805877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 1958861 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959663 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018077 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018077 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47788276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47807841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24836956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24836956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24836956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5262769980 # number of cpu cycles simulated +system.cpu.numCycles 5246772452 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5262769980 # Number of busy cycles +system.cpu.num_busy_cycles 5246772452 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 612.470356 # Cycle average of tags in use +system.cpu.icache.tagsinuse 612.458646 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 612.470356 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.299058 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.299058 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.299052 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44120000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44120000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44120000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44120000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44120000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44120000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44182000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44182000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44182000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44182000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44182000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44182000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55012.468828 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55012.468828 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55012.468828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55012.468828 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55089.775561 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55089.775561 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55089.775561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55089.775561 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42516000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42516000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42516000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42516000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42516000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42516000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42578000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42578000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42578000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42578000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42578000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42578000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53012.468828 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53012.468828 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53089.775561 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53089.775561 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.tagsinuse 4079.313701 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40977019000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4079.313701 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995926 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995926 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151059345000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151059345000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57691387000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57691387000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 208750732000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 208750732000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 208750732000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 208750732000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143374726000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143374726000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377180000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57377180000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200751906000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200751906000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200751906000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20915.353925 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20915.353925 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30535.529714 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30535.529714 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22910.099439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22910.099439 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19851.358009 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19851.358009 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30369.222789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30369.222789 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22032.239528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389919 # number of writebacks -system.cpu.dcache.writebacks::total 3389919 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks +system.cpu.dcache.writebacks::total 3693497 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136614517000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 136614517000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53912747000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53912747000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190527264000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 190527264000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190527264000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 190527264000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128929898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53598540000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53598540000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182528438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182528438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -258,65 +258,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18915.353925 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18915.353925 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28535.529714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.529714 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20910.099439 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20910.099439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20910.099439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20910.099439 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17851.358009 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17851.358009 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28369.222789 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28369.222789 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2133721 # number of replacements -system.cpu.l2cache.tagsinuse 30159.988647 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8449191 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2163414 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.905490 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 496965874000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14375.657027 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 37.778500 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15746.553119 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.438710 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001153 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.480547 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.920410 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5861531 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5861531 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3389919 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3389919 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1100511 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1100511 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6962042 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6962042 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6962042 # number of overall hits -system.cpu.l2cache.overall_hits::total 6962042 # number of overall hits +system.cpu.l2cache.replacements 1926937 # number of replacements +system.cpu.l2cache.tagsinuse 30535.257456 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8959453 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1956729 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.578791 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.931862 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3693497 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108019 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108019 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7152873 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7152873 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7152873 # number of overall hits +system.cpu.l2cache.overall_hits::total 7152873 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1360883 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1361685 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 788809 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 788809 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1177560 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1178362 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 781301 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 781301 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2149692 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2150494 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1958861 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1959663 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2149692 # number of overall misses -system.cpu.l2cache.overall_misses::total 2150494 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41714000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70776793000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 70818507000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018317000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41018317000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 41714000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111795110000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 111836824000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 41714000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111795110000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 111836824000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958861 # number of overall misses +system.cpu.l2cache.overall_misses::total 1959663 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41776000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61258944000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61300720000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40629030000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40629030000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41776000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101887974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 101929750000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41776000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101887974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 101929750000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3389919 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3389919 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3693497 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3693497 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses @@ -326,27 +326,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 802 system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188425 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.188515 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417509 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.417509 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163042 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163135 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413536 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413536 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235926 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.235993 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214982 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.215051 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235926 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.235993 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52012.468828 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.992605 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52007.995241 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.315666 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.315666 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52012.468828 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.175625 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52005.178345 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52012.468828 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.175625 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52005.178345 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214982 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.215051 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52089.775561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52021.930093 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52021.976269 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.763725 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.763725 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52013.917699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52013.917699 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,52 +355,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1048525 # number of writebacks -system.cpu.l2cache.writebacks::total 1048525 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1018077 # number of writebacks +system.cpu.l2cache.writebacks::total 1018077 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360883 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1361685 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788809 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 788809 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177560 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178362 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781301 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 781301 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2149692 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2150494 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958861 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1959663 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2149692 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2150494 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32090000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54446197000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54478287000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31552609000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31552609000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32090000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85998806000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86030896000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32090000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85998806000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86030896000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958861 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959663 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32152000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47128224000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47160376000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31253418000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31253418000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78381642000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78413794000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32152000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78381642000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78413794000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188425 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188515 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417509 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417509 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163042 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163135 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413536 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413536 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235993 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.215051 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235993 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40012.468828 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.992605 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40007.995241 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.315666 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.315666 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40012.468828 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.175625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.178345 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40012.468828 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.175625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.178345 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.215051 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40089.775561 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.930093 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.976269 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.763725 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.763725 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index a3e0cc680..21ff71fb2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.473434 # Number of seconds simulated -sim_ticks 473433799500 # Number of ticks simulated -final_tick 473433799500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.515058 # Number of seconds simulated +sim_ticks 515058060000 # Number of ticks simulated +final_tick 515058060000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169995 # Simulator instruction rate (inst/s) -host_op_rate 189642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52106394 # Simulator tick rate (ticks/s) -host_mem_usage 499160 # Number of bytes of host memory used -host_seconds 9085.91 # Real time elapsed on the host -sim_insts 1544563083 # Number of instructions simulated -sim_ops 1723073895 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156296704 # Number of bytes read from this memory -system.physmem.bytes_read::total 156345088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71931712 # Number of bytes written to this memory -system.physmem.bytes_written::total 71931712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 756 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2442136 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2442892 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1123933 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1123933 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 102198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330134232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 330236430 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 102198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 102198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 151936157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 151936157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 151936157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 102198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330134232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 482172587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2442892 # Total number of read requests seen -system.physmem.writeReqs 1123933 # Total number of write requests seen -system.physmem.cpureqs 3566825 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 156345088 # Total number of bytes read from memory -system.physmem.bytesWritten 71931712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 156345088 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 71931712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1286 # Number of read reqs serviced by write Q +host_inst_rate 166099 # Simulator instruction rate (inst/s) +host_op_rate 185296 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55388247 # Simulator tick rate (ticks/s) +host_mem_usage 494292 # Number of bytes of host memory used +host_seconds 9299.05 # Real time elapsed on the host +sim_insts 1544563078 # Number of instructions simulated +sim_ops 1723073890 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 144392128 # Number of bytes read from this memory +system.physmem.bytes_read::total 144440448 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70617600 # Number of bytes written to this memory +system.physmem.bytes_written::total 70617600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2256127 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2256882 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1103400 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1103400 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 280341459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 280435274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 137106096 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 137106096 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 137106096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 280341459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 417541370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2256882 # Total number of read requests seen +system.physmem.writeReqs 1103400 # Total number of write requests seen +system.physmem.cpureqs 3360282 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 144440448 # Total number of bytes read from memory +system.physmem.bytesWritten 70617600 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 144440448 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70617600 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 637 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 151934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 156031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 154856 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 153024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 150249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 152372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 153472 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 154746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 153379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 151879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 152199 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 152305 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 150118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 153271 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 150713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 151058 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 70393 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 72288 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 71658 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 69978 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 69490 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 69799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 70024 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 70449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 69754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 69615 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 69971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 69698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 68976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 71736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 70217 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69887 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 140407 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 144367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 142491 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141453 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 138510 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 140931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 142120 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 141749 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 141832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 140373 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140948 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 141413 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 137790 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 141680 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 139536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 140645 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 70506 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69820 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 68968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 67927 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68673 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 68853 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68680 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 68439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 68530 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 68800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 68663 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 67351 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70531 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 69216 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69077 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 473433771000 # Total gap between requests +system.physmem.totGap 515058007000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2442892 # Categorize read packet sizes +system.physmem.readPktSize::6 2256882 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1123933 # categorize write packet sizes +system.physmem.writePktSize::6 1103400 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1613567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 411043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 122672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 76227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 63723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 50754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 28949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 23035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 15102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1580398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 450395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 158442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 66982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,60 +138,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 46512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 48422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 48759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 48833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 48858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 48865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 39045821973 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 121584903973 # Sum of mem lat for all requests -system.physmem.totBusLat 9766424000 # Total cycles spent in databus access -system.physmem.totBankLat 72772658000 # Total cycles spent in bank access -system.physmem.avgQLat 15991.86 # Average queueing delay per request -system.physmem.avgBankLat 29805.24 # Average bank access latency per request +system.physmem.totQLat 27231628654 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 103251704654 # Sum of mem lat for all requests +system.physmem.totBusLat 9024980000 # Total cycles spent in databus access +system.physmem.totBankLat 66995096000 # Total cycles spent in bank access +system.physmem.avgQLat 12069.45 # Average queueing delay per request +system.physmem.avgBankLat 29693.18 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 49797.10 # Average memory access latency -system.physmem.avgRdBW 330.24 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 151.94 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 330.24 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 151.94 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 45762.63 # Average memory access latency +system.physmem.avgRdBW 280.44 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 137.11 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 280.44 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 137.11 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.01 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.26 # Average read queue length over time -system.physmem.avgWrQLen 10.90 # Average write queue length over time -system.physmem.readRowHits 966664 # Number of row buffer hits during reads -system.physmem.writeRowHits 336338 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.93 # Row buffer hit rate for writes -system.physmem.avgGap 132732.55 # Average gap between requests +system.physmem.busUtil 2.61 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.20 # Average read queue length over time +system.physmem.avgWrQLen 11.32 # Average write queue length over time +system.physmem.readRowHits 919391 # Number of row buffer hits during reads +system.physmem.writeRowHits 189315 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 17.16 # Row buffer hit rate for writes +system.physmem.avgGap 153278.21 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,140 +235,142 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 946867600 # number of cpu cycles simulated +system.cpu.numCycles 1030116121 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 299593765 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 245452602 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16045022 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 170764551 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155662191 # Number of BTB hits +system.cpu.BPredUnit.lookups 307748972 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 253170818 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16168830 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 178836343 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 162524431 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18346296 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 201 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 291830558 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2150759454 # Number of instructions fetch has processed -system.cpu.fetch.Branches 299593765 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174008487 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 427702866 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 82463506 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 122599229 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 282801731 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5377782 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 908156186 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.634401 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.243337 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18394581 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 234 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 302711500 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2208582342 # Number of instructions fetch has processed +system.cpu.fetch.Branches 307748972 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 180919012 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 439713036 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 91477277 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 153604124 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 69 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 292882660 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6106896 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 969047070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.529561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.216174 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 480453401 52.90% 52.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 22859151 2.52% 55.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38736937 4.27% 59.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47688218 5.25% 64.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40498646 4.46% 69.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46746329 5.15% 74.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38999717 4.29% 78.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18064778 1.99% 80.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174109009 19.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 529334144 54.62% 54.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25043926 2.58% 57.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39264186 4.05% 61.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48337631 4.99% 66.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43062270 4.44% 70.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 47882627 4.94% 75.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39313310 4.06% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19335068 2.00% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 177473908 18.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 908156186 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316405 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.271447 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 320351849 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 103310609 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403372314 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15098642 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 66022772 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46034722 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2339352792 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2529 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 66022772 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 341796573 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 48717971 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14906 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 395855837 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55748127 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2282794185 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 39847 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4611517 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42695661 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2257537981 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10537280026 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10537275559 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4467 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706320026 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 551217955 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 838 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 835 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 129599333 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 622569059 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 218142237 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 84983278 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 64739003 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2182778805 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 865 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2010794421 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4810108 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 455220170 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1060725588 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 683 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 908156186 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.214150 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.929063 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 969047070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.298752 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.144013 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 334775915 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 131820236 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 409429631 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20003640 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 73017648 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46459880 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 721 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2395467722 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2521 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 73017648 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 358478616 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61310545 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17059 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 404218624 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 72004578 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2331266224 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 128849 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5208113 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58805545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2308002536 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10761064902 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10761060796 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4106 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706320018 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 601682518 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1074 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1071 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160130696 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 634128265 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 221560674 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 87711423 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 69100091 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2223438682 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1093 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2032725138 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5162970 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 495697928 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1172411676 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 912 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 969047070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.097654 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906175 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 247277493 27.23% 27.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 133932127 14.75% 41.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 156228000 17.20% 59.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 116195915 12.79% 71.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125706835 13.84% 85.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75923793 8.36% 94.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39533015 4.35% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10697910 1.18% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2661098 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 282916763 29.20% 29.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 152378116 15.72% 44.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 162831122 16.80% 61.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119917560 12.37% 74.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126106053 13.01% 87.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 74105592 7.65% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38169342 3.94% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10016302 1.03% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2606220 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 908156186 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 969047070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 703286 2.81% 2.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4771 0.02% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19012865 76.06% 78.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5274676 21.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 856823 3.47% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4485 0.02% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18914760 76.65% 80.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4900553 19.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1230823853 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 930532 0.05% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1244244744 61.21% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 933049 0.05% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued @@ -390,475 +392,475 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 30 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 585374477 29.11% 90.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193665439 9.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 593617066 29.20% 90.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193930151 9.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2010794421 # Type of FU issued -system.cpu.iq.rate 2.123628 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24995598 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4959550302 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2638184259 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1953078988 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2035789802 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 217 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63764603 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2032725138 # Type of FU issued +system.cpu.iq.rate 1.973297 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24676621 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012140 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5064336479 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2719325477 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1969225475 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 784 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 183 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2057401528 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63678179 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 136642278 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 284566 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 187935 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43295180 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 148201485 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 301622 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 191452 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46713618 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 386993 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3827005 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 66022772 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23145640 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1044628 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2182779773 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5713944 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 622569059 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 218142237 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 173655 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 44651 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 187935 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8601247 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10177350 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18778597 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1981378382 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 570935022 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29416039 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 73017648 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27244100 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1491546 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2223439933 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6134188 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 634128265 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 221560674 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1025 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 470403 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 82153 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 191452 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8679785 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10261943 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18941728 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2001081478 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 578449212 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 31643660 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 103 # number of nop insts executed -system.cpu.iew.exec_refs 761630934 # number of memory reference insts executed -system.cpu.iew.exec_branches 237544754 # Number of branches executed -system.cpu.iew.exec_stores 190695912 # Number of stores executed -system.cpu.iew.exec_rate 2.092561 # Inst execution rate -system.cpu.iew.wb_sent 1962075581 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1953079152 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1293757962 # num instructions producing a value -system.cpu.iew.wb_consumers 2065123050 # num instructions consuming a value +system.cpu.iew.exec_nop 158 # number of nop insts executed +system.cpu.iew.exec_refs 769422153 # number of memory reference insts executed +system.cpu.iew.exec_branches 239265351 # Number of branches executed +system.cpu.iew.exec_stores 190972941 # Number of stores executed +system.cpu.iew.exec_rate 1.942579 # Inst execution rate +system.cpu.iew.wb_sent 1978131551 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1969225658 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1302526017 # num instructions producing a value +system.cpu.iew.wb_consumers 2074719324 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.062674 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626480 # average fanout of values written-back +system.cpu.iew.wb_rate 1.911654 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.627808 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 459769347 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 182 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16044351 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 842133415 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.046082 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.757625 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 500462812 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 181 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16168149 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 896029423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.923010 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718948 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 351966566 41.79% 41.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194208080 23.06% 64.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73932281 8.78% 73.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35396184 4.20% 77.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18675547 2.22% 80.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 31087553 3.69% 83.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19760319 2.35% 86.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10744228 1.28% 87.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106362657 12.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 406862083 45.41% 45.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193059933 21.55% 66.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73977423 8.26% 75.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35390708 3.95% 79.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18895903 2.11% 81.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30453376 3.40% 84.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19841212 2.21% 86.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11401039 1.27% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106147746 11.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 842133415 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563101 # Number of instructions committed -system.cpu.commit.committedOps 1723073913 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 896029423 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563096 # Number of instructions committed +system.cpu.commit.committedOps 1723073908 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773838 # Number of memory references committed -system.cpu.commit.loads 485926781 # Number of loads committed +system.cpu.commit.refs 660773836 # Number of memory references committed +system.cpu.commit.loads 485926780 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462438 # Number of branches committed +system.cpu.commit.branches 213462437 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941889 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941885 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106362657 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106147746 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2918613419 # The number of ROB reads -system.cpu.rob.rob_writes 4431868415 # The number of ROB writes -system.cpu.timesIdled 795856 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 38711414 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563083 # Number of Instructions Simulated -system.cpu.committedOps 1723073895 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563083 # Number of Instructions Simulated -system.cpu.cpi 0.613033 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.613033 # CPI: Total CPI of All Threads -system.cpu.ipc 1.631234 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.631234 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9926647662 # number of integer regfile reads -system.cpu.int_regfile_writes 1933066427 # number of integer regfile writes -system.cpu.fp_regfile_reads 168 # number of floating regfile reads -system.cpu.fp_regfile_writes 190 # number of floating regfile writes -system.cpu.misc_regfile_reads 2888912367 # number of misc regfile reads -system.cpu.misc_regfile_writes 148 # number of misc regfile writes -system.cpu.icache.replacements 20 # number of replacements -system.cpu.icache.tagsinuse 632.636403 # Cycle average of tags in use -system.cpu.icache.total_refs 282800594 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 786 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 359797.193384 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3013417798 # The number of ROB reads +system.cpu.rob.rob_writes 4520246386 # The number of ROB writes +system.cpu.timesIdled 1016810 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 61069051 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563078 # Number of Instructions Simulated +system.cpu.committedOps 1723073890 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563078 # Number of Instructions Simulated +system.cpu.cpi 0.666930 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.666930 # CPI: Total CPI of All Threads +system.cpu.ipc 1.499407 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.499407 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10019536016 # number of integer regfile reads +system.cpu.int_regfile_writes 1949927429 # number of integer regfile writes +system.cpu.fp_regfile_reads 198 # number of floating regfile reads +system.cpu.fp_regfile_writes 204 # number of floating regfile writes +system.cpu.misc_regfile_reads 2950890294 # number of misc regfile reads +system.cpu.misc_regfile_writes 146 # number of misc regfile writes +system.cpu.icache.replacements 21 # number of replacements +system.cpu.icache.tagsinuse 635.874030 # Cycle average of tags in use +system.cpu.icache.total_refs 292881421 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 787 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 372149.200762 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 632.636403 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.308904 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.308904 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 282800594 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 282800594 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 282800594 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 282800594 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 282800594 # number of overall hits -system.cpu.icache.overall_hits::total 282800594 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1137 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1137 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1137 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1137 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1137 # number of overall misses -system.cpu.icache.overall_misses::total 1137 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39598000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39598000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39598000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39598000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39598000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39598000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 282801731 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 282801731 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 282801731 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 282801731 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 282801731 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 282801731 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 635.874030 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310485 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310485 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 292881421 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 292881421 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 292881421 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 292881421 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 292881421 # number of overall hits +system.cpu.icache.overall_hits::total 292881421 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1239 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1239 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1239 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1239 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1239 # number of overall misses +system.cpu.icache.overall_misses::total 1239 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62929999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62929999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62929999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62929999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62929999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62929999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 292882660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 292882660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 292882660 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 292882660 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 292882660 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 292882660 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34826.737027 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34826.737027 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34826.737027 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34826.737027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34826.737027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34826.737027 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50790.959645 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50790.959645 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50790.959645 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50790.959645 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 213 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 351 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 351 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 351 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 351 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 786 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 786 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 786 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 786 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 786 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28796000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28796000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28796000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28796000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28796000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28796000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 452 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 452 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 452 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 452 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 452 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 452 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 787 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 787 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 787 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42672499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42672499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42672499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42672499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42672499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42672499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36636.132316 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36636.132316 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36636.132316 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36636.132316 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36636.132316 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36636.132316 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54221.726811 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54221.726811 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9616903 # number of replacements -system.cpu.dcache.tagsinuse 4087.861296 # Cycle average of tags in use -system.cpu.dcache.total_refs 660505517 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9620999 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.652488 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3324501000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.861296 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998013 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998013 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 492433938 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 492433938 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168071407 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168071407 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 99 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 99 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 73 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 73 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 660505345 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 660505345 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 660505345 # number of overall hits -system.cpu.dcache.overall_hits::total 660505345 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10054191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10054191 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4514640 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4514640 # number of WriteReq misses +system.cpu.dcache.replacements 9616996 # number of replacements +system.cpu.dcache.tagsinuse 4088.070177 # Cycle average of tags in use +system.cpu.dcache.total_refs 662383558 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9621092 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.847025 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3431633000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4088.070177 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998064 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998064 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 495328808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 495328808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167054576 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167054576 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 102 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 102 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 72 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 72 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 662383384 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 662383384 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 662383384 # number of overall hits +system.cpu.dcache.overall_hits::total 662383384 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11493898 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11493898 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5531471 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5531471 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 14568831 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 14568831 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 14568831 # number of overall misses -system.cpu.dcache.overall_misses::total 14568831 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 192605585000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 192605585000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 133759941491 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 133759941491 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 146500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 146500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 326365526491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 326365526491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 326365526491 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 326365526491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 502488129 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 502488129 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17025369 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17025369 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17025369 # number of overall misses +system.cpu.dcache.overall_misses::total 17025369 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 300469698500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 300469698500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 217116494201 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 217116494201 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 190500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 190500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 517586192701 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 517586192701 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 517586192701 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 517586192701 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 506822706 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 506822706 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 102 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 102 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 73 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 73 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 675074176 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 675074176 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 675074176 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 675074176 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026159 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026159 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.029412 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.029412 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021581 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021581 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021581 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021581 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19156.746177 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19156.746177 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29628.041547 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29628.041547 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22401.627591 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22401.627591 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22401.627591 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22401.627591 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1880438 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 248831 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 88187 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1969 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.323302 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 126.374302 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 105 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 105 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 72 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 72 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 679408753 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 679408753 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 679408753 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 679408753 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022678 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022678 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032051 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032051 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.028571 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.028571 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025059 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025059 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025059 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025059 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26141.670867 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26141.670867 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39251.131245 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39251.131245 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30400.879576 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30400.879576 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30400.879576 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30400.879576 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19937535 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 989836 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1174592 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64547 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.974009 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15.335120 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3473899 # number of writebacks -system.cpu.dcache.writebacks::total 3473899 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2327206 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2327206 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2620625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2620625 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3785750 # number of writebacks +system.cpu.dcache.writebacks::total 3785750 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3766794 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3766794 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3637483 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3637483 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4947831 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4947831 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4947831 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4947831 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7726985 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7726985 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894015 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1894015 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9621000 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9621000 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9621000 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9621000 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100672222000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 100672222000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58875647012 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 58875647012 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 159547869012 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 159547869012 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 159547869012 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 159547869012 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015377 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7404277 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7404277 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7404277 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7404277 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7727104 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7727104 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893988 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893988 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9621092 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9621092 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9621092 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9621092 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171327843500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171327843500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71936813831 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71936813831 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 243264657331 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 243264657331 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 243264657331 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 243264657331 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015246 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015246 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014252 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014252 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014252 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014252 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13028.655032 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13028.655032 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31085.100705 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31085.100705 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16583.293734 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16583.293734 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16583.293734 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16583.293734 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014161 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014161 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014161 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014161 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22172.322710 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22172.322710 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37981.662941 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37981.662941 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25284.516283 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25284.516283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25284.516283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25284.516283 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2427272 # number of replacements -system.cpu.l2cache.tagsinuse 31171.716737 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8744168 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2456984 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.558903 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 80002919000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14002.042506 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 15.065518 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17154.608713 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.427308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000460 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.523517 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.951285 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6115863 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6115892 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3473899 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3473899 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1062992 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1062992 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7178855 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7178884 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7178855 # number of overall hits -system.cpu.l2cache.overall_hits::total 7178884 # number of overall hits +system.cpu.l2cache.replacements 2224194 # number of replacements +system.cpu.l2cache.tagsinuse 31538.307180 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9258938 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2253968 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.107839 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 20485728502 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14439.228019 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 20.648477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17078.430684 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440650 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000630 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.521192 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.962473 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6299217 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6299247 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3785750 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3785750 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1065742 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1065742 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7364959 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7364989 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7364959 # number of overall hits +system.cpu.l2cache.overall_hits::total 7364989 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1611122 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1611879 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 831023 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 831023 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1427887 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1428644 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 828246 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 828246 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 757 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2442145 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2442902 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2256133 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2256890 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 757 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2442145 # number of overall misses -system.cpu.l2cache.overall_misses::total 2442902 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27934500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 84953945000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 84981879500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55209394500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 55209394500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27934500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 140163339500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 140191274000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27934500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 140163339500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 140191274000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 786 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7726985 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7727771 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3473899 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3473899 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894015 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1894015 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 786 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9621000 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9621786 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 786 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9621000 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9621786 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963104 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208506 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.208583 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438763 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.438763 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963104 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.253835 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.253893 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963104 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.253835 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.253893 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36901.585205 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52729.678448 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52722.244970 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66435.459067 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66435.459067 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36901.585205 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57393.537034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 57387.187042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36901.585205 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57393.537034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 57387.187042 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1390172 # number of cycles access was blocked +system.cpu.l2cache.overall_misses::cpu.data 2256133 # number of overall misses +system.cpu.l2cache.overall_misses::total 2256890 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41571500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98780136000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98821707500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58846759000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 58846759000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41571500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 157626895000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 157668466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41571500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 157626895000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 157668466500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 787 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7727104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7727891 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3785750 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3785750 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893988 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893988 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 787 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9621092 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9621879 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 787 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9621092 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9621879 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184789 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.184869 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437303 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.437303 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961881 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.234499 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.234558 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961881 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.234499 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.234558 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54916.116248 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69179.238973 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69171.681329 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71049.855961 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71049.855961 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54916.116248 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69865.958700 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69860.944264 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54916.116248 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69865.958700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69860.944264 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 31316 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 44.391749 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1123933 # number of writebacks -system.cpu.l2cache.writebacks::total 1123933 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 756 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611113 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1611869 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 831023 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 831023 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 756 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2442136 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2442892 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 756 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2442136 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2442892 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25190143 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 79130491462 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79155681605 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 52276530586 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 52276530586 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25190143 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131407022048 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 131432212191 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25190143 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131407022048 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 131432212191 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208505 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208581 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438763 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438763 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253834 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.253892 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253834 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.253892 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33320.294974 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49115.419876 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49108.011634 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62906.237957 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62906.237957 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33320.294974 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53808.232649 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53801.892262 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33320.294974 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53808.232649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53801.892262 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1103400 # number of writebacks +system.cpu.l2cache.writebacks::total 1103400 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1427881 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1428636 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 828246 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 828246 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2256127 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2256882 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2256127 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2256882 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31971694 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80731453067 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80763424761 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48402066091 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48402066091 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31971694 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 129133519158 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 129165490852 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31971694 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 129133519158 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 129165490852 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184789 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184868 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437303 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437303 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.234498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.234557 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.234498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.234557 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42346.614570 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56539.342611 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56531.842093 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58439.239177 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58439.239177 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42346.614570 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57236.812980 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57231.831727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42346.614570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57236.812980 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57231.831727 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 49ea5f586..6ff1664e3 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.399400 # Number of seconds simulated -sim_ticks 2399400439000 # Number of ticks simulated -final_tick 2399400439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.391205 # Number of seconds simulated +sim_ticks 2391205115000 # Number of ticks simulated +final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 994913 # Simulator instruction rate (inst/s) -host_op_rate 1110332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1551375376 # Simulator tick rate (ticks/s) -host_mem_usage 233816 # Number of bytes of host memory used -host_seconds 1546.63 # Real time elapsed on the host +host_inst_rate 1213159 # Simulator instruction rate (inst/s) +host_op_rate 1353897 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1885227488 # Simulator tick rate (ticks/s) +host_mem_usage 231376 # Number of bytes of host memory used +host_seconds 1268.39 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137819840 # Number of bytes read from this memory -system.physmem.bytes_read::total 137859264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory +system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67221184 # Number of bytes written to this memory -system.physmem.bytes_written::total 67221184 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory +system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2153435 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2154051 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050331 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050331 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 57439283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 57455713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 28015825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 28015825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 28015825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 57439283 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 85471539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4798800878 # number of cpu cycles simulated +system.cpu.numCycles 4782410230 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759601 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 660773815 # nu system.cpu.num_load_insts 485926769 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4798800878 # Number of busy cycles +system.cpu.num_busy_cycles 4782410230 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 7 # number of replacements -system.cpu.icache.tagsinuse 514.980115 # Cycle average of tags in use +system.cpu.icache.tagsinuse 514.976015 # Cycle average of tags in use system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 514.980115 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.251455 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.251455 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.251453 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34189000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34189000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34189000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34189000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34189000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34189000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53587.774295 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53587.774295 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53587.774295 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53587.774295 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53587.774295 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53587.774295 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32913000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32913000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32913000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32913000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32913000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32913000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51587.774295 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51587.774295 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51587.774295 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51587.774295 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51587.774295 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51587.774295 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9111140 # number of replacements -system.cpu.dcache.tagsinuse 4083.564925 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25914432000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4083.564925 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996964 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996964 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115236 # n system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151247261000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151247261000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57698979000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57698979000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 208946240000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 208946240000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 208946240000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 208946240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20930.727931 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20930.727931 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30542.312438 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30542.312438 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22922.746048 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22922.746048 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22922.746048 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22922.746048 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3385547 # number of writebacks -system.cpu.dcache.writebacks::total 3385547 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks +system.cpu.dcache.writebacks::total 3697418 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136795087000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 136795087000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53920681000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53920681000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190715768000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 190715768000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190715768000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 190715768000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18930.727931 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18930.727931 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28542.312438 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28542.312438 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20922.746048 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20922.746048 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20922.746048 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20922.746048 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2138446 # number of replacements -system.cpu.l2cache.tagsinuse 30623.782374 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8443619 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2168151 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.894387 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 435858689000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14787.769987 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 15.768959 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15820.243429 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.451287 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000481 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.482796 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.934564 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 1926075 # number of replacements +system.cpu.l2cache.tagsinuse 30987.094489 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8967572 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1955843 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.585016 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.945651 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 5861680 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5861702 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3385547 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3385547 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1100121 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1100121 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 6961801 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6961823 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7157078 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7157100 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 6961801 # number of overall hits -system.cpu.l2cache.overall_hits::total 6961823 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7157078 # number of overall hits +system.cpu.l2cache.overall_hits::total 7157100 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1364407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1365023 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 789028 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 789028 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1177282 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1177898 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 780876 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 780876 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2153435 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2154051 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1958158 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1958774 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2153435 # number of overall misses -system.cpu.l2cache.overall_misses::total 2154051 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32055000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70952200000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 70984255000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41030322000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41030322000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32055000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111982522000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 112014577000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32055000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111982522000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 112014577000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses +system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32099000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61225555000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61257654000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608829000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40608829000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32099000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 101866483000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32099000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 101866483000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3385547 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3385547 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses @@ -347,27 +347,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 638 system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188817 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.188885 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417663 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.417663 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.236246 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.236297 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.236246 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.236297 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52037.337662 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.225142 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52002.240988 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.097553 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.097553 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52037.337662 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.811989 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52001.822148 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52037.337662 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.811989 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52001.822148 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -376,52 +376,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050331 # number of writebacks -system.cpu.l2cache.writebacks::total 1050331 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks +system.cpu.l2cache.writebacks::total 1017198 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1364407 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1365023 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 789028 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 789028 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2153435 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2154051 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2153435 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2154051 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24663000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54579316000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54603979000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31561986000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31561986000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24663000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86141302000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86165965000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24663000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86141302000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86165965000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188817 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188885 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417663 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417663 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.236297 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.236297 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40037.337662 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.225142 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.240988 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.097553 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.097553 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40037.337662 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.811989 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.822148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40037.337662 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.811989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.822148 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 04d920eee..21fe18ab3 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.891582 # Number of seconds simulated -sim_ticks 5891581948000 # Number of ticks simulated -final_tick 5891581948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.882581 # Number of seconds simulated +sim_ticks 5882580524000 # Number of ticks simulated +final_tick 5882580524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 701685 # Simulator instruction rate (inst/s) -host_op_rate 1093289 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1374310212 # Simulator tick rate (ticks/s) -host_mem_usage 228764 # Number of bytes of host memory used -host_seconds 4286.94 # Real time elapsed on the host +host_inst_rate 472403 # Simulator instruction rate (inst/s) +host_op_rate 736047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 923827707 # Simulator tick rate (ticks/s) +host_mem_usage 227772 # Number of bytes of host memory used +host_seconds 6367.62 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862594 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory -system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory +system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67393856 # Number of bytes written to this memory -system.physmem.bytes_written::total 67393856 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory +system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2172556 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2173231 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 23600382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 23607714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11439009 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11439009 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11439009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 23600382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35046723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 1958234 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1958909 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018421 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11783163896 # number of cpu cycles simulated +system.cpu.numCycles 11765161048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 1677713082 # nu system.cpu.num_load_insts 1239184745 # Number of load instructions system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11783163896 # Number of busy cycles +system.cpu.num_busy_cycles 11765161048 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 555.725129 # Cycle average of tags in use +system.cpu.icache.tagsinuse 555.705054 # Cycle average of tags in use system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 555.725129 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.271350 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.271350 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.271340 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37130000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37130000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37130000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37130000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37130000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37130000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55007.407407 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55007.407407 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55007.407407 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55007.407407 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675 system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35780000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35780000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35780000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35780000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35780000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35780000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35806000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 35806000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35806000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 35806000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35806000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 35806000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53007.407407 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53007.407407 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.604436 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58853994000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.604436 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997218 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997218 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 58853920000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151971083000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151971083000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57741123000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57741123000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 209712206000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 209712206000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 209712206000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 209712206000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21040.321064 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21040.321064 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30553.655440 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30553.655440 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23013.238152 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23013.238152 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3375759 # number of writebacks -system.cpu.dcache.writebacks::total 3375759 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks +system.cpu.dcache.writebacks::total 3697956 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525383000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525383000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961469000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961469000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486852000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191486852000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486852000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191486852000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses @@ -226,65 +226,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.321064 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.321064 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.655440 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.655440 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2158210 # number of replacements -system.cpu.l2cache.tagsinuse 30849.854795 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1315499445000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14663.466685 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 21.611649 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16164.776461 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.447493 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000660 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.493310 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.941463 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5840135 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5840135 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3375759 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3375759 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1099986 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1099986 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6940121 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6940121 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6940121 # number of overall hits -system.cpu.l2cache.overall_hits::total 6940121 # number of overall hits +system.cpu.l2cache.replacements 1926197 # number of replacements +system.cpu.l2cache.tagsinuse 31136.249390 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 340768633000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15396.795539 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15713.812836 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.950203 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3697956 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108532 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108532 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7154443 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7154443 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7154443 # number of overall hits +system.cpu.l2cache.overall_hits::total 7154443 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1382715 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1383390 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 789841 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 789841 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1176939 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1177614 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 781295 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2172556 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2173231 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1958234 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1958909 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2172556 # number of overall misses -system.cpu.l2cache.overall_misses::total 2173231 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35105000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71901183000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71936288000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41071782000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41071782000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35105000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112972965000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 113008070000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35105000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112972965000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 113008070000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958234 # number of overall misses +system.cpu.l2cache.overall_misses::total 1958909 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35131000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61200881000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61236012000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40627414000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40627414000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35131000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101828295000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 101863426000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35131000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101828295000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 101863426000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3375759 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3375759 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3697956 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3697956 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses @@ -294,27 +294,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 675 system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.191436 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.191512 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417944 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.417944 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162947 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163025 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413421 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413421 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.238410 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.238467 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214891 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214949 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.238410 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.238467 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52007.407407 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.002170 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.005783 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.063304 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.063304 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.026688 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.026688 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52045.925926 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.045032 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.071331 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.094715 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.094715 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.080657 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.080657 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,52 +323,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1053029 # number of writebacks -system.cpu.l2cache.writebacks::total 1053029 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1018421 # number of writebacks +system.cpu.l2cache.writebacks::total 1018421 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1382715 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1383390 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 789841 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 789841 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1176939 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1177614 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2172556 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2173231 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958234 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1958909 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2172556 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2173231 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27005000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55308603000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55335608000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31593690000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31593690000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27005000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86902293000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86929298000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27005000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86902293000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86929298000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27031000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47077613000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47104644000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31251874000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31251874000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27031000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78329487000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78356518000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27031000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78329487000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78356518000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.191436 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191512 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417944 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417944 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413421 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413421 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.238467 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.238467 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40007.407407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.002170 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.005783 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.063304 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.063304 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |