diff options
Diffstat (limited to 'tests/long/se/60.bzip2')
10 files changed, 2742 insertions, 2504 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 8e313893e..25a59730e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.181972 # Number of seconds simulated -sim_ticks 1181971516500 # Number of ticks simulated -final_tick 1181971516500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.182263 # Number of seconds simulated +sim_ticks 1182263011500 # Number of ticks simulated +final_tick 1182263011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 316302 # Simulator instruction rate (inst/s) -host_op_rate 316302 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 204699977 # Simulator tick rate (ticks/s) -host_mem_usage 267460 # Number of bytes of host memory used -host_seconds 5774.17 # Real time elapsed on the host +host_inst_rate 338169 # Simulator instruction rate (inst/s) +host_op_rate 338169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 218905814 # Simulator tick rate (ticks/s) +host_mem_usage 291920 # Number of bytes of host memory used +host_seconds 5400.78 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 125504768 # Number of bytes read from this memory -system.physmem.bytes_read::total 125504768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65167040 # Number of bytes written to this memory -system.physmem.bytes_written::total 65167040 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1961012 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961012 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018235 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018235 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106182566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 106182566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 51873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 55134188 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 55134188 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 55134188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106182566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 161316754 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961012 # Number of read requests accepted -system.physmem.writeReqs 1018235 # Number of write requests accepted -system.physmem.readBursts 1961012 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1018235 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125424512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 80256 # Total number of bytes read from write queue -system.physmem.bytesWritten 65165696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125504768 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65167040 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1254 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 125507520 # Number of bytes read from this memory +system.physmem.bytes_read::total 125507520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65168128 # Number of bytes written to this memory +system.physmem.bytes_written::total 65168128 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1961055 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961055 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018252 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018252 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 106158713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106158713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 51752 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 51752 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 55121515 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55121515 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55121515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106158713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 161280228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961055 # Number of read requests accepted +system.physmem.writeReqs 1018252 # Number of write requests accepted +system.physmem.readBursts 1961055 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018252 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125426368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81152 # Total number of bytes read from write queue +system.physmem.bytesWritten 65166528 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125507520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65168128 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1268 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118750 # Per bank write bursts -system.physmem.perBankRdBursts::1 114103 # Per bank write bursts -system.physmem.perBankRdBursts::2 116233 # Per bank write bursts -system.physmem.perBankRdBursts::3 117780 # Per bank write bursts -system.physmem.perBankRdBursts::4 117833 # Per bank write bursts -system.physmem.perBankRdBursts::5 117521 # Per bank write bursts -system.physmem.perBankRdBursts::6 119886 # Per bank write bursts -system.physmem.perBankRdBursts::7 124520 # Per bank write bursts -system.physmem.perBankRdBursts::8 126974 # Per bank write bursts -system.physmem.perBankRdBursts::9 130087 # Per bank write bursts -system.physmem.perBankRdBursts::10 128649 # Per bank write bursts -system.physmem.perBankRdBursts::11 130350 # Per bank write bursts -system.physmem.perBankRdBursts::12 126060 # Per bank write bursts -system.physmem.perBankRdBursts::13 125237 # Per bank write bursts -system.physmem.perBankRdBursts::14 122580 # Per bank write bursts -system.physmem.perBankRdBursts::15 123195 # Per bank write bursts -system.physmem.perBankWrBursts::0 61223 # Per bank write bursts +system.physmem.perBankRdBursts::0 118756 # Per bank write bursts +system.physmem.perBankRdBursts::1 114094 # Per bank write bursts +system.physmem.perBankRdBursts::2 116231 # Per bank write bursts +system.physmem.perBankRdBursts::3 117777 # Per bank write bursts +system.physmem.perBankRdBursts::4 117824 # Per bank write bursts +system.physmem.perBankRdBursts::5 117524 # Per bank write bursts +system.physmem.perBankRdBursts::6 119883 # Per bank write bursts +system.physmem.perBankRdBursts::7 124524 # Per bank write bursts +system.physmem.perBankRdBursts::8 126980 # Per bank write bursts +system.physmem.perBankRdBursts::9 130091 # Per bank write bursts +system.physmem.perBankRdBursts::10 128645 # Per bank write bursts +system.physmem.perBankRdBursts::11 130349 # Per bank write bursts +system.physmem.perBankRdBursts::12 126066 # Per bank write bursts +system.physmem.perBankRdBursts::13 125260 # Per bank write bursts +system.physmem.perBankRdBursts::14 122596 # Per bank write bursts +system.physmem.perBankRdBursts::15 123187 # Per bank write bursts +system.physmem.perBankWrBursts::0 61220 # Per bank write bursts system.physmem.perBankWrBursts::1 61486 # Per bank write bursts -system.physmem.perBankWrBursts::2 60566 # Per bank write bursts -system.physmem.perBankWrBursts::3 61239 # Per bank write bursts -system.physmem.perBankWrBursts::4 61662 # Per bank write bursts -system.physmem.perBankWrBursts::5 63100 # Per bank write bursts -system.physmem.perBankWrBursts::6 64151 # Per bank write bursts -system.physmem.perBankWrBursts::7 65612 # Per bank write bursts -system.physmem.perBankWrBursts::8 65333 # Per bank write bursts -system.physmem.perBankWrBursts::9 65776 # Per bank write bursts -system.physmem.perBankWrBursts::10 65296 # Per bank write bursts -system.physmem.perBankWrBursts::11 65642 # Per bank write bursts -system.physmem.perBankWrBursts::12 64167 # Per bank write bursts -system.physmem.perBankWrBursts::13 64207 # Per bank write bursts -system.physmem.perBankWrBursts::14 64568 # Per bank write bursts -system.physmem.perBankWrBursts::15 64186 # Per bank write bursts +system.physmem.perBankWrBursts::2 60567 # Per bank write bursts +system.physmem.perBankWrBursts::3 61241 # Per bank write bursts +system.physmem.perBankWrBursts::4 61658 # Per bank write bursts +system.physmem.perBankWrBursts::5 63102 # Per bank write bursts +system.physmem.perBankWrBursts::6 64150 # Per bank write bursts +system.physmem.perBankWrBursts::7 65615 # Per bank write bursts +system.physmem.perBankWrBursts::8 65332 # Per bank write bursts +system.physmem.perBankWrBursts::9 65779 # Per bank write bursts +system.physmem.perBankWrBursts::10 65299 # Per bank write bursts +system.physmem.perBankWrBursts::11 65643 # Per bank write bursts +system.physmem.perBankWrBursts::12 64166 # Per bank write bursts +system.physmem.perBankWrBursts::13 64211 # Per bank write bursts +system.physmem.perBankWrBursts::14 64571 # Per bank write bursts +system.physmem.perBankWrBursts::15 64187 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1181971406500 # Total gap between requests +system.physmem.totGap 1182262901500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961012 # Read request sizes (log2) +system.physmem.readPktSize::6 1961055 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018235 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1833489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126251 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018252 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1833329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126440 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,30 +140,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 59765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 59757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 59783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 59794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 59834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 59898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 29905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -189,26 +189,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1832879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.982912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.202772 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.375131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1452262 79.23% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 263657 14.38% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49315 2.69% 96.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20815 1.14% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12975 0.71% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7226 0.39% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5262 0.29% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4170 0.23% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 17197 0.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1832879 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59235 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.083110 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 163.258366 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59198 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 10 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1836557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.775367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.104101 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.072591 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1457072 79.34% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 262826 14.31% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49283 2.68% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20722 1.13% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12908 0.70% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7083 0.39% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5369 0.29% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4081 0.22% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17213 0.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1836557 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59478 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.947897 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 162.231607 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59437 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 16 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 8 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes @@ -217,94 +217,103 @@ system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # R system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59235 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59235 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.189398 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.153834 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.107502 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 25894 43.71% 43.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1328 2.24% 45.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 27547 46.50% 92.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3948 6.66% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 431 0.73% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 64 0.11% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 18 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59235 # Writes before turning the bus around for reads -system.physmem.totQLat 36544529000 # Total ticks spent queuing -system.physmem.totMemAccLat 73289991500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798790000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18647.47 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59478 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59478 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.119389 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.083537 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.112675 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 28008 47.09% 47.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1262 2.12% 49.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 25918 43.58% 92.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3789 6.37% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 422 0.71% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 60 0.10% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59478 # Writes before turning the bus around for reads +system.physmem.totQLat 36992521000 # Total ticks spent queuing +system.physmem.totMemAccLat 73738527250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798935000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18875.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37397.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 106.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 55.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 106.18 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 55.13 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37625.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 106.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 55.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.16 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 55.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.26 # Data bus utilization in percentage system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.43 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.78 # Average write queue length when enqueuing -system.physmem.readRowHits 729927 # Number of row buffer hits during reads -system.physmem.writeRowHits 415160 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.77 # Row buffer hit rate for writes -system.physmem.avgGap 396734.95 # Average gap between requests -system.physmem.pageHitRate 38.45 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 385912942500 # Time in different power states -system.physmem.memoryStateTime::REF 39468520000 # Time in different power states +system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing +system.physmem.readRowHits 727653 # Number of row buffer hits during reads +system.physmem.writeRowHits 413795 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.13 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.64 # Row buffer hit rate for writes +system.physmem.avgGap 396824.80 # Average gap between requests +system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 385836572500 # Time in different power states +system.physmem.memoryStateTime::REF 39478140000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 756587133750 # Time in different power states +system.physmem.memoryStateTime::ACT 756941975000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 161316754 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1181581 # Transaction distribution -system.membus.trans_dist::ReadResp 1181581 # Transaction distribution -system.membus.trans_dist::Writeback 1018235 # Transaction distribution -system.membus.trans_dist::ReadExReq 779431 # Transaction distribution -system.membus.trans_dist::ReadExResp 779431 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940259 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940259 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190671808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190671808 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190671808 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11933364500 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 1181608 # Transaction distribution +system.membus.trans_dist::ReadResp 1181608 # Transaction distribution +system.membus.trans_dist::Writeback 1018252 # Transaction distribution +system.membus.trans_dist::ReadExReq 779447 # Transaction distribution +system.membus.trans_dist::ReadExResp 779447 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940362 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940362 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190675648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190675648 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2979307 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2979307 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2979307 # Request fanout histogram +system.membus.reqLayer0.occupancy 11933178500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18494109500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18493465250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 244428250 # Number of BP lookups -system.cpu.branchPred.condPredicted 184893435 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15662948 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 166307436 # Number of BTB lookups -system.cpu.branchPred.BTBHits 163975175 # Number of BTB hits +system.cpu.branchPred.lookups 244422779 # Number of BP lookups +system.cpu.branchPred.condPredicted 184893031 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15656805 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 166159806 # Number of BTB lookups +system.cpu.branchPred.BTBHits 163963467 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.597621 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18313183 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 99860 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.678177 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18313255 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 100190 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452570396 # DTB read hits -system.cpu.dtb.read_misses 4982513 # DTB read misses +system.cpu.dtb.read_hits 452570621 # DTB read hits +system.cpu.dtb.read_misses 4982980 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457552909 # DTB read accesses -system.cpu.dtb.write_hits 161353452 # DTB write hits -system.cpu.dtb.write_misses 1708793 # DTB write misses +system.cpu.dtb.read_accesses 457553601 # DTB read accesses +system.cpu.dtb.write_hits 161352620 # DTB write hits +system.cpu.dtb.write_misses 1708824 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163062245 # DTB write accesses -system.cpu.dtb.data_hits 613923848 # DTB hits -system.cpu.dtb.data_misses 6691306 # DTB misses +system.cpu.dtb.write_accesses 163061444 # DTB write accesses +system.cpu.dtb.data_hits 613923241 # DTB hits +system.cpu.dtb.data_misses 6691804 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620615154 # DTB accesses -system.cpu.itb.fetch_hits 591487986 # ITB hits +system.cpu.dtb.data_accesses 620615045 # DTB accesses +system.cpu.itb.fetch_hits 591467838 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 591488005 # ITB accesses +system.cpu.itb.fetch_accesses 591467857 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -318,68 +327,68 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2363943033 # number of cpu cycles simulated +system.cpu.numCycles 2364526023 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 49642925 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 49659953 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.294334 # CPI: cycles per instruction -system.cpu.ipc 0.772598 # IPC: instructions per cycle -system.cpu.tickCycles 2043545366 # Number of cycles that the object actually ticked -system.cpu.idleCycles 320397667 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.294653 # CPI: cycles per instruction +system.cpu.ipc 0.772408 # IPC: instructions per cycle +system.cpu.tickCycles 2043503290 # Number of cycles that the object actually ticked +system.cpu.idleCycles 321022733 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 750.580892 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 591487028 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 617418.609603 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 749.760915 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 591466882 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 956 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 618689.207113 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 750.580892 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.366495 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.366495 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 749.760915 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366094 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366094 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 953 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1182976930 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1182976930 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 591487028 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 591487028 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 591487028 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 591487028 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 591487028 # number of overall hits -system.cpu.icache.overall_hits::total 591487028 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses -system.cpu.icache.overall_misses::total 958 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 69768750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 69768750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 69768750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 69768750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 69768750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 69768750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 591487986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 591487986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 591487986 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 591487986 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 591487986 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 591487986 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 872 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.465332 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1182936632 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1182936632 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 591466882 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 591466882 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 591466882 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 591466882 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 591466882 # number of overall hits +system.cpu.icache.overall_hits::total 591466882 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 956 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 956 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 956 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 956 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 956 # number of overall misses +system.cpu.icache.overall_misses::total 956 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 70103250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 70103250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 70103250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 70103250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 70103250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 70103250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 591467838 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 591467838 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 591467838 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 591467838 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 591467838 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 591467838 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72827.505219 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72827.505219 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72827.505219 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72827.505219 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72827.505219 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72827.505219 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73329.759414 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73329.759414 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73329.759414 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73329.759414 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73329.759414 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73329.759414 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,62 +397,71 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67467250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 67467250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67467250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 67467250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67467250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 67467250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 956 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 956 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 956 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 956 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 956 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 956 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67802750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 67802750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67802750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 67802750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67802750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 67802750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70425.104384 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70425.104384 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70425.104384 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70425.104384 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70425.104384 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70425.104384 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70923.378661 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70923.378661 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70923.378661 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70923.378661 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70923.378661 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70923.378661 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 694575222 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7239698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887316 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887316 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952725 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954641 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455674 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482432 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.938106 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29805 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -451,60 +469,60 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1232 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12869 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15516 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 106466413 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 106466413 # 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Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 16715078000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.551150 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.996228 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996228 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.554959 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.996229 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996229 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1617 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1616 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2312 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 64 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1227941810 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1227941810 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 441389836 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 441389836 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 158490339 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158490339 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 599880175 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 599880175 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 599880175 # 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number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 278864044500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 278864044500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 278864044500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 278864044500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 448679375 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 448679375 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1227940890 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1227940890 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 441389342 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 441389342 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 158490221 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158490221 # 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number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 609407877 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 609407877 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 609407877 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 609407877 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 609407409 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 609407409 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 609407409 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 609407409 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016247 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016247 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013925 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013925 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015634 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015634 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015634 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015634 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24417.566426 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24417.566426 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45068.764764 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45068.764764 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29268.762237 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29268.762237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29268.762237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29268.762237 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013926 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013926 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.015635 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015635 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.015635 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015635 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24444.767383 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24444.767383 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45186.169543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45186.169543 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29317.336311 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29317.336311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29317.336311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29317.336311 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -621,32 +639,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700613 # number of writebacks -system.cpu.dcache.writebacks::total 3700613 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50799 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50799 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350847 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 350847 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 401646 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 401646 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 401646 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 401646 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238740 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238740 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887316 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887316 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9126056 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126056 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9126056 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126056 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162027926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 162027926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75898088250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75898088250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237926014250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 237926014250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237926014250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 237926014250 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3700618 # number of writebacks +system.cpu.dcache.writebacks::total 3700618 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50811 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50811 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350963 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 350963 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 401774 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 401774 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 401774 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 401774 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238754 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238754 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887318 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887318 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9126072 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126072 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9126072 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126072 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162228644750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 162228644750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76111394500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 76111394500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238340039250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 238340039250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238340039250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 238340039250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016133 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016133 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses @@ -655,14 +673,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014975 system.cpu.dcache.demand_mshr_miss_rate::total 0.014975 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014975 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014975 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22383.443251 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22383.443251 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40214.827962 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40214.827962 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26071.066652 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26071.066652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26071.066652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26071.066652 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22411.128317 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22411.128317 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40327.806178 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40327.806178 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26116.388217 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26116.388217 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26116.388217 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26116.388217 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 87bb9f534..a0b66714a 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.661836 # Number of seconds simulated -sim_ticks 661835607000 # Number of ticks simulated -final_tick 661835607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.662267 # Number of seconds simulated +sim_ticks 662266942000 # Number of ticks simulated +final_tick 662266942000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129941 # Simulator instruction rate (inst/s) -host_op_rate 129941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49537566 # Simulator tick rate (ticks/s) -host_mem_usage 237180 # Number of bytes of host memory used -host_seconds 13360.28 # Real time elapsed on the host +host_inst_rate 180229 # Simulator instruction rate (inst/s) +host_op_rate 180229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68753783 # Simulator tick rate (ticks/s) +host_mem_usage 293196 # Number of bytes of host memory used +host_seconds 9632.44 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125980800 # Number of bytes read from this memory -system.physmem.bytes_read::total 126042752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65306880 # Number of bytes written to this memory -system.physmem.bytes_written::total 65306880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1968450 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1969418 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1020420 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1020420 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 190350593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 190444199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93606 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93606 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98675380 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98675380 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98675380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 190350593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 289119579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1969418 # Number of read requests accepted -system.physmem.writeReqs 1020420 # Number of write requests accepted -system.physmem.readBursts 1969418 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1020420 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125960256 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82496 # Total number of bytes read from write queue -system.physmem.bytesWritten 65304896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126042752 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65306880 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1289 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 62272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125973696 # Number of bytes read from this memory +system.physmem.bytes_read::total 126035968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65304064 # Number of bytes written to this memory +system.physmem.bytes_written::total 65304064 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 973 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1968339 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1969312 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1020376 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1020376 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 94029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 190215890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 190309919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94029 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94029 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98606861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98606861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98606861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 190215890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 288916779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1969312 # Number of read requests accepted +system.physmem.writeReqs 1020376 # Number of write requests accepted +system.physmem.readBursts 1969312 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1020376 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125955072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 80896 # Total number of bytes read from write queue +system.physmem.bytesWritten 65302080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126035968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65304064 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1264 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119133 # Per bank write bursts -system.physmem.perBankRdBursts::1 114512 # Per bank write bursts -system.physmem.perBankRdBursts::2 116620 # Per bank write bursts -system.physmem.perBankRdBursts::3 118156 # Per bank write bursts -system.physmem.perBankRdBursts::4 118267 # Per bank write bursts -system.physmem.perBankRdBursts::5 117901 # Per bank write bursts -system.physmem.perBankRdBursts::6 120342 # Per bank write bursts -system.physmem.perBankRdBursts::7 125056 # Per bank write bursts -system.physmem.perBankRdBursts::8 127675 # Per bank write bursts -system.physmem.perBankRdBursts::9 130585 # Per bank write bursts -system.physmem.perBankRdBursts::10 129305 # Per bank write bursts -system.physmem.perBankRdBursts::11 130922 # Per bank write bursts -system.physmem.perBankRdBursts::12 126863 # Per bank write bursts -system.physmem.perBankRdBursts::13 125867 # Per bank write bursts -system.physmem.perBankRdBursts::14 123079 # Per bank write bursts -system.physmem.perBankRdBursts::15 123846 # Per bank write bursts -system.physmem.perBankWrBursts::0 61299 # Per bank write bursts -system.physmem.perBankWrBursts::1 61588 # Per bank write bursts -system.physmem.perBankWrBursts::2 60677 # Per bank write bursts -system.physmem.perBankWrBursts::3 61353 # Per bank write bursts -system.physmem.perBankWrBursts::4 61807 # Per bank write bursts -system.physmem.perBankWrBursts::5 63207 # Per bank write bursts -system.physmem.perBankWrBursts::6 64256 # Per bank write bursts -system.physmem.perBankWrBursts::7 65745 # Per bank write bursts -system.physmem.perBankWrBursts::8 65527 # Per bank write bursts -system.physmem.perBankWrBursts::9 65905 # Per bank write bursts -system.physmem.perBankWrBursts::10 65467 # Per bank write bursts -system.physmem.perBankWrBursts::11 65774 # Per bank write bursts -system.physmem.perBankWrBursts::12 64405 # Per bank write bursts -system.physmem.perBankWrBursts::13 64356 # Per bank write bursts -system.physmem.perBankWrBursts::14 64678 # Per bank write bursts -system.physmem.perBankWrBursts::15 64345 # Per bank write bursts +system.physmem.perBankRdBursts::0 119151 # Per bank write bursts +system.physmem.perBankRdBursts::1 114520 # Per bank write bursts +system.physmem.perBankRdBursts::2 116626 # Per bank write bursts +system.physmem.perBankRdBursts::3 118169 # Per bank write bursts +system.physmem.perBankRdBursts::4 118249 # Per bank write bursts +system.physmem.perBankRdBursts::5 117904 # Per bank write bursts +system.physmem.perBankRdBursts::6 120341 # Per bank write bursts +system.physmem.perBankRdBursts::7 125053 # Per bank write bursts +system.physmem.perBankRdBursts::8 127649 # Per bank write bursts +system.physmem.perBankRdBursts::9 130602 # Per bank write bursts +system.physmem.perBankRdBursts::10 129289 # Per bank write bursts +system.physmem.perBankRdBursts::11 130962 # Per bank write bursts +system.physmem.perBankRdBursts::12 126769 # Per bank write bursts +system.physmem.perBankRdBursts::13 125905 # Per bank write bursts +system.physmem.perBankRdBursts::14 123070 # Per bank write bursts +system.physmem.perBankRdBursts::15 123789 # Per bank write bursts +system.physmem.perBankWrBursts::0 61320 # Per bank write bursts +system.physmem.perBankWrBursts::1 61597 # Per bank write bursts +system.physmem.perBankWrBursts::2 60678 # Per bank write bursts +system.physmem.perBankWrBursts::3 61357 # Per bank write bursts +system.physmem.perBankWrBursts::4 61793 # Per bank write bursts +system.physmem.perBankWrBursts::5 63216 # Per bank write bursts +system.physmem.perBankWrBursts::6 64269 # Per bank write bursts +system.physmem.perBankWrBursts::7 65744 # Per bank write bursts +system.physmem.perBankWrBursts::8 65524 # Per bank write bursts +system.physmem.perBankWrBursts::9 65904 # Per bank write bursts +system.physmem.perBankWrBursts::10 65459 # Per bank write bursts +system.physmem.perBankWrBursts::11 65777 # Per bank write bursts +system.physmem.perBankWrBursts::12 64349 # Per bank write bursts +system.physmem.perBankWrBursts::13 64362 # Per bank write bursts +system.physmem.perBankWrBursts::14 64665 # Per bank write bursts +system.physmem.perBankWrBursts::15 64331 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 661835517500 # Total gap between requests +system.physmem.totGap 662266852500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1969418 # Read request sizes (log2) +system.physmem.readPktSize::6 1969312 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1020420 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1619695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 248396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 75753 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1020376 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1619195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 248434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 76068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,38 +144,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 27847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 29428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 63276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 60589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 64564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 210 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -193,132 +193,133 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1772142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.926701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.988600 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 137.225720 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1375537 77.62% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 272696 15.39% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53852 3.04% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21473 1.21% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12850 0.73% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6581 0.37% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4855 0.27% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3761 0.21% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20537 1.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1772142 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59644 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.954195 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 163.722438 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59607 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 6 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1775882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.694867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.878503 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 136.793796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1380775 77.75% 77.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 271356 15.28% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53913 3.04% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21326 1.20% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12854 0.72% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6480 0.36% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5132 0.29% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3787 0.21% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20259 1.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1775882 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59943 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.788466 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.189780 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59903 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 15 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 9 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59644 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59644 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.107991 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.066184 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.220335 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29768 49.91% 49.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1416 2.37% 52.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 22411 37.57% 89.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4939 8.28% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 872 1.46% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 162 0.27% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 31 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59644 # Writes before turning the bus around for reads -system.physmem.totQLat 40394853000 # Total ticks spent queuing -system.physmem.totMemAccLat 77297271750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9840645000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20524.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59943 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59943 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.021921 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.980571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.225631 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 33661 56.16% 56.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 25267 42.15% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 929 1.55% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 52 0.09% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-69 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59943 # Writes before turning the bus around for reads +system.physmem.totQLat 41251747750 # Total ticks spent queuing +system.physmem.totMemAccLat 78152647750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9840240000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20960.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39274.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 190.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 98.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 190.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 98.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39710.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 190.19 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 98.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 190.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 98.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.26 # Data bus utilization in percentage system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.96 # Average write queue length when enqueuing -system.physmem.readRowHits 798370 # Number of row buffer hits during reads -system.physmem.writeRowHits 417997 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.96 # Row buffer hit rate for writes -system.physmem.avgGap 221361.66 # Average gap between requests -system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 126237669000 # Time in different power states -system.physmem.memoryStateTime::REF 22100000000 # Time in different power states +system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing +system.physmem.readRowHits 795732 # Number of row buffer hits during reads +system.physmem.writeRowHits 416769 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.84 # Row buffer hit rate for writes +system.physmem.avgGap 221517.05 # Average gap between requests +system.physmem.pageHitRate 40.57 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 126335534000 # Time in different power states +system.physmem.memoryStateTime::REF 22114300000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 513493900500 # Time in different power states +system.physmem.memoryStateTime::ACT 513810229000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 289119579 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1198182 # Transaction distribution -system.membus.trans_dist::ReadResp 1198182 # Transaction distribution -system.membus.trans_dist::Writeback 1020420 # Transaction distribution -system.membus.trans_dist::ReadExReq 771236 # Transaction distribution -system.membus.trans_dist::ReadExResp 771236 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4959256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4959256 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191349632 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191349632 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191349632 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11823202500 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 1197969 # Transaction distribution +system.membus.trans_dist::ReadResp 1197969 # Transaction distribution +system.membus.trans_dist::Writeback 1020376 # Transaction distribution +system.membus.trans_dist::ReadExReq 771343 # Transaction distribution +system.membus.trans_dist::ReadExResp 771343 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4959000 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4959000 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191340032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191340032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2989688 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2989688 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2989688 # Request fanout histogram +system.membus.reqLayer0.occupancy 11823557000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 18425039000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18423875500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 410520712 # Number of BP lookups -system.cpu.branchPred.condPredicted 318849760 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16265290 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 282927738 # Number of BTB lookups -system.cpu.branchPred.BTBHits 279343276 # Number of BTB hits +system.cpu.branchPred.lookups 410506798 # Number of BP lookups +system.cpu.branchPred.condPredicted 318826270 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16270103 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 283363020 # Number of BTB lookups +system.cpu.branchPred.BTBHits 279346814 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.733082 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26370791 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.582664 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26372853 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 646139057 # DTB read hits -system.cpu.dtb.read_misses 12159875 # DTB read misses +system.cpu.dtb.read_hits 646169518 # DTB read hits +system.cpu.dtb.read_misses 12159492 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 658298932 # DTB read accesses -system.cpu.dtb.write_hits 218185834 # DTB write hits -system.cpu.dtb.write_misses 7515423 # DTB write misses +system.cpu.dtb.read_accesses 658329010 # DTB read accesses +system.cpu.dtb.write_hits 218199205 # DTB write hits +system.cpu.dtb.write_misses 7515385 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225701257 # DTB write accesses -system.cpu.dtb.data_hits 864324891 # DTB hits -system.cpu.dtb.data_misses 19675298 # DTB misses +system.cpu.dtb.write_accesses 225714590 # DTB write accesses +system.cpu.dtb.data_hits 864368723 # DTB hits +system.cpu.dtb.data_misses 19674877 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 884000189 # DTB accesses -system.cpu.itb.fetch_hits 422443679 # ITB hits -system.cpu.itb.fetch_misses 44 # ITB misses +system.cpu.dtb.data_accesses 884043600 # DTB accesses +system.cpu.itb.fetch_hits 422435766 # ITB hits +system.cpu.itb.fetch_misses 46 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 422443723 # ITB accesses +system.cpu.itb.fetch_accesses 422435812 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,98 +333,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1323671215 # number of cpu cycles simulated +system.cpu.numCycles 1324533885 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 433730630 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3419498139 # Number of instructions fetch has processed -system.cpu.fetch.Branches 410520712 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 305714067 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 866879802 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45990094 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1786 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 422443679 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8426079 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1323607404 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.583469 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.158025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 433728129 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3419447982 # Number of instructions fetch has processed +system.cpu.fetch.Branches 410506798 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 305719667 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 867740174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45999556 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 89 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1859 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 122 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 422435766 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8419815 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1324470151 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.581748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.157662 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 696600974 52.63% 52.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48023746 3.63% 56.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24394821 1.84% 58.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45250405 3.42% 61.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142990505 10.80% 72.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 66206181 5.00% 77.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43787822 3.31% 80.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29609921 2.24% 82.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226743029 17.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 697483370 52.66% 52.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48005474 3.62% 56.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24395138 1.84% 58.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45249876 3.42% 61.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142980828 10.80% 72.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 66219617 5.00% 77.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43796288 3.31% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29613001 2.24% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226726559 17.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1323607404 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310138 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.583344 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 355560821 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 384357689 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 525784970 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34909729 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22994195 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62281773 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 917 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3264096854 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2212 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22994195 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 373922324 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 204910686 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7734 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 538718918 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 183053547 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3181111000 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1787853 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18972686 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 140245391 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27858899 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2377395421 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4126748897 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4126578364 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 170532 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1324470151 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309925 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.581624 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 355594570 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 385179518 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 525809516 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34887563 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22998984 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62292881 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 862 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3264034617 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2122 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22998984 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 373946851 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 205483814 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7143 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 538725666 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 183307693 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3181027912 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1764061 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19006533 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 140449897 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27939508 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2377346604 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4126580900 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4126409923 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 170976 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1001192458 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 212 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99259627 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 719210617 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272896274 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90779805 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 59022559 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2889836484 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 194 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2624050349 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1575226 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1139401909 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 505657216 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 165 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1323607404 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.982499 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.151238 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1001143641 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 182 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 180 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99171579 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 719206222 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272877842 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90853191 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58764648 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2889718435 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 163 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2624030011 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1568714 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1139278450 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 505521247 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 134 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1324470151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.981192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.151140 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 519394281 39.24% 39.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169344121 12.79% 52.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158328435 11.96% 64.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149155945 11.27% 75.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126186051 9.53% 84.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84451720 6.38% 91.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68205907 5.15% 96.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33984275 2.57% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14556669 1.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 520285766 39.28% 39.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169352294 12.79% 52.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158263377 11.95% 64.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149147598 11.26% 75.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126214674 9.53% 84.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84460771 6.38% 91.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68224303 5.15% 96.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33971144 2.56% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14550224 1.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1323607404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1324470151 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13175247 35.70% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13169928 35.70% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available @@ -452,118 +453,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19116655 51.79% 87.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4618094 12.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19111172 51.81% 87.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4608428 12.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1719340504 65.52% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 109 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1719281995 65.52% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896937 0.03% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 170 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 672950109 25.65% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230862442 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896550 0.03% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 159 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 672977290 25.65% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230873835 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2624050349 # Type of FU issued -system.cpu.iq.rate 1.982403 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36909996 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014066 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6608212970 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4028086926 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2521962769 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1980354 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1298007 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 893087 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2659977012 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 983333 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69535121 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2624030011 # Type of FU issued +system.cpu.iq.rate 1.981097 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36889528 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014058 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6609007948 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4027844088 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2521909296 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1980467 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1299263 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 893137 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2659936163 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 983376 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69546745 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 274614954 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 379465 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 148696 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 112167772 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 274610559 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 379781 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 148802 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 112149340 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 269 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6022963 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 343 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6024507 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22994195 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 147722049 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18412868 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3041056525 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6683505 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 719210617 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272896274 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 194 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 821771 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17859213 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 148696 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10896298 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8844115 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19740413 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2578377980 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 658298938 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45672369 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22998984 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 147954834 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18526434 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3040938881 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6690511 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 719206222 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272877842 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 163 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 822212 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17973283 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 148802 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10902941 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8845995 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19748936 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2578346915 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 658329015 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45683096 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151219847 # number of nop insts executed -system.cpu.iew.exec_refs 884000267 # number of memory reference insts executed -system.cpu.iew.exec_branches 315975248 # Number of branches executed -system.cpu.iew.exec_stores 225701329 # Number of stores executed -system.cpu.iew.exec_rate 1.947899 # Inst execution rate -system.cpu.iew.wb_sent 2552852780 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2522855856 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1489309006 # num instructions producing a value -system.cpu.iew.wb_consumers 1920624303 # num instructions consuming a value +system.cpu.iew.exec_nop 151220283 # number of nop insts executed +system.cpu.iew.exec_refs 884043668 # number of memory reference insts executed +system.cpu.iew.exec_branches 315967801 # Number of branches executed +system.cpu.iew.exec_stores 225714653 # Number of stores executed +system.cpu.iew.exec_rate 1.946607 # Inst execution rate +system.cpu.iew.wb_sent 2552803336 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2522802433 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1489230488 # num instructions producing a value +system.cpu.iew.wb_consumers 1920481156 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.905954 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775430 # average fanout of values written-back +system.cpu.iew.wb_rate 1.904672 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775447 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1005196168 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1005079964 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16264438 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1184721059 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.536041 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.558766 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16269309 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1185591559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.534913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.558094 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 695617998 58.72% 58.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159800446 13.49% 72.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79745623 6.73% 78.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52150996 4.40% 83.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28466079 2.40% 85.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19402088 1.64% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20010452 1.69% 89.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23121038 1.95% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106406339 8.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 696399330 58.74% 58.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159901902 13.49% 72.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79790439 6.73% 78.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52118707 4.40% 83.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28427889 2.40% 85.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19400301 1.64% 87.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20045609 1.69% 89.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23104546 1.95% 91.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106402836 8.97% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1184721059 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1185591559 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -609,225 +610,233 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106406339 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106402836 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3817511814 # The number of ROB reads -system.cpu.rob.rob_writes 5788973646 # The number of ROB writes -system.cpu.timesIdled 715 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 63811 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3818269613 # The number of ROB reads +system.cpu.rob.rob_writes 5788733936 # The number of ROB writes +system.cpu.timesIdled 729 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 63734 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.762464 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.762464 # CPI: Total CPI of All Threads -system.cpu.ipc 1.311537 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.311537 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3467668910 # number of integer regfile reads -system.cpu.int_regfile_writes 2022324472 # number of integer regfile writes -system.cpu.fp_regfile_reads 45289 # number of floating regfile reads -system.cpu.fp_regfile_writes 607 # number of floating regfile writes +system.cpu.cpi 0.762961 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.762961 # CPI: Total CPI of All Threads +system.cpu.ipc 1.310683 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.310683 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3467602221 # number of integer regfile reads +system.cpu.int_regfile_writes 2022271322 # number of integer regfile writes +system.cpu.fp_regfile_reads 45596 # number of floating regfile reads +system.cpu.fp_regfile_writes 565 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1252958492 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7335196 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7335196 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3742782 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879093 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879093 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22169424 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22171360 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829190592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 829252544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 829252544 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10221470348 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 7335000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7335000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3742826 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879134 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879134 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1946 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22169148 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22171094 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829183168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 829245440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12957100 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12957100 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12957100 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10221444363 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1621500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14118250749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14117208750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 769.518205 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 422442162 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 968 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 436407.192149 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 772.533395 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 422434249 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 973 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 434156.473792 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 769.518205 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.375741 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.375741 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 967 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 772.533395 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377214 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377214 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 972 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 900 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.472168 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 844888324 # Number of tag accesses -system.cpu.icache.tags.data_accesses 844888324 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 422442162 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 422442162 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 422442162 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 422442162 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 422442162 # number of overall hits -system.cpu.icache.overall_hits::total 422442162 # number of overall hits +system.cpu.icache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 844872503 # Number of tag accesses +system.cpu.icache.tags.data_accesses 844872503 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 422434249 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 422434249 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 422434249 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 422434249 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 422434249 # number of overall hits +system.cpu.icache.overall_hits::total 422434249 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1516 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1516 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1516 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1516 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1516 # number of overall misses system.cpu.icache.overall_misses::total 1516 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 105797750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 105797750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 105797750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 105797750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 105797750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 105797750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 422443678 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 422443678 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 422443678 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 422443678 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 422443678 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 422443678 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 104441749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 104441749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 104441749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 104441749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 104441749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 104441749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 422435765 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 422435765 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 422435765 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 422435765 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 422435765 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 422435765 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69787.434037 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69787.434037 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69787.434037 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69787.434037 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69787.434037 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69787.434037 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 455 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68892.974274 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68892.974274 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68892.974274 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68892.974274 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68892.974274 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68892.974274 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 469 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58.625000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 548 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 548 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 548 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 548 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 548 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 548 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 968 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72550750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 72550750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72550750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 72550750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72550750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 72550750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 543 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 543 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 543 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 543 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 543 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 543 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 973 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 973 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 973 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 973 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 973 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 973 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72760499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 72760499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72760499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 72760499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72760499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 72760499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74949.121901 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74949.121901 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74949.121901 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74949.121901 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74949.121901 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74949.121901 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74779.546763 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74779.546763 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74779.546763 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74779.546763 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74779.546763 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74779.546763 # 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Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.513412 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958446 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1936599 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31406.671872 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9110908 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1966387 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.633324 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 27876757750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14558.085450 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.965177 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16821.621245 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69976.738559 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61348.915289 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69980.981356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69976.738559 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213644 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.213727 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61182.939363 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70371.438793 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70363.975821 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70284.646064 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70284.646064 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61182.939363 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70337.426886 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70332.903826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61182.939363 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70337.426886 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70332.903826 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9209225 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.405523 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 713868953 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9213321 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.482262 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5101114000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.405523 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997902 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997902 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9209065 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.415581 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 713883338 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9213161 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.485169 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5099544250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.415581 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997904 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997904 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 735 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2949 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 748 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2938 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1472872785 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1472872785 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 558354793 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 558354793 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155514155 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155514155 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 713868948 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 713868948 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 713868948 # number of overall hits -system.cpu.dcache.overall_hits::total 713868948 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12746431 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12746431 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5214347 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5214347 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1472907715 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1472907715 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 558369192 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 558369192 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155514142 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155514142 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 713883334 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 713883334 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 713883334 # number of overall hits +system.cpu.dcache.overall_hits::total 713883334 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12749578 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12749578 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5214360 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5214360 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17960778 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17960778 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17960778 # number of overall misses -system.cpu.dcache.overall_misses::total 17960778 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 384137632000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 384137632000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 288800427104 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 288800427104 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 70500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 70500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 672938059104 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 672938059104 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 672938059104 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 672938059104 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 571101224 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 571101224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17963938 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17963938 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17963938 # number of overall misses +system.cpu.dcache.overall_misses::total 17963938 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 385716453000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 385716453000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289481531698 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289481531698 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 71500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 675197984698 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 675197984698 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 675197984698 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 675197984698 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 571118770 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 571118770 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 731829726 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 731829726 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 731829726 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 731829726 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 731847272 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731847272 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731847272 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731847272 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022324 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022324 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032442 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.032442 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024542 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024542 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024542 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024542 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30136.877688 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30136.877688 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55385.732308 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55385.732308 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37467.088514 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37467.088514 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37467.088514 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37467.088514 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14080620 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8619116 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1054999 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67267 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.346572 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 128.132903 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024546 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024546 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024546 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024546 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30253.272148 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30253.272148 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55516.215163 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55516.215163 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37586.301216 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37586.301216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37586.301216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37586.301216 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14206702 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8627771 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1055420 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67280 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.460709 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 128.236787 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3742782 # number of writebacks -system.cpu.dcache.writebacks::total 3742782 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5412183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3335275 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3335275 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8747458 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8747458 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8747458 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8747458 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334248 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334248 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879072 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879072 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3742826 # number of writebacks +system.cpu.dcache.writebacks::total 3742826 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5415535 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5415535 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3335243 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3335243 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8750778 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8750778 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8750778 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8750778 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334043 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7334043 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879117 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879117 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9213320 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245645243567 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245645243567 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245645243567 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9213160 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9213160 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9213160 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9213160 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168998137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168998137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77338215218 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77338215218 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 246336352218 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 246336352218 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 246336352218 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 246336352218 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22980.774921 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22980.774921 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41030.115433 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41030.115433 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 68500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 68500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26661.968060 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26661.968060 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26661.968060 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26661.968060 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23042.970569 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23042.970569 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41156.679024 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41156.679024 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index f3667e9fd..272b9aec7 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3321406 # Simulator instruction rate (inst/s) -host_op_rate 3321406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1666724755 # Simulator tick rate (ticks/s) -host_mem_usage 255644 # Number of bytes of host memory used -host_seconds 547.89 # Real time elapsed on the host +host_inst_rate 2928853 # Simulator instruction rate (inst/s) +host_op_rate 2928852 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1469736098 # Simulator tick rate (ticks/s) +host_mem_usage 279876 # Number of bytes of host memory used +host_seconds 621.33 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 906468506 # Wr system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11068994882 # Throughput (bytes/s) -system.membus.data_through_bus 10108087278 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution +system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution +system.membus.trans_dist::WriteReq 160728502 # Transaction distribution +system.membus.trans_dist::WriteResp 160728502 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3652757018 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1210648330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4863405348 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 7305514036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2802573242 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 10108087278 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram +system.membus.snoop_fanout::mean 0.751070 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.432393 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 605324165 24.89% 24.89% # Request fanout histogram +system.membus.snoop_fanout::1 1826378509 75.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2431702674 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 07eca3cb9..2d7afdf8e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu sim_ticks 2623386226000 # Number of ticks simulated final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1619868 # Simulator instruction rate (inst/s) -host_op_rate 1619868 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2335193556 # Simulator tick rate (ticks/s) -host_mem_usage 265412 # Number of bytes of host memory used -host_seconds 1123.41 # Real time elapsed on the host +host_inst_rate 1656263 # Simulator instruction rate (inst/s) +host_op_rate 1656263 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2387660297 # Simulator tick rate (ticks/s) +host_mem_usage 289632 # Number of bytes of host memory used +host_seconds 1098.73 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 24836956 # To system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 72644797 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1178362 # Transaction distribution system.membus.trans_dist::ReadResp 1178362 # Transaction distribution system.membus.trans_dist::Writeback 1018077 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 781301 # Tr system.membus.trans_dist::ReadExResp 781301 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190575360 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2977740 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2977740 # Request fanout histogram system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks) @@ -481,7 +489,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 312415345 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution @@ -490,11 +497,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916965 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 21918569 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12806033 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12806033 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12806033 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index d103f16e9..217d3879c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.095875 # Number of seconds simulated -sim_ticks 1095875470500 # Number of ticks simulated -final_tick 1095875470500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.096187 # Number of seconds simulated +sim_ticks 1096186990500 # Number of ticks simulated +final_tick 1096186990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 232088 # Simulator instruction rate (inst/s) -host_op_rate 250040 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 164667871 # Simulator tick rate (ticks/s) -host_mem_usage 318056 # Number of bytes of host memory used -host_seconds 6655.07 # Real time elapsed on the host +host_inst_rate 242878 # Simulator instruction rate (inst/s) +host_op_rate 261664 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 172372275 # Simulator tick rate (ticks/s) +host_mem_usage 308000 # Number of bytes of host memory used +host_seconds 6359.42 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131539072 # Number of bytes read from this memory -system.physmem.bytes_read::total 131539072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 131551936 # Number of bytes read from this memory +system.physmem.bytes_read::total 131551936 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66963456 # Number of bytes written to this memory -system.physmem.bytes_written::total 66963456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2055298 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2055298 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046304 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046304 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 120031040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 120031040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 46020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 46020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 61104987 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 61104987 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 61104987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 120031040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 181136026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2055298 # Number of read requests accepted -system.physmem.writeReqs 1046304 # Number of write requests accepted -system.physmem.readBursts 2055298 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046304 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131453056 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue -system.physmem.bytesWritten 66961856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131539072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66963456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_written::writebacks 66968384 # Number of bytes written to this memory +system.physmem.bytes_written::total 66968384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2055499 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055499 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046381 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 120008664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 120008664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 46007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 46007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 61092117 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 61092117 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 61092117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 120008664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 181100781 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2055499 # Number of read requests accepted +system.physmem.writeReqs 1046381 # Number of write requests accepted +system.physmem.readBursts 2055499 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046381 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131465088 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 86848 # Total number of bytes read from write queue +system.physmem.bytesWritten 66966784 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131551936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66968384 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1357 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127944 # Per bank write bursts -system.physmem.perBankRdBursts::1 125151 # Per bank write bursts -system.physmem.perBankRdBursts::2 122313 # Per bank write bursts -system.physmem.perBankRdBursts::3 124176 # Per bank write bursts -system.physmem.perBankRdBursts::4 123203 # Per bank write bursts -system.physmem.perBankRdBursts::5 123365 # Per bank write bursts -system.physmem.perBankRdBursts::6 123797 # Per bank write bursts -system.physmem.perBankRdBursts::7 124247 # Per bank write bursts -system.physmem.perBankRdBursts::8 131879 # Per bank write bursts -system.physmem.perBankRdBursts::9 134089 # Per bank write bursts -system.physmem.perBankRdBursts::10 132451 # Per bank write bursts -system.physmem.perBankRdBursts::11 133680 # Per bank write bursts -system.physmem.perBankRdBursts::12 133764 # Per bank write bursts -system.physmem.perBankRdBursts::13 133810 # Per bank write bursts -system.physmem.perBankRdBursts::14 129795 # Per bank write bursts -system.physmem.perBankRdBursts::15 130290 # Per bank write bursts -system.physmem.perBankWrBursts::0 65788 # Per bank write bursts -system.physmem.perBankWrBursts::1 64108 # Per bank write bursts -system.physmem.perBankWrBursts::2 62418 # Per bank write bursts -system.physmem.perBankWrBursts::3 62855 # Per bank write bursts -system.physmem.perBankWrBursts::4 62808 # Per bank write bursts -system.physmem.perBankWrBursts::5 62982 # Per bank write bursts -system.physmem.perBankWrBursts::6 64271 # Per bank write bursts -system.physmem.perBankWrBursts::7 65268 # Per bank write bursts -system.physmem.perBankWrBursts::8 67081 # Per bank write bursts -system.physmem.perBankWrBursts::9 67609 # Per bank write bursts -system.physmem.perBankWrBursts::10 67274 # Per bank write bursts -system.physmem.perBankWrBursts::11 67626 # Per bank write bursts -system.physmem.perBankWrBursts::12 67000 # Per bank write bursts -system.physmem.perBankWrBursts::13 67431 # Per bank write bursts -system.physmem.perBankWrBursts::14 66125 # Per bank write bursts -system.physmem.perBankWrBursts::15 65635 # Per bank write bursts +system.physmem.perBankRdBursts::0 127914 # Per bank write bursts +system.physmem.perBankRdBursts::1 125107 # Per bank write bursts +system.physmem.perBankRdBursts::2 122280 # Per bank write bursts +system.physmem.perBankRdBursts::3 124254 # Per bank write bursts +system.physmem.perBankRdBursts::4 123262 # Per bank write bursts +system.physmem.perBankRdBursts::5 123345 # Per bank write bursts +system.physmem.perBankRdBursts::6 123865 # Per bank write bursts +system.physmem.perBankRdBursts::7 124190 # Per bank write bursts +system.physmem.perBankRdBursts::8 131999 # Per bank write bursts +system.physmem.perBankRdBursts::9 134064 # Per bank write bursts +system.physmem.perBankRdBursts::10 132428 # Per bank write bursts +system.physmem.perBankRdBursts::11 133673 # Per bank write bursts +system.physmem.perBankRdBursts::12 133725 # Per bank write bursts +system.physmem.perBankRdBursts::13 133862 # Per bank write bursts +system.physmem.perBankRdBursts::14 129895 # Per bank write bursts +system.physmem.perBankRdBursts::15 130279 # Per bank write bursts +system.physmem.perBankWrBursts::0 65789 # Per bank write bursts +system.physmem.perBankWrBursts::1 64087 # Per bank write bursts +system.physmem.perBankWrBursts::2 62403 # Per bank write bursts +system.physmem.perBankWrBursts::3 62885 # Per bank write bursts +system.physmem.perBankWrBursts::4 62820 # Per bank write bursts +system.physmem.perBankWrBursts::5 62979 # Per bank write bursts +system.physmem.perBankWrBursts::6 64285 # Per bank write bursts +system.physmem.perBankWrBursts::7 65232 # Per bank write bursts +system.physmem.perBankWrBursts::8 67082 # Per bank write bursts +system.physmem.perBankWrBursts::9 67588 # Per bank write bursts +system.physmem.perBankWrBursts::10 67303 # Per bank write bursts +system.physmem.perBankWrBursts::11 67613 # Per bank write bursts +system.physmem.perBankWrBursts::12 67020 # Per bank write bursts +system.physmem.perBankWrBursts::13 67468 # Per bank write bursts +system.physmem.perBankWrBursts::14 66169 # Per bank write bursts +system.physmem.perBankWrBursts::15 65633 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1095875382500 # Total gap between requests +system.physmem.totGap 1096186902500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2055298 # Read request sizes (log2) +system.physmem.readPktSize::6 2055499 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046304 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1922424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131512 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046381 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1922421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131703 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,30 +140,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 33528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 60945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 61936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -189,98 +189,107 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1911965 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.774418 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.877172 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.825249 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485376 77.69% 77.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 306998 16.06% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52789 2.76% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21060 1.10% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13283 0.69% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6873 0.36% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5659 0.30% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4134 0.22% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15793 0.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1911965 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60795 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.737117 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.571664 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60754 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1916158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.556187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.764224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.552714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1491113 77.82% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305811 15.96% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52727 2.75% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21051 1.10% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13077 0.68% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6875 0.36% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5570 0.29% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4107 0.21% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15827 0.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1916158 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61021 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.615247 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.737468 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60978 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 19 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60795 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60795 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.209951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.175292 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.091996 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 25805 42.45% 42.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1192 1.96% 44.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 29551 48.61% 93.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3811 6.27% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 363 0.60% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 60 0.10% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 11 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61021 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61021 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.147474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.112394 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.099372 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27727 45.44% 45.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1223 2.00% 47.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 27936 45.78% 93.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3708 6.08% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 355 0.58% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 59 0.10% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 10 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60795 # Writes before turning the bus around for reads -system.physmem.totQLat 38124649000 # Total ticks spent queuing -system.physmem.totMemAccLat 76636286500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10269770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18561.59 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61021 # Writes before turning the bus around for reads +system.physmem.totQLat 38533876500 # Total ticks spent queuing +system.physmem.totMemAccLat 77049039000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10270710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18759.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37311.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 119.95 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 61.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 120.03 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 61.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37509.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 119.93 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 61.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 120.01 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 61.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.41 # Data bus utilization in percentage system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.69 # Average write queue length when enqueuing -system.physmem.readRowHits 779774 # Number of row buffer hits during reads -system.physmem.writeRowHits 408484 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.04 # Row buffer hit rate for writes -system.physmem.avgGap 353325.60 # Average gap between requests -system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 306310282500 # Time in different power states -system.physmem.memoryStateTime::REF 36593440000 # Time in different power states +system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing +system.physmem.readRowHits 777772 # Number of row buffer hits during reads +system.physmem.writeRowHits 406558 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes +system.physmem.avgGap 353394.36 # Average gap between requests +system.physmem.pageHitRate 38.20 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 306608104500 # Time in different power states +system.physmem.memoryStateTime::REF 36603840000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 752968660500 # Time in different power states +system.physmem.memoryStateTime::ACT 752971887000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 181136026 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1255348 # Transaction distribution -system.membus.trans_dist::ReadResp 1255348 # Transaction distribution -system.membus.trans_dist::Writeback 1046304 # Transaction distribution -system.membus.trans_dist::ReadExReq 799950 # Transaction distribution -system.membus.trans_dist::ReadExResp 799950 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5156900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5156900 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198502528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 198502528 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 198502528 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12227667000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 1255486 # Transaction distribution +system.membus.trans_dist::ReadResp 1255486 # Transaction distribution +system.membus.trans_dist::Writeback 1046381 # Transaction distribution +system.membus.trans_dist::ReadExReq 800013 # Transaction distribution +system.membus.trans_dist::ReadExResp 800013 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157379 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5157379 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198520320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198520320 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3101880 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3101880 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3101880 # Request fanout histogram +system.membus.reqLayer0.occupancy 12229457500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 19360882250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 19361348500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 239641872 # Number of BP lookups -system.cpu.branchPred.condPredicted 186303374 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14594643 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 130836287 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121989290 # Number of BTB hits +system.cpu.branchPred.lookups 239650352 # Number of BP lookups +system.cpu.branchPred.condPredicted 186306880 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14598405 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 131764254 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121991524 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.238117 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15653729 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.583171 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15654227 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -367,69 +376,69 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2191750941 # number of cpu cycles simulated +system.cpu.numCycles 2192373981 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563087 # Number of instructions committed system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 42066132 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 42081657 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.419010 # CPI: cycles per instruction -system.cpu.ipc 0.704717 # IPC: instructions per cycle -system.cpu.tickCycles 1808188284 # Number of cycles that the object actually ticked -system.cpu.idleCycles 383562657 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.419414 # CPI: cycles per instruction +system.cpu.ipc 0.704516 # IPC: instructions per cycle +system.cpu.tickCycles 1808241834 # Number of cycles that the object actually ticked +system.cpu.idleCycles 384132147 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.141376 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 464847257 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 661.144399 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 464861353 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 566886.898780 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 566904.089024 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.141376 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322823 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322823 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 661.144399 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322824 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322824 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 929696974 # Number of tag accesses -system.cpu.icache.tags.data_accesses 929696974 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 464847257 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 464847257 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 464847257 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 464847257 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 464847257 # number of overall hits -system.cpu.icache.overall_hits::total 464847257 # number of overall hits +system.cpu.icache.tags.tag_accesses 929725166 # Number of tag accesses +system.cpu.icache.tags.data_accesses 929725166 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 464861353 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 464861353 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 464861353 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 464861353 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 464861353 # number of overall hits +system.cpu.icache.overall_hits::total 464861353 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses system.cpu.icache.overall_misses::total 820 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58324499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58324499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58324499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58324499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58324499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58324499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 464848077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 464848077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 464848077 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 464848077 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 464848077 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 464848077 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59141749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59141749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59141749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59141749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59141749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59141749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 464862173 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 464862173 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 464862173 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 464862173 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 464862173 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 464862173 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71127.437805 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71127.437805 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71127.437805 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71127.437805 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72124.084146 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72124.084146 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72124.084146 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72124.084146 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,56 +453,69 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 820 system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56360501 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 56360501 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56360501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 56360501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56360501 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 56360501 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57178251 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 57178251 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57178251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 57178251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57178251 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 57178251 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68732.318293 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68732.318293 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68732.318293 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68732.318293 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68732.318293 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68732.318293 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.574390 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.574390 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 755014954 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7336391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7336391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890876 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890876 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7336783 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7336783 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890869 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22153789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22155429 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827349888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 827402368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 827402368 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10164976000 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22154304 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22155944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827358208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827410688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12928292 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 12928292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12928292 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10164786000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1391999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1391749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14185372245 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14185031745 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 2022594 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31252.258926 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8984184 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2052369 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.377470 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2022796 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31252.383158 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8984119 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2052571 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.377008 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14968.183746 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 16284.075180 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.456793 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496951 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.953743 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14967.342328 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 16285.040830 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.456767 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496980 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.953747 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id @@ -501,60 +523,60 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107368541 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107368541 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6081037 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6081037 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3700895 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700895 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090926 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1090926 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7171963 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7171963 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7171963 # number of overall hits -system.cpu.l2cache.overall_hits::total 7171963 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1255354 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1255354 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 799950 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 799950 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2055304 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2055304 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2055304 # number of overall misses -system.cpu.l2cache.overall_misses::total 2055304 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100122250500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 100122250500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64358555750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 64358555750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 164480806250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 164480806250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 164480806250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 164480806250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7336391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3700895 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3700895 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890876 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1890876 # 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number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 460997192 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 460997192 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 633577518 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633577518 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 633577518 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633577518 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012983 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012983 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.inst 633583239 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633583239 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 633583239 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633583239 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012982 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012982 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.inst 0.015115 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015115 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.015115 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015115 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24988.087706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24988.087706 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45188.180594 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45188.180594 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29714.330657 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29714.330657 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25015.783601 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25015.783601 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45267.805090 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45267.805090 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29753.840342 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29753.840342 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,48 +707,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700895 # number of writebacks -system.cpu.dcache.writebacks::total 3700895 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 212 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 212 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349723 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 349723 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 349935 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 349935 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 349935 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 349935 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335571 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7335571 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890876 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890876 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9226447 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9226447 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9226447 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9226447 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168217924005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168217924005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77187221250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77187221250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245405145255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245405145255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245405145255 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245405145255 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3700640 # number of writebacks +system.cpu.dcache.writebacks::total 3700640 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349642 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 349642 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 349853 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 349853 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 349853 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 349853 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335963 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7335963 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890869 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890869 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9226832 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9226832 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9226832 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9226832 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168431190255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168431190255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77354259500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77354259500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245785449755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245785449755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245785449755 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245785449755 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22931.810490 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22931.810490 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40820.879450 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40820.879450 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22959.656456 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22959.656456 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40909.369978 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40909.369978 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index a0b5e888a..6fb6c2d5a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.506591 # Number of seconds simulated -sim_ticks 506591420000 # Number of ticks simulated -final_tick 506591420000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.753004 # Number of seconds simulated +sim_ticks 753003557500 # Number of ticks simulated +final_tick 753003557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188296 # Simulator instruction rate (inst/s) -host_op_rate 202861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61758141 # Simulator tick rate (ticks/s) -host_mem_usage 254008 # Number of bytes of host memory used -host_seconds 8202.83 # Real time elapsed on the host +host_inst_rate 139511 # Simulator instruction rate (inst/s) +host_op_rate 150302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68014357 # Simulator tick rate (ticks/s) +host_mem_usage 308752 # Number of bytes of host memory used +host_seconds 11071.24 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1664032415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 46336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143772736 # Number of bytes read from this memory -system.physmem.bytes_read::total 143819072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70460288 # Number of bytes written to this memory -system.physmem.bytes_written::total 70460288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 724 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2246449 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2247173 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100942 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100942 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 91466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283804128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 283895594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 139087014 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 139087014 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 139087014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283804128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 422982608 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2247174 # Number of read requests accepted -system.physmem.writeReqs 1100942 # Number of write requests accepted -system.physmem.readBursts 2247174 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100942 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143725504 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 93632 # Total number of bytes read from write queue -system.physmem.bytesWritten 70458432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143819136 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70460288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1463 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 14592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 231381248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 95077696 # Number of bytes read from this memory +system.physmem.bytes_read::total 326473536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 14592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 14592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 107048704 # Number of bytes written to this memory +system.physmem.bytes_written::total 107048704 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 228 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3615332 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1485589 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5101149 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1672636 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1672636 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 307277762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 126264604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 433561744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19378 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19378 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 142162282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 142162282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 142162282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 307277762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 126264604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 575724026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5101149 # Number of read requests accepted +system.physmem.writeReqs 1672636 # Number of write requests accepted +system.physmem.readBursts 5101149 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1672636 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 326003456 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 470080 # Total number of bytes read from write queue +system.physmem.bytesWritten 107046272 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 326473536 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 107048704 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7345 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139870 # Per bank write bursts -system.physmem.perBankRdBursts::1 136313 # Per bank write bursts -system.physmem.perBankRdBursts::2 133717 # Per bank write bursts -system.physmem.perBankRdBursts::3 136218 # Per bank write bursts -system.physmem.perBankRdBursts::4 134833 # Per bank write bursts -system.physmem.perBankRdBursts::5 135331 # Per bank write bursts -system.physmem.perBankRdBursts::6 136159 # Per bank write bursts -system.physmem.perBankRdBursts::7 136113 # Per bank write bursts -system.physmem.perBankRdBursts::8 143820 # Per bank write bursts -system.physmem.perBankRdBursts::9 146459 # Per bank write bursts -system.physmem.perBankRdBursts::10 144333 # Per bank write bursts -system.physmem.perBankRdBursts::11 146068 # Per bank write bursts -system.physmem.perBankRdBursts::12 145787 # Per bank write bursts -system.physmem.perBankRdBursts::13 145950 # Per bank write bursts -system.physmem.perBankRdBursts::14 142167 # Per bank write bursts -system.physmem.perBankRdBursts::15 142573 # Per bank write bursts -system.physmem.perBankWrBursts::0 69256 # Per bank write bursts -system.physmem.perBankWrBursts::1 67490 # Per bank write bursts -system.physmem.perBankWrBursts::2 65701 # Per bank write bursts -system.physmem.perBankWrBursts::3 66292 # Per bank write bursts -system.physmem.perBankWrBursts::4 66182 # Per bank write bursts -system.physmem.perBankWrBursts::5 66456 # Per bank write bursts -system.physmem.perBankWrBursts::6 67905 # Per bank write bursts -system.physmem.perBankWrBursts::7 68814 # Per bank write bursts -system.physmem.perBankWrBursts::8 70409 # Per bank write bursts -system.physmem.perBankWrBursts::9 70980 # Per bank write bursts -system.physmem.perBankWrBursts::10 70565 # Per bank write bursts -system.physmem.perBankWrBursts::11 70894 # Per bank write bursts -system.physmem.perBankWrBursts::12 70329 # Per bank write bursts -system.physmem.perBankWrBursts::13 70807 # Per bank write bursts -system.physmem.perBankWrBursts::14 69706 # Per bank write bursts -system.physmem.perBankWrBursts::15 69127 # Per bank write bursts +system.physmem.perBankRdBursts::0 320458 # Per bank write bursts +system.physmem.perBankRdBursts::1 318552 # Per bank write bursts +system.physmem.perBankRdBursts::2 312159 # Per bank write bursts +system.physmem.perBankRdBursts::3 320321 # Per bank write bursts +system.physmem.perBankRdBursts::4 313091 # Per bank write bursts +system.physmem.perBankRdBursts::5 313451 # Per bank write bursts +system.physmem.perBankRdBursts::6 306429 # Per bank write bursts +system.physmem.perBankRdBursts::7 300886 # Per bank write bursts +system.physmem.perBankRdBursts::8 320656 # Per bank write bursts +system.physmem.perBankRdBursts::9 326914 # Per bank write bursts +system.physmem.perBankRdBursts::10 318873 # Per bank write bursts +system.physmem.perBankRdBursts::11 328947 # Per bank write bursts +system.physmem.perBankRdBursts::12 326980 # Per bank write bursts +system.physmem.perBankRdBursts::13 328236 # Per bank write bursts +system.physmem.perBankRdBursts::14 322345 # Per bank write bursts +system.physmem.perBankRdBursts::15 315506 # Per bank write bursts +system.physmem.perBankWrBursts::0 106372 # Per bank write bursts +system.physmem.perBankWrBursts::1 103970 # Per bank write bursts +system.physmem.perBankWrBursts::2 101390 # Per bank write bursts +system.physmem.perBankWrBursts::3 102163 # Per bank write bursts +system.physmem.perBankWrBursts::4 101308 # Per bank write bursts +system.physmem.perBankWrBursts::5 100856 # Per bank write bursts +system.physmem.perBankWrBursts::6 104858 # Per bank write bursts +system.physmem.perBankWrBursts::7 106447 # Per bank write bursts +system.physmem.perBankWrBursts::8 107624 # Per bank write bursts +system.physmem.perBankWrBursts::9 106732 # Per bank write bursts +system.physmem.perBankWrBursts::10 104273 # Per bank write bursts +system.physmem.perBankWrBursts::11 105282 # Per bank write bursts +system.physmem.perBankWrBursts::12 105198 # Per bank write bursts +system.physmem.perBankWrBursts::13 104874 # Per bank write bursts +system.physmem.perBankWrBursts::14 106564 # Per bank write bursts +system.physmem.perBankWrBursts::15 104687 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 506591366500 # Total gap between requests +system.physmem.totGap 753003515500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2247174 # Read request sizes (log2) +system.physmem.readPktSize::6 5101149 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100942 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1574104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 476401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 148213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 46974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1672636 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2761902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1096580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 406963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 307813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 214927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 130899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 69362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 43944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 31968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 12494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 6876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 4504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 473 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -144,152 +148,171 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 65003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 66811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 67231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 67460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 67663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 67777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 68170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 69182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 70669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 67984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 68233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 66514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 65455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 23634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 25442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 58935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 74795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 105264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 108420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 110279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 111519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 112924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 114921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 116959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 109523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 106852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 104984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 103460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2025013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 105.768407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.613194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.925028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1567130 77.39% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 318117 15.71% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 66732 3.30% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23886 1.18% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14001 0.69% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6496 0.32% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4833 0.24% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3896 0.19% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19922 0.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2025013 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 65320 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 34.335441 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 154.678788 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 65282 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 65320 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 65320 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.854149 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.813582 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.224401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 41990 64.28% 64.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 22168 33.94% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 1073 1.64% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 57 0.09% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 14 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-85 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 65320 # Writes before turning the bus around for reads -system.physmem.totQLat 50678676000 # Total ticks spent queuing -system.physmem.totMemAccLat 92785757250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11228555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22566.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 4344411 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 99.679291 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.657847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 113.406930 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3407328 78.43% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 696147 16.02% 94.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 107309 2.47% 96.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 43326 1.00% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 33261 0.77% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16273 0.37% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9699 0.22% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6677 0.15% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24391 0.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4344411 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 100519 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 50.674768 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.618065 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.194987 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 98006 97.50% 97.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1235 1.23% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 738 0.73% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 394 0.39% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 104 0.10% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 26 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2559 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3327 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 100519 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 100519 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.639620 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.599991 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.204272 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 73763 73.38% 73.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1810 1.80% 75.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 17937 17.84% 93.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4183 4.16% 97.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1485 1.48% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 646 0.64% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 326 0.32% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 183 0.18% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 100 0.10% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 51 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 16 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 100519 # Writes before turning the bus around for reads +system.physmem.totQLat 147032532073 # Total ticks spent queuing +system.physmem.totMemAccLat 242541357073 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 25469020000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28864.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41316.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 283.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 139.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 283.90 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 139.09 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47614.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 432.94 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 142.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 433.56 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 142.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.30 # Data bus utilization in percentage -system.physmem.busUtilRead 2.22 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.09 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing -system.physmem.readRowHits 906473 # Number of row buffer hits during reads -system.physmem.writeRowHits 415128 # Number of row buffer hits during writes +system.physmem.busUtil 4.49 # Data bus utilization in percentage +system.physmem.busUtilRead 3.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.11 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing +system.physmem.readRowHits 2056015 # Number of row buffer hits during reads +system.physmem.writeRowHits 365966 # Number of row buffer hits during writes system.physmem.readRowHitRate 40.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.71 # Row buffer hit rate for writes -system.physmem.avgGap 151306.40 # Average gap between requests -system.physmem.pageHitRate 39.49 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 89126966500 # Time in different power states -system.physmem.memoryStateTime::REF 16916120000 # Time in different power states +system.physmem.writeRowHitRate 21.88 # Row buffer hit rate for writes +system.physmem.avgGap 111164.37 # Average gap between requests +system.physmem.pageHitRate 35.79 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 77100737509 # Time in different power states +system.physmem.memoryStateTime::REF 25144340000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 400546526000 # Time in different power states +system.physmem.memoryStateTime::ACT 650755672741 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 422982608 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1419539 # Transaction distribution -system.membus.trans_dist::ReadResp 1419538 # Transaction distribution -system.membus.trans_dist::Writeback 1100942 # Transaction distribution -system.membus.trans_dist::ReadExReq 827635 # Transaction distribution -system.membus.trans_dist::ReadExResp 827635 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5595289 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5595289 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214279360 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214279360 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214279360 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12858312000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 21011522750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4164250 # Transaction distribution +system.membus.trans_dist::ReadResp 4164249 # Transaction distribution +system.membus.trans_dist::Writeback 1672636 # Transaction distribution +system.membus.trans_dist::ReadExReq 936899 # Transaction distribution +system.membus.trans_dist::ReadExResp 936899 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11874933 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11874933 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 433522176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 433522176 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6773785 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6773785 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6773785 # Request fanout histogram +system.membus.reqLayer0.occupancy 21336071694 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 47387677526 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 322479068 # Number of BP lookups -system.cpu.branchPred.condPredicted 251697336 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15342173 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 182789015 # Number of BTB lookups -system.cpu.branchPred.BTBHits 169211218 # Number of BTB hits +system.cpu.branchPred.lookups 286237274 # Number of BP lookups +system.cpu.branchPred.condPredicted 223376247 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631258 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157873028 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150326972 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.571875 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19180311 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 62 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.220174 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16640209 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -375,235 +398,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1013182841 # number of cpu cycles simulated +system.cpu.numCycles 1506007116 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 309137299 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2319640214 # Number of instructions fetch has processed -system.cpu.fetch.Branches 322479068 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 188391529 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 688452374 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31084694 # Number of cycles fetch has spent squashing -system.cpu.fetch.CacheLines 300792002 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5498702 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1013132020 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.455758 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.154346 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13915908 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067206547 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286237274 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166967181 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1477423210 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29286858 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656844028 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 587 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1505982817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.470565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.223309 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 555222202 54.80% 54.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 28050197 2.77% 57.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43308558 4.27% 61.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 56959165 5.62% 67.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 42292761 4.17% 71.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 51207543 5.05% 76.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41019007 4.05% 80.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29441196 2.91% 83.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 165631391 16.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 423738570 28.14% 28.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465347942 30.90% 59.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101390896 6.73% 65.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515505409 34.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1013132020 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.318283 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.289459 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 248682792 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 345622952 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 359459924 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 43824601 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15541751 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 49856372 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 610 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2395697302 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2189 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15541751 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 269479595 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 192381996 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17471 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 380094168 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 155617039 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2338847400 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 939227 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 43524152 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 85831703 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 28336004 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2341659219 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10827293229 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2896191361 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 924 # Number of floating rename lookups +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1505982817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.190064 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.372641 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74738188 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 508470466 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849951241 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58180203 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14642719 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42195522 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 748 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037029518 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52402529 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14642719 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139800206 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 434773312 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14137 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837909741 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 78842702 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976226014 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26698193 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45123172 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125355 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1314299 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 18015097 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985707207 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9127389229 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432660668 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 146 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 666760274 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 297 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 295 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 177584133 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 623787680 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 234474986 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 103326529 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 119861826 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2235979798 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2042453270 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1123672 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 568282292 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1410742018 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 109 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1013132020 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.015979 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.060962 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310808262 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 156 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 144 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111604908 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542499825 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199292304 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26858708 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28865215 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947820848 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857727691 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13537484 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 279225798 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 646033301 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1505982817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.233565 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.149736 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 369509753 36.47% 36.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 122144381 12.06% 48.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 148105848 14.62% 63.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 116397380 11.49% 74.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 120158766 11.86% 86.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67734855 6.69% 93.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38716090 3.82% 97.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19620402 1.94% 98.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10744545 1.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 553461726 36.75% 36.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325286672 21.60% 58.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378400557 25.13% 83.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219701727 14.59% 98.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29125951 1.93% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6184 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1013132020 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1505982817 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3650692 18.70% 18.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 890 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15434151 79.07% 97.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 434530 2.23% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166582994 41.01% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1992 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191579576 47.17% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 48024706 11.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1227555044 60.10% 60.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 999501 0.05% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 75 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 18 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 618802083 30.30% 90.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 195096510 9.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138365513 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800977 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 27 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 26 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532245079 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186316069 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2042453270 # Type of FU issued -system.cpu.iq.rate 2.015878 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19520263 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009557 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5118681932 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2804481694 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1937195401 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 563 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 772 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 222 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2061973250 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 283 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 29620868 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857727691 # Type of FU issued +system.cpu.iq.rate 1.233545 # Inst issue rate +system.cpu.iq.fu_busy_cnt 406189268 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218648 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5641164724 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2227059400 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805827330 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 67 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2263916833 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17868715 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 165481346 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 152761 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 223174 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 59627941 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84193491 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66602 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12979 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24445259 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 27365932 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 20554693 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4569389 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 5015263 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15541751 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 99594513 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 79709192 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2235980127 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3715851 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 623787680 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 234474986 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 217 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 887425 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 78519079 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 223174 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8257753 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10408115 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18665868 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2014561503 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 604829298 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27891767 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 14642719 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25280273 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1153411 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947821148 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 542499825 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199292304 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 158606 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 993784 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12979 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7710323 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8723960 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16434283 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1828067374 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 517076026 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29660317 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 50 # number of nop insts executed -system.cpu.iew.exec_refs 796810326 # number of memory reference insts executed -system.cpu.iew.exec_branches 245407289 # Number of branches executed -system.cpu.iew.exec_stores 191981028 # Number of stores executed -system.cpu.iew.exec_rate 1.988349 # Inst execution rate -system.cpu.iew.wb_sent 1947397166 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1937195623 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1312629106 # num instructions producing a value -system.cpu.iew.wb_consumers 2061058840 # num instructions consuming a value +system.cpu.iew.exec_nop 86 # number of nop insts executed +system.cpu.iew.exec_refs 698832649 # number of memory reference insts executed +system.cpu.iew.exec_branches 229600081 # Number of branches executed +system.cpu.iew.exec_stores 181756623 # Number of stores executed +system.cpu.iew.exec_rate 1.213850 # Inst execution rate +system.cpu.iew.wb_sent 1808848691 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805827397 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169333238 # num instructions producing a value +system.cpu.iew.wb_consumers 1689629138 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.911990 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.636871 # average fanout of values written-back +system.cpu.iew.wb_rate 1.199083 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692065 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 572342091 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 257853927 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15341577 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 933174586 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.783195 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675212 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14630548 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1466512041 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.134687 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.044179 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 468896979 50.25% 50.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 178641910 19.14% 69.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 68227019 7.31% 76.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32102473 3.44% 80.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24397966 2.61% 82.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27603302 2.96% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17322198 1.86% 87.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 14774408 1.58% 89.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101208331 10.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 886829793 60.47% 60.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250699029 17.09% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 109472668 7.46% 85.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55016344 3.75% 88.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29216480 1.99% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 33954895 2.32% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24874922 1.70% 94.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18134171 1.24% 96.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58313739 3.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 933174586 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1466512041 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -649,442 +670,484 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction -system.cpu.commit.bw_lim_events 101208331 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 58313739 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3068340180 # The number of ROB reads -system.cpu.rob.rob_writes 4552875899 # The number of ROB writes -system.cpu.timesIdled 556 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3330084063 # The number of ROB reads +system.cpu.rob.rob_writes 3883248691 # The number of ROB writes +system.cpu.timesIdled 433 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24299 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.655967 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.655967 # CPI: Total CPI of All Threads -system.cpu.ipc 1.524466 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.524466 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2376547647 # number of integer regfile reads -system.cpu.int_regfile_writes 1366493054 # number of integer regfile writes -system.cpu.fp_regfile_reads 209 # number of floating regfile reads -system.cpu.fp_regfile_writes 233 # number of floating regfile writes -system.cpu.cc_regfile_reads 7643535318 # number of cc regfile reads -system.cpu.cc_regfile_writes 583887345 # number of cc regfile writes -system.cpu.misc_regfile_reads 725285725 # number of misc regfile reads +system.cpu.cpi 0.975038 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.975038 # CPI: Total CPI of All Threads +system.cpu.ipc 1.025601 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.025601 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2176017050 # number of integer regfile reads +system.cpu.int_regfile_writes 1261587528 # number of integer regfile writes +system.cpu.fp_regfile_reads 38 # number of floating regfile reads +system.cpu.fp_regfile_writes 49 # number of floating regfile writes +system.cpu.cc_regfile_reads 6966468810 # number of cc regfile reads +system.cpu.cc_regfile_writes 551975360 # number of cc regfile writes +system.cpu.misc_regfile_reads 675847678 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1691907313 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7714547 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7714546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3783532 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1894199 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1894199 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1502 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22999521 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23001023 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 48064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 857057664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 857105728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 857105728 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10479902270 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 14271352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 14271352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4800041 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2156446 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737659 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737659 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2176 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38815887 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 38818063 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1395709696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1395779328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2156446 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 23967212 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.089975 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.286146 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 21810766 91.00% 91.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 2156446 9.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 23967212 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15706134446 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1252249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1655247 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14758141993 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15 # number of replacements -system.cpu.icache.tags.tagsinuse 614.894819 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 300790815 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 751 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 400520.392810 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 25977831897 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) +system.cpu.icache.tags.replacements 600 # number of replacements +system.cpu.icache.tags.tagsinuse 446.759697 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656842791 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1088 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 603715.800551 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 614.894819 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.300242 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.300242 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 736 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 709 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.359375 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 601584755 # Number of tag accesses -system.cpu.icache.tags.data_accesses 601584755 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 300790815 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 300790815 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 300790815 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 300790815 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 300790815 # number of overall hits -system.cpu.icache.overall_hits::total 300790815 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1187 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1187 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1187 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1187 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1187 # number of overall misses -system.cpu.icache.overall_misses::total 1187 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 83295499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 83295499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 83295499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 83295499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 83295499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 83295499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 300792002 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 300792002 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 300792002 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 300792002 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 300792002 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 300792002 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70173.124684 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70173.124684 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70173.124684 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70173.124684 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 446.759697 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.872578 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.872578 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1313689140 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313689140 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656842791 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656842791 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656842791 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656842791 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656842791 # number of overall hits +system.cpu.icache.overall_hits::total 656842791 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1235 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1235 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1235 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1235 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1235 # number of overall misses +system.cpu.icache.overall_misses::total 1235 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31675742 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31675742 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31675742 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31675742 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31675742 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31675742 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656844026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656844026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656844026 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656844026 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656844026 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656844026 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25648.374089 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25648.374089 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25648.374089 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25648.374089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25648.374089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25648.374089 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3135 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 123 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.487805 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 436 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 436 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 436 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 436 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 436 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 436 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 751 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 751 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 751 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54758751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54758751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54758751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54758751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54758751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54758751 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 147 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 147 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 147 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 147 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1088 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1088 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1088 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1088 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1088 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1088 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25912248 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25912248 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25912248 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25912248 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25912248 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25912248 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72914.448735 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72914.448735 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72914.448735 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72914.448735 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72914.448735 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72914.448735 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23816.404412 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23816.404412 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23816.404412 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23816.404412 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23816.404412 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23816.404412 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2214491 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 162611547750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44565250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162566982500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 162611547750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.183932 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184008 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436931 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436931 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233810 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.233868 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233810 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.233868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61554.212707 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71685.561366 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71680.394128 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73532.937527 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73532.937527 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61554.212707 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72366.169957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72362.686534 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61554.212707 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72366.169957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72362.686534 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1672636 # number of writebacks +system.cpu.l2cache.writebacks::total 1672636 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67618 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 67646 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 4482 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 4482 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 72100 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 72128 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 72100 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 72128 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2676852 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2677080 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1500168 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1500168 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 936637 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 936637 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3613489 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3613717 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3613489 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1500168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5113885 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16681749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 190526161225 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 190542842974 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 108098150766 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 108098150766 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85432139513 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85432139513 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16681749 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275958300738 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 275974982487 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16681749 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275958300738 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 108098150766 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 384073133253 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.187583 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.187584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.342131 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.342131 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212459 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.212459 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212459 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.300657 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73165.565789 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71175.455806 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71175.625298 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72057.363419 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72057.363419 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91211.578779 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91211.578779 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73165.565789 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76368.933388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76368.731278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73165.565789 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76368.933388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72057.363419 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 657 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2421 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.replacements 17007411 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.965023 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638377840 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17007923 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.534145 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 77012000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.965023 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 449 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1403558154 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1403558154 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 511838800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 511838800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166902232 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166902232 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1335546211 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335546211 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469430568 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469430568 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168947154 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168947154 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 678741032 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 678741032 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 678741034 # number of overall hits -system.cpu.dcache.overall_hits::total 678741034 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12550102 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12550102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5683815 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5683815 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638377722 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638377722 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638377722 # number of overall hits +system.cpu.dcache.overall_hits::total 638377722 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17252405 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17252405 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3638893 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3638893 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 18233917 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 18233917 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 18233919 # number of overall misses -system.cpu.dcache.overall_misses::total 18233919 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 378927155489 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 378927155489 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307221007401 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307221007401 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 686148162890 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 686148162890 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 686148162890 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 686148162890 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 524388902 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 524388902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 20891298 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20891298 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20891300 # number of overall misses +system.cpu.dcache.overall_misses::total 20891300 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 389285003128 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 389285003128 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129453998118 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129453998118 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 384750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 384750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 518739001246 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 518739001246 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 518739001246 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 518739001246 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486682973 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486682973 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 4 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 4 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 66 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 66 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 696974949 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 696974949 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 696974953 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 696974953 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023933 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032933 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032933 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.500000 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.500000 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045455 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045455 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026162 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026162 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026162 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026162 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30193.153449 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30193.153449 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54051.901302 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54051.901302 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37630.321718 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37630.321718 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37630.317591 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37630.317591 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28822616 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4626055 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1847693 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65151 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.599245 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.005127 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 659269020 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659269020 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659269022 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659269022 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035449 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035449 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.021085 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.031689 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.031689 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.031689 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.031689 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22564.100665 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22564.100665 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35575.104329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35575.104329 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 96187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 96187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24830.386376 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24830.386376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24830.383999 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24830.383999 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20820542 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1650046 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1039120 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 52884 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.036706 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 31.201233 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3783532 # number of writebacks -system.cpu.dcache.writebacks::total 3783532 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4836306 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4836306 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3789617 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3789617 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8625923 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8625923 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8625923 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8625923 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7713796 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7713796 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894198 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1894198 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 4800041 # number of writebacks +system.cpu.dcache.writebacks::total 4800041 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2982110 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2982110 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 901266 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 901266 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3883376 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3883376 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3883376 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3883376 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270295 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14270295 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737627 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737627 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9607994 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9607994 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9607995 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9607995 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 192253948507 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 192253948507 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84881076130 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84881076130 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 277135024637 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 277135024637 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 277135094137 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 277135094137 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014710 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014710 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.013785 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.013785 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24923.390314 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24923.390314 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44811.089511 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44811.089511 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28844.212917 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28844.212917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28844.217148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28844.217148 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 17007922 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17007922 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17007923 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17007923 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 301459973376 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 301459973376 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108130443900 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 108130443900 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 101000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 101000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 409590417276 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 409590417276 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 409590518276 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 409590518276 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025798 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025798 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025798 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025798 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21124.999404 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21124.999404 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39497.873122 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39497.873122 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 101000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 101000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24082.331591 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24082.331591 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24082.336113 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24082.336113 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 4decc9d3b..ca7d8e82b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490000 # Number of ticks simulated final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1782051 # Simulator instruction rate (inst/s) -host_op_rate 1919890 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 959946236 # Simulator tick rate (ticks/s) -host_mem_usage 306272 # Number of bytes of host memory used -host_seconds 866.73 # Real time elapsed on the host +host_inst_rate 2048371 # Simulator instruction rate (inst/s) +host_op_rate 2206809 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1103406177 # Simulator tick rate (ticks/s) +host_mem_usage 296712 # Number of bytes of host memory used +host_seconds 754.04 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1664032433 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,36 @@ system.physmem.bw_write::total 750174605 # Wr system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10076480987 # Throughput (bytes/s) -system.membus.data_through_bus 8383808419 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution +system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution +system.membus.trans_dist::WriteReq 172586047 # Transaction distribution +system.membus.trans_dist::WriteResp 172586047 # Transaction distribution +system.membus.trans_dist::SoftPFReq 1 # Transaction distribution +system.membus.trans_dist::SoftPFResp 1 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution +system.membus.trans_dist::StoreCondReq 61 # Transaction distribution +system.membus.trans_dist::StoreCondResp 61 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram +system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram +system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 2172060894 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 8e22dfda9..249435dd7 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.363671 # Nu sim_ticks 2363670998000 # Number of ticks simulated final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1066052 # Simulator instruction rate (inst/s) -host_op_rate 1148821 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1637550718 # Simulator tick rate (ticks/s) -host_mem_usage 316024 # Number of bytes of host memory used -host_seconds 1443.42 # Real time elapsed on the host +host_inst_rate 1205605 # Simulator instruction rate (inst/s) +host_op_rate 1299208 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1851916301 # Simulator tick rate (ticks/s) +host_mem_usage 306192 # Number of bytes of host memory used +host_seconds 1276.34 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1658228914 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 27542188 # To system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 80578984 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1177898 # Transaction distribution system.membus.trans_dist::ReadResp 1177898 # Transaction distribution system.membus.trans_dist::Writeback 1017198 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 780876 # Tr system.membus.trans_dist::ReadExResp 780876 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190462208 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2975972 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2975972 # Request fanout histogram system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) @@ -561,7 +569,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 346939438 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution @@ -570,11 +577,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 84901d870..7956102ad 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1186122 # Simulator instruction rate (inst/s) -host_op_rate 1848085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1122213991 # Simulator tick rate (ticks/s) -host_mem_usage 278740 # Number of bytes of host memory used -host_seconds 2536.06 # Real time elapsed on the host +host_inst_rate 1299561 # Simulator instruction rate (inst/s) +host_op_rate 2024834 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1229541445 # Simulator tick rate (ticks/s) +host_mem_usage 299440 # Number of bytes of host memory used +host_seconds 2314.69 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,33 @@ system.physmem.bw_write::total 542745211 # Wr system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 13588998587 # Throughput (bytes/s) -system.membus.data_through_bus 38674388193 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution +system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution +system.membus.trans_dist::WriteReq 438528338 # Transaction distribution +system.membus.trans_dist::WriteResp 438528338 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram +system.membus.snoop_fanout::mean 2.705196 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 1677713084 29.48% 29.48% # Request fanout histogram +system.membus.snoop_fanout::3 4013232882 70.52% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 5690945966 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index bc5edc6ef..a2f8fddf2 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu sim_ticks 5882580526000 # Number of ticks simulated final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 693030 # Simulator instruction rate (inst/s) -host_op_rate 1079804 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1355284560 # Simulator tick rate (ticks/s) -host_mem_usage 288492 # Number of bytes of host memory used -host_seconds 4340.48 # Real time elapsed on the host +host_inst_rate 912016 # Simulator instruction rate (inst/s) +host_op_rate 1421004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1783532526 # Simulator tick rate (ticks/s) +host_mem_usage 308940 # Number of bytes of host memory used +host_seconds 3298.27 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 11079992 # To system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 32392097 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1177614 # Transaction distribution system.membus.trans_dist::ReadResp 1177614 # Transaction distribution system.membus.trans_dist::Writeback 1018421 # Transaction distribution @@ -45,11 +44,20 @@ system.membus.trans_dist::ReadExResp 781295 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190549120 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2977330 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2977330 # Request fanout histogram system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks) @@ -454,7 +462,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 139381638 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution @@ -463,11 +470,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12811308 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 12811308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) |