diff options
Diffstat (limited to 'tests/long/se/60.bzip2')
36 files changed, 418 insertions, 100 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index cd7da392b..317ef3f76 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -120,6 +120,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -136,6 +137,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -158,6 +160,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -174,6 +177,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -183,6 +187,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -204,6 +209,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -220,6 +226,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -246,7 +253,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index 037bfdea9..45898c91d 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:05:17 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:29:41 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1017016979500 because target called exit() +Exiting @ tick 1009838214500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 864d4a591..01fe4f841 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 1.009838 # Nu sim_ticks 1009838214500 # Number of ticks simulated final_tick 1009838214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87394 # Simulator instruction rate (inst/s) -host_op_rate 87394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48496748 # Simulator tick rate (ticks/s) -host_mem_usage 275936 # Number of bytes of host memory used -host_seconds 20822.81 # Real time elapsed on the host +host_inst_rate 128161 # Simulator instruction rate (inst/s) +host_op_rate 128161 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71119760 # Simulator tick rate (ticks/s) +host_mem_usage 230508 # Number of bytes of host memory used +host_seconds 14199.12 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory @@ -325,6 +327,7 @@ system.membus.reqLayer0.occupancy 11785228500 # La system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) system.membus.respLayer1.occupancy 18364778000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 326538257 # Number of BP lookups system.cpu.branchPred.condPredicted 252572868 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 138234365 # Number of conditional branches incorrect @@ -436,6 +439,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 668.332859 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.326334 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.326334 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 858 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 785 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.418945 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 463858599 # Number of tag accesses +system.cpu.icache.tags.data_accesses 463858599 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 231927731 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 231927731 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 231927731 # number of demand (read+write) hits @@ -544,6 +553,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.455687 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.486850 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.943594 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29793 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 613 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 725 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12815 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15482 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909210 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 106291061 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106291061 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.data 6044291 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6044291 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3693280 # number of Writeback hits @@ -675,6 +693,14 @@ system.cpu.dcache.tags.warmup_cycle 12709353000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4082.357931 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.996669 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 590 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2876 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 593 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1219759777 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1219759777 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 437268777 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437268777 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 156014425 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 3e178e75c..20db05a32 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -529,6 +533,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -550,6 +555,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -566,6 +572,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -592,7 +599,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 3d7fe8a25..b7f8b903e 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 15 2013 19:07:40 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:30:51 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -25,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 694171131000 because target called exit() +Exiting @ tick 685386545000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 29e4de429..09d12ecba 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.685387 # Nu sim_ticks 685386545000 # Number of ticks simulated final_tick 685386545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111182 # Simulator instruction rate (inst/s) -host_op_rate 111182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43894428 # Simulator tick rate (ticks/s) -host_mem_usage 276060 # Number of bytes of host memory used -host_seconds 15614.43 # Real time elapsed on the host +host_inst_rate 166100 # Simulator instruction rate (inst/s) +host_op_rate 166100 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65575812 # Simulator tick rate (ticks/s) +host_mem_usage 231660 # Number of bytes of host memory used +host_seconds 10451.82 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125792064 # Number of bytes read from this memory system.physmem.bytes_read::total 125853824 # Number of bytes read from this memory @@ -326,6 +328,7 @@ system.membus.reqLayer0.occupancy 11873404000 # La system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) system.membus.respLayer1.occupancy 18493738500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 381642976 # Number of BP lookups system.cpu.branchPred.condPredicted 296606399 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 16082111 # Number of conditional branches incorrect @@ -657,6 +660,13 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 773.100738 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.377491 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.377491 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 782110757 # Number of tag accesses +system.cpu.icache.tags.data_accesses 782110757 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 391053395 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 391053395 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 391053395 # number of demand (read+write) hits @@ -745,6 +755,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.445145 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.513002 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.958966 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29778 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 978 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 594 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17297 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10763 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908752 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 107098856 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107098856 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.data 6106330 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6106330 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3725230 # number of Writeback hits @@ -876,6 +895,14 @@ system.cpu.dcache.tags.warmup_cycle 5178034250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4087.561673 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997940 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997940 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 690 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2994 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1430860164 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1430860164 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 538716411 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 538716411 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 155539725 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index 86a7050c2..6cbd45db6 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,26 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +108,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -111,11 +123,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +142,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +152,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr index 1ed796979..506aa6e28 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr @@ -1,7 +1,5 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 33b8f7ad8..1dfd46cbe 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:09:10 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:36:30 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 87abf8a8a..8ad24bba9 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4050769 # Simulator instruction rate (inst/s) -host_op_rate 4050768 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2032728095 # Simulator tick rate (ticks/s) -host_mem_usage 217548 # Number of bytes of host memory used -host_seconds 449.24 # Real time elapsed on the host +host_inst_rate 3833053 # Simulator instruction rate (inst/s) +host_op_rate 3833053 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1923475514 # Simulator tick rate (ticks/s) +host_mem_usage 220744 # Number of bytes of host memory used +host_seconds 474.76 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 11068994882 # To system.membus.throughput 11068994882 # Throughput (bytes/s) system.membus.data_through_bus 10108087278 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 482b126d1..2cb068091 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -147,6 +165,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +174,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +189,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +217,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -207,11 +232,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +251,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +261,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout index 154161af5..43eef16e9 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:14:34 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:44:35 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 27c712d4a..894d37cbc 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.623386 # Nu sim_ticks 2623386226000 # Number of ticks simulated final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1731328 # Simulator instruction rate (inst/s) -host_op_rate 1731328 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2495874089 # Simulator tick rate (ticks/s) -host_mem_usage 225024 # Number of bytes of host memory used -host_seconds 1051.09 # Real time elapsed on the host +host_inst_rate 1625838 # Simulator instruction rate (inst/s) +host_op_rate 1625838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2343799751 # Simulator tick rate (ticks/s) +host_mem_usage 229480 # Number of bytes of host memory used +host_seconds 1119.29 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125367104 # Number of bytes read from this memory system.physmem.bytes_read::total 125418432 # Number of bytes read from this memory @@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy 11122356000 # La system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -114,6 +117,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses +system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -196,6 +205,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1059 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27303 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 106294313 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106294313 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits @@ -327,6 +345,15 @@ system.cpu.dcache.tags.warmup_cycle 40977439000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1238 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index d4b45072d..c32ff375e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -514,6 +516,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -530,6 +533,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -584,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -600,6 +605,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -626,7 +632,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr index b4d96e4ea..5d8946ede 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 7f1aa9216..aa09d1777 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 02:37:44 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 23:27:54 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 541686426500 because target called exit() +Exiting @ tick 533797009000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 19d70b574..5e5db11e7 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.533797 # Nu sim_ticks 533797009000 # Number of ticks simulated final_tick 533797009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102910 # Simulator instruction rate (inst/s) -host_op_rate 114803 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35565366 # Simulator tick rate (ticks/s) -host_mem_usage 295220 # Number of bytes of host memory used -host_seconds 15008.90 # Real time elapsed on the host +host_inst_rate 163502 # Simulator instruction rate (inst/s) +host_op_rate 182399 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56505895 # Simulator tick rate (ticks/s) +host_mem_usage 249880 # Number of bytes of host memory used +host_seconds 9446.75 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 47680 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 143743296 # Number of bytes read from this memory system.physmem.bytes_read::total 143790976 # Number of bytes read from this memory @@ -327,6 +329,7 @@ system.membus.reqLayer0.occupancy 12926153000 # La system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) system.membus.respLayer1.occupancy 21085487000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 303451211 # Number of BP lookups system.cpu.branchPred.condPredicted 249690817 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15200865 # Number of conditional branches incorrect @@ -668,6 +671,13 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 628.438821 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.306855 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.306855 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 754 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 726 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.368164 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 579143830 # Number of tag accesses +system.cpu.icache.tags.data_accesses 579143830 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 289570320 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 289570320 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 289570320 # number of demand (read+write) hits @@ -756,6 +766,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.436471 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000618 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.525223 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.962312 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29773 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1896 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23750 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3957 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908600 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 111203780 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 111203780 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 6288761 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6288789 # number of ReadReq hits @@ -899,6 +918,14 @@ system.cpu.dcache.tags.warmup_cycle 3547188250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4088.041920 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998057 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 642 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2397 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1056 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1355914350 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1355914350 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 489062653 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 489062653 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 166956698 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 4c52e043e..1a911e7c2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -75,21 +80,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -108,18 +117,21 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -129,7 +141,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -143,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -160,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -169,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index 836ec0832..922328096 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:33:02 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 23:35:09 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index c05db510c..de1eec5b4 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.861538 # Nu sim_ticks 861538200000 # Number of ticks simulated final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2812355 # Simulator instruction rate (inst/s) -host_op_rate 3137389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1568696760 # Simulator tick rate (ticks/s) -host_mem_usage 234512 # Number of bytes of host memory used -host_seconds 549.21 # Real time elapsed on the host +host_inst_rate 2414882 # Simulator instruction rate (inst/s) +host_op_rate 2693979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1346991470 # Simulator tick rate (ticks/s) +host_mem_usage 238968 # Number of bytes of host memory used +host_seconds 639.60 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1723073853 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory system.physmem.bytes_read::total 7759650027 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 9731209155 # To system.membus.throughput 9731209155 # Throughput (bytes/s) system.membus.data_through_bus 8383808419 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 0b3714a01..05924440e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,18 +100,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -115,6 +126,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -123,6 +135,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -137,14 +150,18 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -163,12 +180,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -179,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -187,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -201,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -225,7 +250,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -239,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -256,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -265,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 8e102e919..684ae1ce5 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:46:27 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 23:38:44 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 0ee21876c..3ce47f2c9 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.391205 # Nu sim_ticks 2391205115000 # Number of ticks simulated final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 594937 # Simulator instruction rate (inst/s) -host_op_rate 663956 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 924522029 # Simulator tick rate (ticks/s) -host_mem_usage 240640 # Number of bytes of host memory used -host_seconds 2586.42 # Real time elapsed on the host +host_inst_rate 1202285 # Simulator instruction rate (inst/s) +host_op_rate 1341761 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1868329144 # Simulator tick rate (ticks/s) +host_mem_usage 247832 # Number of bytes of host memory used +host_seconds 1279.86 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory @@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy 11113556000 # La system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -124,6 +127,13 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses +system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits @@ -206,6 +216,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26880 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits @@ -340,6 +359,15 @@ system.cpu.dcache.tags.warmup_cycle 25914401000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1319055826 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1319055826 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 593d636da..40d9825c1 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -76,16 +81,19 @@ icache_port=system.membus.slave[1] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.membus.slave[4] @@ -93,6 +101,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -103,22 +112,26 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -128,7 +141,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +eventq_index=0 +executable=/dist/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -142,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -159,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -168,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 5a2f2668d..ff491d90e 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:38:48 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 21:14:55 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 256e15dc9..5fca1ed49 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1357896 # Simulator instruction rate (inst/s) -host_op_rate 2115724 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1284732870 # Simulator tick rate (ticks/s) -host_mem_usage 240864 # Number of bytes of host memory used -host_seconds 2215.25 # Real time elapsed on the host +host_inst_rate 1743046 # Simulator instruction rate (inst/s) +host_op_rate 2715824 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1649131867 # Simulator tick rate (ticks/s) +host_mem_usage 242928 # Number of bytes of host memory used +host_seconds 1725.76 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory @@ -36,6 +38,8 @@ system.physmem.bw_total::total 13588998587 # To system.membus.throughput 13588998587 # Throughput (bytes/s) system.membus.data_through_bus 38674388193 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 5692014456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 8de21ec08..5c76444e5 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -69,6 +74,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -76,6 +82,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -84,6 +91,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -98,18 +106,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -120,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -128,6 +141,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -142,12 +156,15 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -158,16 +175,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -178,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -186,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -200,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -215,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -224,7 +250,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +eventq_index=0 +executable=/dist/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -238,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -255,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -264,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 2a7659f1c..d2167f766 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:55:52 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 21:25:13 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index f740c02c8..49729ff93 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 5.882581 # Nu sim_ticks 5882580526000 # Number of ticks simulated final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 876676 # Simulator instruction rate (inst/s) -host_op_rate 1365940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1714420225 # Simulator tick rate (ticks/s) -host_mem_usage 249312 # Number of bytes of host memory used -host_seconds 3431.24 # Real time elapsed on the host +host_inst_rate 833754 # Simulator instruction rate (inst/s) +host_op_rate 1299064 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1630482633 # Simulator tick rate (ticks/s) +host_mem_usage 251632 # Number of bytes of host memory used +host_seconds 3607.88 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory @@ -52,6 +54,8 @@ system.membus.reqLayer0.occupancy 11124698000 # La system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 11765161052 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -86,6 +90,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 8026466441 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8026466441 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits @@ -168,6 +178,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 996 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 743 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27921 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 106336271 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106336271 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits @@ -299,6 +318,15 @@ system.cpu.dcache.tags.warmup_cycle 58853922000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits |