diff options
Diffstat (limited to 'tests/long/se/60.bzip2')
7 files changed, 33 insertions, 96 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index a0ce19406..cc971b1f8 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.208778 # Nu sim_ticks 1208777694500 # Number of ticks simulated final_tick 1208777694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 395749 # Simulator instruction rate (inst/s) -host_op_rate 395749 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 261924296 # Simulator tick rate (ticks/s) +host_inst_rate 390102 # Simulator instruction rate (inst/s) +host_op_rate 390102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 258186532 # Simulator tick rate (ticks/s) host_mem_usage 253640 # Number of bytes of host memory used -host_seconds 4614.99 # Real time elapsed on the host +host_seconds 4681.80 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -457,8 +457,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3686603 # number of writebacks system.cpu.dcache.writebacks::total 3686603 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50808 # number of ReadReq MSHR hits @@ -501,7 +499,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194 system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements system.cpu.icache.tags.tagsinuse 750.173547 # Cycle average of tags in use system.cpu.icache.tags.total_refs 597988654 # Total number of references to valid blocks. @@ -559,8 +556,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 3 # number of writebacks system.cpu.icache.writebacks::total 3 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses @@ -587,7 +582,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916 system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1920891 # number of replacements system.cpu.l2cache.tags.tagsinuse 30765.315888 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14409692 # Total number of references to valid blocks. @@ -692,8 +686,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1022139 # number of writebacks system.cpu.l2cache.writebacks::total 1022139 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses @@ -748,7 +740,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77650.283372 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67182.672234 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77655.418921 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77650.283372 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 18249005 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121977 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index f0b14c5aa..f667a67d9 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.669588 # Nu sim_ticks 669587683000 # Number of ticks simulated final_tick 669587683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 206275 # Simulator instruction rate (inst/s) -host_op_rate 206275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79559671 # Simulator tick rate (ticks/s) +host_inst_rate 207572 # Simulator instruction rate (inst/s) +host_op_rate 207572 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 80060022 # Simulator tick rate (ticks/s) host_mem_usage 254664 # Number of bytes of host memory used -host_seconds 8416.17 # Real time elapsed on the host +host_seconds 8363.57 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -730,8 +730,6 @@ system.cpu.dcache.blocked::no_mshrs 1104455 # nu system.cpu.dcache.blocked::no_targets 68040 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.190667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 140.706805 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3727750 # number of writebacks system.cpu.dcache.writebacks::total 3727750 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5562625 # number of ReadReq MSHR hits @@ -782,7 +780,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 753.790798 # Cycle average of tags in use system.cpu.icache.tags.total_refs 420611422 # Total number of references to valid blocks. @@ -841,8 +838,6 @@ system.cpu.icache.blocked::no_mshrs 4 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1 # number of writebacks system.cpu.icache.writebacks::total 1 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 540 # number of ReadReq MSHR hits @@ -875,7 +870,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782 system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1929018 # number of replacements system.cpu.l2cache.tags.tagsinuse 31408.626842 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14580161 # Total number of references to valid blocks. @@ -980,8 +974,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1024304 # number of writebacks system.cpu.l2cache.writebacks::total 1024304 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses @@ -1036,7 +1028,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.259116 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72552.687039 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79672.703483 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.259116 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 18419450 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207203 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 2fb4a6971..86be7ae28 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.636720 # Nu sim_ticks 2636719559500 # Number of ticks simulated final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1488641 # Simulator instruction rate (inst/s) -host_op_rate 1488641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2156924734 # Simulator tick rate (ticks/s) -host_mem_usage 297352 # Number of bytes of host memory used -host_seconds 1222.44 # Real time elapsed on the host +host_inst_rate 1392133 # Simulator instruction rate (inst/s) +host_op_rate 1392132 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2017091448 # Simulator tick rate (ticks/s) +host_mem_usage 252104 # Number of bytes of host memory used +host_seconds 1307.19 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,8 +200,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3679426 # number of writebacks system.cpu.dcache.writebacks::total 3679426 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses @@ -236,7 +234,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. @@ -295,8 +292,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1 # number of writebacks system.cpu.icache.writebacks::total 1 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses @@ -323,7 +318,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1919525 # number of replacements system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks. @@ -428,8 +422,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1021962 # number of writebacks system.cpu.l2cache.writebacks::total 1021962 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses @@ -484,7 +476,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.374326 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 0b0903e3c..80a1c9ff6 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.116866 # Nu sim_ticks 1116865668500 # Number of ticks simulated final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 315195 # Simulator instruction rate (inst/s) -host_op_rate 339575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 227915704 # Simulator tick rate (ticks/s) -host_mem_usage 272300 # Number of bytes of host memory used -host_seconds 4900.35 # Real time elapsed on the host +host_inst_rate 304077 # Simulator instruction rate (inst/s) +host_op_rate 327597 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 219876370 # Simulator tick rate (ticks/s) +host_mem_usage 272296 # Number of bytes of host memory used +host_seconds 5079.52 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -548,8 +548,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3684567 # number of writebacks system.cpu.dcache.writebacks::total 3684567 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits @@ -600,7 +598,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. @@ -659,8 +656,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 29 # number of writebacks system.cpu.icache.writebacks::total 29 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses @@ -687,7 +682,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 2013919 # number of replacements system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. @@ -796,8 +790,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks system.cpu.l2cache.writebacks::total 1050123 # number of writebacks system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits @@ -858,7 +850,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77530.075135 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index ad14d9d64..c43dbec03 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.767804 # Nu sim_ticks 767803843500 # Number of ticks simulated final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188017 # Simulator instruction rate (inst/s) -host_op_rate 202560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93463451 # Simulator tick rate (ticks/s) -host_mem_usage 313392 # Number of bytes of host memory used -host_seconds 8215.02 # Real time elapsed on the host +host_inst_rate 224780 # Simulator instruction rate (inst/s) +host_op_rate 242166 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 111738196 # Simulator tick rate (ticks/s) +host_mem_usage 312364 # Number of bytes of host memory used +host_seconds 6871.45 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -809,8 +809,6 @@ system.cpu.dcache.blocked::no_mshrs 943594 # nu system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks system.cpu.dcache.writebacks::total 17003710 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits @@ -863,7 +861,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 589 # number of replacements system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. @@ -922,8 +919,6 @@ system.cpu.icache.blocked::no_mshrs 183 # nu system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 589 # number of writebacks system.cpu.icache.writebacks::total 589 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits @@ -956,7 +951,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue @@ -1086,8 +1080,6 @@ system.cpu.l2cache.blocked::no_mshrs 1 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference system.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks system.cpu.l2cache.writebacks::total 1635896 # number of writebacks @@ -1171,7 +1163,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 232fe8b45..af0dd5de2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.377030 # Nu sim_ticks 2377029670500 # Number of ticks simulated final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 872363 # Simulator instruction rate (inst/s) -host_op_rate 940093 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1347600333 # Simulator tick rate (ticks/s) -host_mem_usage 317216 # Number of bytes of host memory used -host_seconds 1763.90 # Real time elapsed on the host +host_inst_rate 1034140 # Simulator instruction rate (inst/s) +host_op_rate 1114431 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1597508455 # Simulator tick rate (ticks/s) +host_mem_usage 269992 # Number of bytes of host memory used +host_seconds 1487.96 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -300,8 +300,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks system.cpu.dcache.writebacks::total 3681379 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses @@ -344,7 +342,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. @@ -403,8 +400,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 7 # number of writebacks system.cpu.icache.writebacks::total 7 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses @@ -431,7 +426,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1919027 # number of replacements system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks. @@ -540,8 +534,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks system.cpu.l2cache.writebacks::total 1021127 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses @@ -596,7 +588,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index d16f022eb..aea63bd4a 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.895948 # Nu sim_ticks 5895947852500 # Number of ticks simulated final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 730138 # Simulator instruction rate (inst/s) -host_op_rate 1137621 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1431096811 # Simulator tick rate (ticks/s) -host_mem_usage 317400 # Number of bytes of host memory used -host_seconds 4119.88 # Real time elapsed on the host +host_inst_rate 781389 # Simulator instruction rate (inst/s) +host_op_rate 1217475 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1531550481 # Simulator tick rate (ticks/s) +host_mem_usage 272448 # Number of bytes of host memory used +host_seconds 3849.66 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -171,8 +171,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks system.cpu.dcache.writebacks::total 3682716 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses @@ -207,7 +205,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10 # number of replacements system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. @@ -265,8 +262,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 10 # number of writebacks system.cpu.icache.writebacks::total 10 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses @@ -293,7 +288,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1919169 # number of replacements system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks. @@ -398,8 +392,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks system.cpu.l2cache.writebacks::total 1022289 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses @@ -454,7 +446,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |