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-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt423
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt1281
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt1275
3 files changed, 1467 insertions, 1512 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index bbfef95ab..4d872659d 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.993559 # Nu
sim_ticks 993559170500 # Number of ticks simulated
final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 148425 # Simulator instruction rate (inst/s)
-host_op_rate 148425 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 81036604 # Simulator tick rate (ticks/s)
-host_mem_usage 464668 # Number of bytes of host memory used
-host_seconds 12260.62 # Real time elapsed on the host
+host_inst_rate 139940 # Simulator instruction rate (inst/s)
+host_op_rate 139940 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 76403951 # Simulator tick rate (ticks/s)
+host_mem_usage 449176 # Number of bytes of host memory used
+host_seconds 13004.03 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
@@ -85,30 +85,17 @@ system.physmem.readPktSize::3 0 # Ca
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 1959688 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 1018171 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1630106 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 205346 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 87736 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 35917 # What read queue length does an incoming req see
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 1018058 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1630116 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 205318 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 87737 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 35934 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@@ -137,9 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 43771 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 43773 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see
@@ -162,7 +148,7 @@ system.physmem.wrQLenPdf::20 44263 # Wh
system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 493 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 491 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see
@@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 5 # Wh
system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 35848625999 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 104288840999 # Sum of mem lat for all requests
+system.physmem.totQLat 35843451500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 104284202750 # Sum of mem lat for all requests
system.physmem.totBusLat 9795530000 # Total cycles spent in databus access
-system.physmem.totBankLat 58644685000 # Total cycles spent in bank access
-system.physmem.avgQLat 18298.46 # Average queueing delay per request
-system.physmem.avgBankLat 29934.41 # Average bank access latency per request
+system.physmem.totBankLat 58645221250 # Total cycles spent in bank access
+system.physmem.avgQLat 18295.82 # Average queueing delay per request
+system.physmem.avgBankLat 29934.69 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 53232.87 # Average memory access latency
+system.physmem.avgMemAccLat 53230.51 # Average memory access latency
system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s
@@ -187,13 +172,13 @@ system.physmem.peakBW 12800.00 # Th
system.physmem.busUtil 1.50 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.10 # Average read queue length over time
system.physmem.avgWrQLen 10.46 # Average write queue length over time
-system.physmem.readRowHits 770935 # Number of row buffer hits during reads
-system.physmem.writeRowHits 285714 # Number of row buffer hits during writes
+system.physmem.readRowHits 770937 # Number of row buffer hits during reads
+system.physmem.writeRowHits 285715 # Number of row buffer hits during writes
system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes
system.physmem.avgGap 333661.47 # Average gap between requests
system.cpu.branchPred.lookups 326540496 # Number of BP lookups
-system.cpu.branchPred.condPredicted 252608544 # Number of conditional branches predicted
+system.cpu.branchPred.condPredicted 252608543 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups
system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits
@@ -205,22 +190,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 444796007 # DTB read hits
+system.cpu.dtb.read_hits 444796009 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 449693085 # DTB read accesses
-system.cpu.dtb.write_hits 160833351 # DTB write hits
+system.cpu.dtb.read_accesses 449693087 # DTB read accesses
+system.cpu.dtb.write_hits 160833358 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 162534655 # DTB write accesses
-system.cpu.dtb.data_hits 605629358 # DTB hits
+system.cpu.dtb.write_accesses 162534662 # DTB write accesses
+system.cpu.dtb.data_hits 605629367 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 612227740 # DTB accesses
-system.cpu.itb.fetch_hits 232025962 # ITB hits
+system.cpu.dtb.data_accesses 612227749 # DTB accesses
+system.cpu.itb.fetch_hits 232025963 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 232025984 # ITB accesses
+system.cpu.itb.fetch_accesses 232025985 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -237,16 +222,16 @@ system.cpu.workload.num_syscalls 29 # Nu
system.cpu.numCycles 1987118342 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken 172378846 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 154161650 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 1667662469 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedTaken 172378847 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 154161649 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 1667662468 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 3043865086 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 3043865085 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 651727789 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 617884568 # Number of Address Generations
+system.cpu.regfile_manager.regForwards 651727790 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 617884569 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted
@@ -256,12 +241,12 @@ system.cpu.execution_unit.executions 1139371391 # Nu
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 1741838166 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 1741838474 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 7484554 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 415293759 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 1571824583 # Number of cycles cpu stages are processed.
-system.cpu.activity 79.100703 # Percentage of cycles cpu is active
+system.cpu.timesIdled 7484621 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 415293731 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 1571824611 # Number of cycles cpu stages are processed.
+system.cpu.activity 79.100705 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
@@ -279,66 +264,66 @@ system.cpu.cpi_total 1.091955 # CP
system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 800261653 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 1186856689 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 59.727529 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 1053419210 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 933699132 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.idleCycles 800261647 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 1186856695 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 59.727530 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 1053419200 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 933699142 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 1014725197 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 972393145 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 48.934838 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 1577495451 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 409622891 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.idleCycles 1014725184 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 972393158 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 48.934839 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 1577495448 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 409622894 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 965781597 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 1021336745 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.idleCycles 965781598 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 1021336744 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 667.839755 # Cycle average of tags in use
-system.cpu.icache.total_refs 232024853 # Total number of references to valid blocks.
+system.cpu.icache.total_refs 232024854 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 270110.422584 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 270110.423749 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 667.839755 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.326094 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.326094 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 232024853 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 232024853 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 232024853 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 232024853 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 232024853 # number of overall hits
-system.cpu.icache.overall_hits::total 232024853 # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst 232024854 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 232024854 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 232024854 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 232024854 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 232024854 # number of overall hits
+system.cpu.icache.overall_hits::total 232024854 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1109 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1109 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses
system.cpu.icache.overall_misses::total 1109 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 64824000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 64824000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 64824000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 64824000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 64824000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 64824000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 232025962 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 232025962 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 232025962 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 232025962 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 232025962 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 232025962 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 64819000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 64819000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 64819000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 64819000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 64819000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 64819000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 232025963 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 232025963 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 232025963 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 232025963 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 232025963 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 232025963 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58452.660054 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 58452.660054 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 58452.660054 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 58452.660054 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58448.151488 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 58448.151488 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 58448.151488 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 58448.151488 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
@@ -359,34 +344,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 859
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51094000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 51094000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51094000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 51094000 # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31308.868607 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31308.868607 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 13465422 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 4771270 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 372557 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65753 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.141221 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 72.557298 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.143253 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 72.563533 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3693293 # number of writebacks
system.cpu.dcache.writebacks::total 3693293 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595195 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2595195 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2699817 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2699817 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2699817 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2699817 # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595235 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2595235 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2699857 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2699857 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2699857 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2699857 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses
@@ -596,14 +581,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111468
system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964459500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964459500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79317190500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 79317190500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230281650000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 230281650000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230281650000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 230281650000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964297500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964297500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79314869000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 79314869000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230279166500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 230279166500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230279166500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 230279166500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
@@ -612,14 +597,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.595412 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.595412 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41984.872048 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41984.872048 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.572981 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.572981 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41983.643211 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41983.643211 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index db2985766..e183c5fce 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,117 +1,104 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.665563 # Number of seconds simulated
-sim_ticks 665562897500 # Number of ticks simulated
-final_tick 665562897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.665771 # Number of seconds simulated
+sim_ticks 665770972500 # Number of ticks simulated
+final_tick 665770972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 181531 # Simulator instruction rate (inst/s)
-host_op_rate 181531 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 69595242 # Simulator tick rate (ticks/s)
-host_mem_usage 467736 # Number of bytes of host memory used
-host_seconds 9563.34 # Real time elapsed on the host
+host_inst_rate 179472 # Simulator instruction rate (inst/s)
+host_op_rate 179472 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68827168 # Simulator tick rate (ticks/s)
+host_mem_usage 452252 # Number of bytes of host memory used
+host_seconds 9673.08 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125801472 # Number of bytes read from this memory
-system.physmem.bytes_read::total 125863104 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65262912 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65262912 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1965648 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1966611 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1019733 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1019733 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 92601 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 189015152 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 189107753 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 92601 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 92601 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 98056716 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 98056716 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 98056716 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 92601 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 189015152 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 287164469 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1966611 # Total number of read requests seen
-system.physmem.writeReqs 1019733 # Total number of write requests seen
-system.physmem.cpureqs 2988993 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 125863104 # Total number of bytes read from memory
-system.physmem.bytesWritten 65262912 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 125863104 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 65262912 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 562 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 62016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125796608 # Number of bytes read from this memory
+system.physmem.bytes_read::total 125858624 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 62016 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 62016 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 65265344 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65265344 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 969 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1965572 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1966541 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1019771 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1019771 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 93149 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 188948772 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 189041922 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 93149 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 93149 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 98029723 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 98029723 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 98029723 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 93149 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 188948772 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 287071645 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1966541 # Total number of read requests seen
+system.physmem.writeReqs 1019771 # Total number of write requests seen
+system.physmem.cpureqs 2988947 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 125858624 # Total number of bytes read from memory
+system.physmem.bytesWritten 65265344 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 125858624 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 65265344 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 566 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 122665 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 122306 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 122208 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 124220 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 123661 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 122580 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 120700 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 121417 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 122611 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 122314 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 122187 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 124202 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 123643 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 122594 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 120701 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 121432 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 121606 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 122292 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 121462 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 123460 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 125578 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 124270 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 123173 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 124451 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 63478 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 62392 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 63122 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 63842 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 64138 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 63875 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 63473 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 63461 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 63474 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 63840 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 63360 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 64241 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 64652 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 64261 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 63751 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 64373 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::9 122264 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 121460 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 123481 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 125598 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 124291 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 123180 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 124411 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 63480 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 62406 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 63107 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 63843 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 64137 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 63874 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 63470 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 63464 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 63489 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 63818 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 63362 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 64260 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 64664 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 64287 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 63760 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 64350 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 2649 # Number of times wr buffer was full causing retry
-system.physmem.totGap 665562829000 # Total gap between requests
+system.physmem.numWrRetry 2635 # Number of times wr buffer was full causing retry
+system.physmem.totGap 665770904000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 1966611 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 1022382 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1625792 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 234895 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 77536 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 27805 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 1966541 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 1019771 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1625771 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 234883 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 77503 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 27794 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
@@ -137,90 +124,88 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 42397 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 43965 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 44248 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 44303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 44315 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 44317 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 44319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 44319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 44320 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1940 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 372 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 89 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 34 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 42250 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 43943 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 44238 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 44300 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 44316 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 44321 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 44321 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 44322 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 44322 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 2088 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 395 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 34363983237 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 102498683237 # Sum of mem lat for all requests
-system.physmem.totBusLat 9830245000 # Total cycles spent in databus access
-system.physmem.totBankLat 58304455000 # Total cycles spent in bank access
-system.physmem.avgQLat 17478.70 # Average queueing delay per request
-system.physmem.avgBankLat 29655.65 # Average bank access latency per request
+system.physmem.totQLat 34478547500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 102599787500 # Sum of mem lat for all requests
+system.physmem.totBusLat 9829875000 # Total cycles spent in databus access
+system.physmem.totBankLat 58291365000 # Total cycles spent in bank access
+system.physmem.avgQLat 17537.63 # Average queueing delay per request
+system.physmem.avgBankLat 29650.10 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 52134.35 # Average memory access latency
-system.physmem.avgRdBW 189.11 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 98.06 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 189.11 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 98.06 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 52187.74 # Average memory access latency
+system.physmem.avgRdBW 189.04 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 98.03 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 189.04 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 98.03 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.24 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
-system.physmem.avgWrQLen 10.79 # Average write queue length over time
-system.physmem.readRowHits 776053 # Number of row buffer hits during reads
-system.physmem.writeRowHits 286138 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 39.47 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes
-system.physmem.avgGap 222868.77 # Average gap between requests
-system.cpu.branchPred.lookups 381322658 # Number of BP lookups
-system.cpu.branchPred.condPredicted 296346711 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 16069927 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 262182430 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 259521497 # Number of BTB hits
+system.physmem.avgWrQLen 10.14 # Average write queue length over time
+system.physmem.readRowHits 776350 # Number of row buffer hits during reads
+system.physmem.writeRowHits 285987 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 39.49 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 28.04 # Row buffer hit rate for writes
+system.physmem.avgGap 222940.84 # Average gap between requests
+system.cpu.branchPred.lookups 381390262 # Number of BP lookups
+system.cpu.branchPred.condPredicted 296397889 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 16086653 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 262140629 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 259559256 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.985083 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 24701305 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 3076 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.015272 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 24699160 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3055 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 613798645 # DTB read hits
-system.cpu.dtb.read_misses 11251599 # DTB read misses
+system.cpu.dtb.read_hits 613788534 # DTB read hits
+system.cpu.dtb.read_misses 11249325 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 625050244 # DTB read accesses
-system.cpu.dtb.write_hits 212271089 # DTB write hits
-system.cpu.dtb.write_misses 7143652 # DTB write misses
+system.cpu.dtb.read_accesses 625037859 # DTB read accesses
+system.cpu.dtb.write_hits 212245958 # DTB write hits
+system.cpu.dtb.write_misses 7142739 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 219414741 # DTB write accesses
-system.cpu.dtb.data_hits 826069734 # DTB hits
-system.cpu.dtb.data_misses 18395251 # DTB misses
+system.cpu.dtb.write_accesses 219388697 # DTB write accesses
+system.cpu.dtb.data_hits 826034492 # DTB hits
+system.cpu.dtb.data_misses 18392064 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 844464985 # DTB accesses
-system.cpu.itb.fetch_hits 390709896 # ITB hits
-system.cpu.itb.fetch_misses 44 # ITB misses
+system.cpu.dtb.data_accesses 844426556 # DTB accesses
+system.cpu.itb.fetch_hits 390787767 # ITB hits
+system.cpu.itb.fetch_misses 43 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 390709940 # ITB accesses
+system.cpu.itb.fetch_accesses 390787810 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -234,98 +219,98 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1331125796 # number of cpu cycles simulated
+system.cpu.numCycles 1331541946 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 402151320 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3159313188 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 381322658 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 284222802 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 574163176 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 140279243 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 173671179 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1322 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 390709896 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 8056983 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1266457048 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.494607 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.152796 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 402238482 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3159760476 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 381390262 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 284258416 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 574242721 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 140320135 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 173885771 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1317 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 44 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 390787767 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 8065204 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1266865295 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.494157 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.152669 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 692293872 54.66% 54.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 42630313 3.37% 58.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 21744461 1.72% 59.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 39673370 3.13% 62.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 129246893 10.21% 73.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 61513639 4.86% 77.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38552077 3.04% 80.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 28113770 2.22% 83.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 212688653 16.79% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 692622574 54.67% 54.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 42615431 3.36% 58.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 21758353 1.72% 59.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 39697295 3.13% 62.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 129259260 10.20% 73.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 61526950 4.86% 77.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 38544819 3.04% 80.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 28129154 2.22% 83.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 212711459 16.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1266457048 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.286466 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.373414 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 433835858 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 155176701 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 542390430 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 18584911 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 116469148 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 58290582 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 824 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3086789571 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2029 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 116469148 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 456704578 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 101399871 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 7042 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 535436988 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 56439421 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3004825157 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 566473 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1727265 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 50367655 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2246602827 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3897066108 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3895827965 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1238143 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1266865295 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.286428 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.373009 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 433949818 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 155380202 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 542435049 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 18604092 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 116496134 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 58311036 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 855 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3087126857 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2089 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 116496134 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 456815247 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 101557658 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 5194 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 535499027 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 56492035 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3005134049 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 566488 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1739616 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 50408333 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2246840239 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3897438135 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3896197591 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1240544 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 870399864 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 162 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 161 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 121306422 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 679329311 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 255341435 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 67772546 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 36892101 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2723405673 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2508908939 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3097394 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 978157995 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 414914582 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1266457048 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.981045 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.973109 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 870637276 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 168 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 166 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 121366950 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 679350790 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 255350759 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 67967300 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 37114772 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2723579625 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 126 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2508981641 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3091159 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 978310045 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 415071720 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 97 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1266865295 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.980464 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.972855 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 426262331 33.66% 33.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 201879469 15.94% 49.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 185440300 14.64% 64.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 153069981 12.09% 76.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 133127020 10.51% 86.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 81075751 6.40% 93.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 65263497 5.15% 98.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 15238482 1.20% 99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 5100217 0.40% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 426523141 33.67% 33.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 201951837 15.94% 49.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 185492394 14.64% 64.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 153160708 12.09% 76.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 133131866 10.51% 86.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 81031270 6.40% 93.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 65244416 5.15% 98.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 15224722 1.20% 99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 5104941 0.40% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1266457048 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1266865295 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2147356 11.64% 11.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2143481 11.64% 11.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.64% # attempts to use FU when none available
@@ -354,118 +339,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.64% # at
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 11882629 64.43% 76.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4412064 23.92% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 11871999 64.46% 76.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4401590 23.90% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1643457358 65.50% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 108 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 38 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 641426814 25.57% 91.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 224024134 8.93% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1643559437 65.51% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 106 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 261 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 31 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 641411468 25.56% 91.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 224010136 8.93% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2508908939 # Type of FU issued
-system.cpu.iq.rate 1.884802 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 18442049 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007351 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6303917077 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3700456251 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2412530118 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1897292 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1213669 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 850482 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2526413076 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 937912 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 62601543 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2508981641 # Type of FU issued
+system.cpu.iq.rate 1.884268 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 18417070 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.007340 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6304440735 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3700781380 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2412589185 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1896071 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1214370 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 849902 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2526461544 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 937167 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 62583251 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 234733648 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 263681 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 107887 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 94612933 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 234755127 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 263530 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 107682 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 94622257 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 149 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1508556 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 167 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1505929 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 116469148 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 45249808 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1153798 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2865411802 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 8865893 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 679329311 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 255341435 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 296621 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 17062 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 107887 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 10351897 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8549059 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 18900956 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2461552831 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 625050873 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 47356108 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 116496134 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 45259128 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1153276 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2865598045 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 8882954 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 679350790 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 255350759 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 126 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 296462 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 17110 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 107682 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 10363121 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 8561161 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 18924282 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2461596227 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 625038408 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 47385414 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 142006007 # number of nop insts executed
-system.cpu.iew.exec_refs 844465652 # number of memory reference insts executed
-system.cpu.iew.exec_branches 300780520 # Number of branches executed
-system.cpu.iew.exec_stores 219414779 # Number of stores executed
-system.cpu.iew.exec_rate 1.849226 # Inst execution rate
-system.cpu.iew.wb_sent 2441340597 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2413380600 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1388547079 # num instructions producing a value
-system.cpu.iew.wb_consumers 1764258867 # num instructions consuming a value
+system.cpu.iew.exec_nop 142018294 # number of nop insts executed
+system.cpu.iew.exec_refs 844427141 # number of memory reference insts executed
+system.cpu.iew.exec_branches 300792164 # Number of branches executed
+system.cpu.iew.exec_stores 219388733 # Number of stores executed
+system.cpu.iew.exec_rate 1.848681 # Inst execution rate
+system.cpu.iew.wb_sent 2441396740 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2413439087 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1388573479 # num instructions producing a value
+system.cpu.iew.wb_consumers 1764243384 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.813037 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.787043 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.812515 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.787065 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 824496541 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 824671147 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 16069169 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1149987900 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.582434 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.513328 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 16085857 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1150369161 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.581910 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.512649 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 636582703 55.36% 55.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 174528815 15.18% 70.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 86154838 7.49% 78.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 53696009 4.67% 82.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 34510870 3.00% 85.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 25214106 2.19% 87.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 21871895 1.90% 89.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 22921084 1.99% 91.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 94507580 8.22% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 636844570 55.36% 55.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 174611268 15.18% 70.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 86171312 7.49% 78.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 53631613 4.66% 82.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 34569452 3.01% 85.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 25367501 2.21% 87.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 21831937 1.90% 89.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 22907604 1.99% 91.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 94433904 8.21% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1149987900 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1150369161 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -476,189 +461,189 @@ system.cpu.commit.branches 214632552 # Nu
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 94507580 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 94433904 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3613977787 # The number of ROB reads
-system.cpu.rob.rob_writes 5405122718 # The number of ROB writes
-system.cpu.timesIdled 818240 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 64668748 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3614607330 # The number of ROB reads
+system.cpu.rob.rob_writes 5405498913 # The number of ROB writes
+system.cpu.timesIdled 817784 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 64676651 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
-system.cpu.cpi 0.766758 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.766758 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.304192 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.304192 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3317304663 # number of integer regfile reads
-system.cpu.int_regfile_writes 1931628776 # number of integer regfile writes
-system.cpu.fp_regfile_reads 30090 # number of floating regfile reads
-system.cpu.fp_regfile_writes 557 # number of floating regfile writes
+system.cpu.cpi 0.766998 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.766998 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.303785 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.303785 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3317361939 # number of integer regfile reads
+system.cpu.int_regfile_writes 1931707111 # number of integer regfile writes
+system.cpu.fp_regfile_reads 30073 # number of floating regfile reads
+system.cpu.fp_regfile_writes 529 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.tagsinuse 772.264197 # Cycle average of tags in use
-system.cpu.icache.total_refs 390708412 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 963 # Sample count of references to valid blocks.
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@@ -667,180 +652,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 44113.397678 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 431500 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 431500 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31727.257337 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31727.257337 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31727.257337 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31727.257337 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 12329196 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 5816488 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 735313 # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.023022 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.023022 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.023022 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.023022 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26145.856854 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26145.856854 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44087.783760 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 44087.783760 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31718.737826 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31718.737826 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 12309965 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 5809756 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 734892 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.767276 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 89.300335 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.750713 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 89.196979 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3725054 # number of writebacks
-system.cpu.dcache.writebacks::total 3725054 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3985636 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3985636 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198598 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3198598 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7184234 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7184234 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7184234 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7184234 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296792 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7296792 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883566 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1883566 # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 3724718 # number of writebacks
+system.cpu.dcache.writebacks::total 3724718 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3983366 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 3983366 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198630 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3198630 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7181996 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7181996 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7181996 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7181996 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296577 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7296577 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883555 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1883555 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9180358 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9180358 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9180358 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9180358 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159255490500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 159255490500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71503545346 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 71503545346 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 429500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 429500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230759035846 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 230759035846 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230759035846 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 230759035846 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9180132 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9180132 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9180132 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9180132 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159251608500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 159251608500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71602703007 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 71602703007 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 47500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 47500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230854311507 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 230854311507 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230854311507 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 230854311507 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013267 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013267 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.411839 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.411839 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37961.794461 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37961.794461 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 429500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 429500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.522913 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.522913 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38014.660048 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38014.660048 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 47500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 47500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index fe58c49f1..dd9108dcd 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,115 +1,102 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.517386 # Number of seconds simulated
-sim_ticks 517386177000 # Number of ticks simulated
-final_tick 517386177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.517371 # Number of seconds simulated
+sim_ticks 517371024000 # Number of ticks simulated
+final_tick 517371024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 165493 # Simulator instruction rate (inst/s)
-host_op_rate 184620 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 55435711 # Simulator tick rate (ticks/s)
-host_mem_usage 502788 # Number of bytes of host memory used
-host_seconds 9333.08 # Real time elapsed on the host
+host_inst_rate 170437 # Simulator instruction rate (inst/s)
+host_op_rate 190135 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57090080 # Simulator tick rate (ticks/s)
+host_mem_usage 485276 # Number of bytes of host memory used
+host_seconds 9062.36 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1723073835 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 143728256 # Number of bytes read from this memory
-system.physmem.bytes_read::total 143776256 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 48000 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 48000 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 70436224 # Number of bytes written to this memory
-system.physmem.bytes_written::total 70436224 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 750 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2245754 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2246504 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1100566 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1100566 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 92774 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 277796861 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 277889635 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 92774 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 92774 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 136138589 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 136138589 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 136138589 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 92774 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 277796861 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 414028224 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 2246504 # Total number of read requests seen
-system.physmem.writeReqs 1100566 # Total number of write requests seen
-system.physmem.cpureqs 3350665 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 143776256 # Total number of bytes read from memory
-system.physmem.bytesWritten 70436224 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 143776256 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 70436224 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 651 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 143734144 # Number of bytes read from this memory
+system.physmem.bytes_read::total 143782208 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 70446784 # Number of bytes written to this memory
+system.physmem.bytes_written::total 70446784 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2245846 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2246597 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1100731 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1100731 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 92900 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 277816378 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 277909279 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 92900 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 92900 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 136162987 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 136162987 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 136162987 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 92900 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 277816378 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 414072265 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2246597 # Total number of read requests seen
+system.physmem.writeReqs 1100731 # Total number of write requests seen
+system.physmem.cpureqs 3350452 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 143782208 # Total number of bytes read from memory
+system.physmem.bytesWritten 70446784 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 143782208 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 70446784 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 642 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 141458 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 139475 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 141540 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 141707 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 142337 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 139999 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 141291 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 140517 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 138551 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 136478 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 140625 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 140699 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 141026 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 139159 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 139234 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 141757 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 69121 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 68349 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 69146 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 69473 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 69281 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 68946 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 69052 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 68358 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 67825 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 67029 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 69533 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 69302 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 69105 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 68630 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 141495 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 139690 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 141603 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 141749 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 142295 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 140068 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 141091 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 140693 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 138519 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 136203 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 140642 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 140693 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 141066 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 139208 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 139271 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 141669 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 69094 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 68448 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 69171 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 69468 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 69338 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 68952 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 69046 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 68406 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 67828 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 66957 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 69534 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 69263 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 69109 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 68653 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 68505 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 68911 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 68959 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 3595 # Number of times wr buffer was full causing retry
-system.physmem.totGap 517386097500 # Total gap between requests
+system.physmem.numWrRetry 3124 # Number of times wr buffer was full causing retry
+system.physmem.totGap 517370944500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 2246504 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 1104161 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1563469 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 451045 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 162632 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 68688 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 2246597 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 1100731 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1563680 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 451075 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 162592 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 68583 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -137,70 +124,68 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 44097 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 47155 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 47729 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 47801 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 47826 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 47832 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 47832 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 47832 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 47832 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 3754 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 696 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 122 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 51687050307 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 131176334057 # Sum of mem lat for all requests
-system.physmem.totBusLat 11229265000 # Total cycles spent in databus access
-system.physmem.totBankLat 68260018750 # Total cycles spent in bank access
-system.physmem.avgQLat 23014.44 # Average queueing delay per request
-system.physmem.avgBankLat 30393.81 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 44125 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 47135 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 47739 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 47809 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 47835 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 47837 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 47838 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 47840 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 47857 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 47857 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 47857 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 3733 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 723 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 119 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 29 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see
+system.physmem.totQLat 51812524750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 131293078500 # Sum of mem lat for all requests
+system.physmem.totBusLat 11229775000 # Total cycles spent in databus access
+system.physmem.totBankLat 68250778750 # Total cycles spent in bank access
+system.physmem.avgQLat 23069.26 # Average queueing delay per request
+system.physmem.avgBankLat 30388.31 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 58408.25 # Average memory access latency
-system.physmem.avgRdBW 277.89 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 136.14 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 277.89 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 136.14 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 58457.57 # Average memory access latency
+system.physmem.avgRdBW 277.91 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 136.16 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 277.91 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 136.16 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.23 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.25 # Average read queue length over time
-system.physmem.avgWrQLen 10.38 # Average write queue length over time
-system.physmem.readRowHits 827421 # Number of row buffer hits during reads
-system.physmem.writeRowHits 271011 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 36.84 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 24.62 # Row buffer hit rate for writes
-system.physmem.avgGap 154578.81 # Average gap between requests
-system.cpu.branchPred.lookups 303247532 # Number of BP lookups
-system.cpu.branchPred.condPredicted 249450034 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 15218023 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 175041543 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 161435617 # Number of BTB hits
+system.physmem.avgWrQLen 10.92 # Average write queue length over time
+system.physmem.readRowHits 827855 # Number of row buffer hits during reads
+system.physmem.writeRowHits 271156 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 36.86 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 24.63 # Row buffer hit rate for writes
+system.physmem.avgGap 154562.37 # Average gap between requests
+system.cpu.branchPred.lookups 303290886 # Number of BP lookups
+system.cpu.branchPred.condPredicted 249488582 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15222231 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 174596646 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 161469311 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 92.227030 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 17558020 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 197 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 92.481336 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 17557313 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 202 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -244,133 +229,133 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 1034772355 # number of cpu cycles simulated
+system.cpu.numCycles 1034742049 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 298171037 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2186159989 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 303247532 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 178993637 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 435067157 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 87822274 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 155469980 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 663 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 288529454 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5728473 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 958589014 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.523348 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.213310 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 298209547 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2186343540 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 303290886 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 179026624 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 435120674 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 87852250 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 155399906 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 380 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 288562414 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 5732154 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 958634216 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.523474 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.213325 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 523521931 54.61% 54.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 25504837 2.66% 57.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 39086427 4.08% 61.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 48350867 5.04% 66.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 43002654 4.49% 70.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46446539 4.85% 75.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38408277 4.01% 79.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 18709630 1.95% 81.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 175557852 18.31% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 523513675 54.61% 54.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 25518990 2.66% 57.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 39095186 4.08% 61.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 48349741 5.04% 66.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 43010158 4.49% 70.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46440341 4.84% 75.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 38425121 4.01% 79.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 18710957 1.95% 81.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 175570047 18.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 958589014 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.293057 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.112697 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 329732299 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 133726687 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 405163333 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 20087198 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 69879497 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 46055159 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 678 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2366957956 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2458 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 69879497 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 353264569 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 63487571 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 18775 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 400193247 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 71745355 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2304463172 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 133379 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5038858 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 58609164 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 17 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2279851599 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 10642208168 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 10642204755 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 3413 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 958634216 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.293108 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.112936 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 329763250 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 133666994 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 405221512 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 20079412 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 69903048 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46058380 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2367190993 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2433 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 69903048 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 353304996 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 63447183 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 15614 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 400231748 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 71731627 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2304653779 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 133097 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5040028 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 58589233 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 7 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2280042978 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 10643127773 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 10643124880 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2893 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 573531669 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 681 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 678 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 158828994 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 624462299 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 220966139 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 86157140 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 71007424 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2201342631 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 714 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2018151759 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3999657 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 473702297 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1125076843 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 544 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 958589014 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.105336 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.906417 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 573723048 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 497 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 494 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 158827938 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 624515157 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 220983969 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 86332349 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 71315853 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2201513470 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2018112827 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 4002858 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 473886256 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1126241029 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 958634216 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.105196 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.906381 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 277560944 28.96% 28.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 151408943 15.79% 44.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 161184316 16.81% 61.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 119741050 12.49% 74.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 124054843 12.94% 87.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 73850392 7.70% 94.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 38407609 4.01% 98.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 9813288 1.02% 99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2567629 0.27% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 277594004 28.96% 28.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 151404549 15.79% 44.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 161201477 16.82% 61.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 119812250 12.50% 74.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 123999377 12.94% 87.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 73820536 7.70% 94.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 38419650 4.01% 98.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 9808498 1.02% 99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2573875 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 958589014 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 958634216 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 872793 3.65% 3.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5710 0.02% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 18283969 76.42% 80.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4762893 19.91% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 872312 3.66% 3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5645 0.02% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 18268766 76.62% 80.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4697940 19.70% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1236667909 61.28% 61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 925774 0.05% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1236677496 61.28% 61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 926030 0.05% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
@@ -392,90 +377,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 33 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 24 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 587469094 29.11% 90.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 193088896 9.57% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 587482532 29.11% 90.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 193026708 9.56% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2018151759 # Type of FU issued
-system.cpu.iq.rate 1.950334 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 23925365 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.011855 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5022817228 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2675235301 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1957490366 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2042076961 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 163 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 64626006 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2018112827 # Type of FU issued
+system.cpu.iq.rate 1.950354 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 23844663 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.011815 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5022707128 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2675590256 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1957438118 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 556 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2041957357 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 64629974 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 138535530 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 270863 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 192819 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 46119094 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 138588388 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 271831 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 192988 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 46136924 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4653355 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 4659196 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 69879497 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28935964 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1499081 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2201343583 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 6151222 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 624462299 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 220966139 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 652 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 473850 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 90091 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 192819 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 8153540 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 9614603 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 17768143 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1988132356 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 573881676 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 30019403 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 69903048 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 28888784 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1501235 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2201514122 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 6139547 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 624515157 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 220983969 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 460 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 475783 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 89669 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 192988 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 8156378 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 9617829 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 17774207 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1988116656 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 573901246 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 29996171 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 238 # number of nop insts executed
-system.cpu.iew.exec_refs 764075762 # number of memory reference insts executed
-system.cpu.iew.exec_branches 238335526 # Number of branches executed
-system.cpu.iew.exec_stores 190194086 # Number of stores executed
-system.cpu.iew.exec_rate 1.921323 # Inst execution rate
-system.cpu.iew.wb_sent 1965930006 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1957490498 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1296385031 # num instructions producing a value
-system.cpu.iew.wb_consumers 2061135459 # num instructions consuming a value
+system.cpu.iew.exec_nop 130 # number of nop insts executed
+system.cpu.iew.exec_refs 764045166 # number of memory reference insts executed
+system.cpu.iew.exec_branches 238330381 # Number of branches executed
+system.cpu.iew.exec_stores 190143920 # Number of stores executed
+system.cpu.iew.exec_rate 1.921365 # Inst execution rate
+system.cpu.iew.wb_sent 1965882705 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1957438221 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1296419261 # num instructions producing a value
+system.cpu.iew.wb_consumers 2061223018 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.891711 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.628966 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.891716 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.628956 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 478367692 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 478537797 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 15217365 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 888709517 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.938849 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.727981 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 15221576 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 888731168 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.938802 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.727796 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 401294450 45.15% 45.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 192123349 21.62% 66.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 72572906 8.17% 74.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 35244916 3.97% 78.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 18969010 2.13% 81.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 30763331 3.46% 84.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 20056672 2.26% 86.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 11441847 1.29% 88.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106243036 11.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 401249220 45.15% 45.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 192209497 21.63% 66.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 72554391 8.16% 74.94% # Number of insts commited each cycle
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@@ -486,70 +471,70 @@ system.cpu.commit.branches 213462426 # Nu
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-system.cpu.dcache.overall_misses::total 17015519 # number of overall misses
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-system.cpu.dcache.ReadReq_miss_latency::total 322914399500 # number of ReadReq miss cycles
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-system.cpu.dcache.WriteReq_miss_latency::total 229337265001 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 552251664501 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 552251664501 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 552251664501 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 552251664501 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 500521549 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 500521549 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.LoadLockedReq_miss_latency::total 423500 # number of LoadLockedReq miss cycles
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+system.cpu.dcache.overall_miss_latency::total 552631798218 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 673107596 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 673107596 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 673107596 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 673107596 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022929 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.022929 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032095 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.032095 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025279 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025279 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025279 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025279 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28137.189345 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28137.189345 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41403.404204 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41403.404204 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32455.763736 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32455.763736 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 26327984 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1057907 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1182334 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 64553 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.267806 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 16.388193 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 673116163 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 673116163 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 673116163 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 673116163 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025281 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025281 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025281 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025281 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28139.570735 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28139.570735 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389561 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389561 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 141166.666667 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 141166.666667 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 32474.859624 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32474.859624 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 26343962 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 1054966 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1182360 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 64552 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.280830 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 16.342886 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3781250 # number of writebacks
-system.cpu.dcache.writebacks::total 3781250 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767955 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3767955 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645642 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3645642 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 3781695 # number of writebacks
+system.cpu.dcache.writebacks::total 3781695 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3769070 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 3769070 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645155 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3645155 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7413597 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7413597 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7413597 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7413597 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708472 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7708472 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893450 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1893450 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9601922 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9601922 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9601922 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9601922 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186178488500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 186178488500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508071510 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508071510 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269686560010 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 269686560010 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269686560010 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 269686560010 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24152.450512 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24152.450512 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44103.658143 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44103.658143 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data 7414225 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7414225 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7414225 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7414225 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709443 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7709443 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893551 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1893551 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9602994 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9602994 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9602994 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9602994 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186232562000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 186232562000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83589909224 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 83589909224 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269822471224 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 269822471224 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269822471224 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 269822471224 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.014266 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.014266 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24156.422455 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24156.422455 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.524876 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.524876 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------