diff options
Diffstat (limited to 'tests/long/se/60.bzip2')
4 files changed, 2566 insertions, 2480 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 5327d957c..a0ce19406 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.208729 # Number of seconds simulated -sim_ticks 1208728699500 # Number of ticks simulated -final_tick 1208728699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.208778 # Number of seconds simulated +sim_ticks 1208777694500 # Number of ticks simulated +final_tick 1208777694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 330067 # Simulator instruction rate (inst/s) -host_op_rate 330067 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 218444071 # Simulator tick rate (ticks/s) -host_mem_usage 300788 # Number of bytes of host memory used -host_seconds 5533.36 # Real time elapsed on the host +host_inst_rate 395749 # Simulator instruction rate (inst/s) +host_op_rate 395749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 261924296 # Simulator tick rate (ticks/s) +host_mem_usage 253640 # Number of bytes of host memory used +host_seconds 4614.99 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124969728 # Number of bytes read from this memory -system.physmem.bytes_read::total 125030976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65416576 # Number of bytes written to this memory -system.physmem.bytes_written::total 65416576 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 957 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1952652 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1953609 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1022134 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1022134 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 50671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 103389394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 103440066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 50671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 50671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54120148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54120148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54120148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 50671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 103389394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 157560214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1953609 # Number of read requests accepted -system.physmem.writeReqs 1022134 # Number of write requests accepted -system.physmem.readBursts 1953609 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1022134 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 124947712 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83264 # Total number of bytes read from write queue -system.physmem.bytesWritten 65415296 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125030976 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65416576 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1301 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124970112 # Number of bytes read from this memory +system.physmem.bytes_read::total 125031424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65416896 # Number of bytes written to this memory +system.physmem.bytes_written::total 65416896 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1952658 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1953616 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1022139 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1022139 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103385521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103436244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50722 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50722 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54118219 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54118219 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54118219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103385521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157554463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1953616 # Number of read requests accepted +system.physmem.writeReqs 1022139 # Number of write requests accepted +system.physmem.readBursts 1953616 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1022139 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 124948416 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83008 # Total number of bytes read from write queue +system.physmem.bytesWritten 65415616 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125031424 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65416896 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1297 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118310 # Per bank write bursts -system.physmem.perBankRdBursts::1 113529 # Per bank write bursts -system.physmem.perBankRdBursts::2 115745 # Per bank write bursts +system.physmem.perBankRdBursts::0 118316 # Per bank write bursts +system.physmem.perBankRdBursts::1 113525 # Per bank write bursts +system.physmem.perBankRdBursts::2 115740 # Per bank write bursts system.physmem.perBankRdBursts::3 117258 # Per bank write bursts -system.physmem.perBankRdBursts::4 117308 # Per bank write bursts -system.physmem.perBankRdBursts::5 117123 # Per bank write bursts -system.physmem.perBankRdBursts::6 119399 # Per bank write bursts -system.physmem.perBankRdBursts::7 124116 # Per bank write bursts -system.physmem.perBankRdBursts::8 126646 # Per bank write bursts -system.physmem.perBankRdBursts::9 129571 # Per bank write bursts -system.physmem.perBankRdBursts::10 128166 # Per bank write bursts -system.physmem.perBankRdBursts::11 129914 # Per bank write bursts -system.physmem.perBankRdBursts::12 125584 # Per bank write bursts -system.physmem.perBankRdBursts::13 124843 # Per bank write bursts -system.physmem.perBankRdBursts::14 122159 # Per bank write bursts -system.physmem.perBankRdBursts::15 122637 # Per bank write bursts -system.physmem.perBankWrBursts::0 61419 # Per bank write bursts +system.physmem.perBankRdBursts::4 117310 # Per bank write bursts +system.physmem.perBankRdBursts::5 117126 # Per bank write bursts +system.physmem.perBankRdBursts::6 119402 # Per bank write bursts +system.physmem.perBankRdBursts::7 124113 # Per bank write bursts +system.physmem.perBankRdBursts::8 126650 # Per bank write bursts +system.physmem.perBankRdBursts::9 129582 # Per bank write bursts +system.physmem.perBankRdBursts::10 128169 # Per bank write bursts +system.physmem.perBankRdBursts::11 129917 # Per bank write bursts +system.physmem.perBankRdBursts::12 125580 # Per bank write bursts +system.physmem.perBankRdBursts::13 124837 # Per bank write bursts +system.physmem.perBankRdBursts::14 122150 # Per bank write bursts +system.physmem.perBankRdBursts::15 122644 # Per bank write bursts +system.physmem.perBankWrBursts::0 61421 # Per bank write bursts system.physmem.perBankWrBursts::1 61661 # Per bank write bursts -system.physmem.perBankWrBursts::2 60723 # Per bank write bursts -system.physmem.perBankWrBursts::3 61396 # Per bank write bursts +system.physmem.perBankWrBursts::2 60724 # Per bank write bursts +system.physmem.perBankWrBursts::3 61398 # Per bank write bursts system.physmem.perBankWrBursts::4 61819 # Per bank write bursts -system.physmem.perBankWrBursts::5 63308 # Per bank write bursts +system.physmem.perBankWrBursts::5 63309 # Per bank write bursts system.physmem.perBankWrBursts::6 64356 # Per bank write bursts system.physmem.perBankWrBursts::7 65855 # Per bank write bursts -system.physmem.perBankWrBursts::8 65578 # Per bank write bursts -system.physmem.perBankWrBursts::9 66028 # Per bank write bursts -system.physmem.perBankWrBursts::10 65644 # Per bank write bursts -system.physmem.perBankWrBursts::11 65946 # Per bank write bursts -system.physmem.perBankWrBursts::12 64498 # Per bank write bursts -system.physmem.perBankWrBursts::13 64533 # Per bank write bursts -system.physmem.perBankWrBursts::14 64901 # Per bank write bursts -system.physmem.perBankWrBursts::15 64449 # Per bank write bursts +system.physmem.perBankWrBursts::8 65577 # Per bank write bursts +system.physmem.perBankWrBursts::9 66031 # Per bank write bursts +system.physmem.perBankWrBursts::10 65643 # Per bank write bursts +system.physmem.perBankWrBursts::11 65945 # Per bank write bursts +system.physmem.perBankWrBursts::12 64508 # Per bank write bursts +system.physmem.perBankWrBursts::13 64526 # Per bank write bursts +system.physmem.perBankWrBursts::14 64900 # Per bank write bursts +system.physmem.perBankWrBursts::15 64446 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1208728583000 # Total gap between requests +system.physmem.totGap 1208777578000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1953609 # Read request sizes (log2) +system.physmem.readPktSize::6 1953616 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1022134 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1829960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 122331 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1022139 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1830097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122205 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,30 +144,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see @@ -193,31 +193,31 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1831742 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.922688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.125561 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.468112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1453729 79.36% 79.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 261245 14.26% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48901 2.67% 96.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20697 1.13% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13090 0.71% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7260 0.40% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5482 0.30% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4525 0.25% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16813 0.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1831742 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59619 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.744729 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 150.866534 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 59458 99.73% 99.73% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1831457 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.940817 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.136003 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.529919 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1452947 79.33% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261995 14.31% 93.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48664 2.66% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20593 1.12% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13175 0.72% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7238 0.40% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5438 0.30% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4580 0.25% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16827 0.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1831457 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59614 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.747643 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 146.947369 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 59453 99.73% 99.73% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-1023 115 0.19% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 8 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 9 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 9 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 9 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-3071 3 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 3 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes @@ -225,30 +225,30 @@ system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # R system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10752-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59619 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59619 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.144098 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.107874 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.119193 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27514 46.15% 46.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1196 2.01% 48.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26405 44.29% 92.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3955 6.63% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 448 0.75% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 78 0.13% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 59614 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.145620 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.109391 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.119268 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27453 46.05% 46.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1268 2.13% 48.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26337 44.18% 92.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4007 6.72% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 455 0.76% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 71 0.12% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 15 0.03% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59619 # Writes before turning the bus around for reads -system.physmem.totQLat 36502723500 # Total ticks spent queuing -system.physmem.totMemAccLat 73108498500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9761540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18697.22 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 59614 # Writes before turning the bus around for reads +system.physmem.totQLat 36537628750 # Total ticks spent queuing +system.physmem.totMemAccLat 73143610000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9761595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18714.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37447.22 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37464.99 # Average memory access latency per DRAM burst system.physmem.avgRdBW 103.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 54.12 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 103.44 # Average system read bandwidth in MiByte/s @@ -258,71 +258,75 @@ system.physmem.busUtil 1.23 # Da system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.64 # Average write queue length when enqueuing -system.physmem.readRowHits 723641 # Number of row buffer hits during reads -system.physmem.writeRowHits 419030 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing +system.physmem.readRowHits 723773 # Number of row buffer hits during reads +system.physmem.writeRowHits 419204 # Number of row buffer hits during writes system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.00 # Row buffer hit rate for writes -system.physmem.avgGap 406193.88 # Average gap between requests -system.physmem.pageHitRate 38.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6715147320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3664018875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7353699600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3243479760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 78947837280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 414818688735 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 361357239750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 876100111320 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.815145 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 598389652500 # Time in different power states -system.physmem_0.memoryStateTime::REF 40361880000 # Time in different power states +system.physmem.writeRowHitRate 41.01 # Row buffer hit rate for writes +system.physmem.avgGap 406208.70 # Average gap between requests +system.physmem.pageHitRate 38.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6714376200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3663598125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7353738600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3243518640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 78951397200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 415074736440 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361165338750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 876166703955 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.837554 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 598070170000 # Time in different power states +system.physmem_0.memoryStateTime::REF 40363700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 569973346500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 570342873000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7132791960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3891900375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7873632000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3379818960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 78947837280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 426678504030 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 350953893000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 878858377605 # Total energy per rank (pJ) -system.physmem_1.averagePower 727.097114 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 581002634000 # Time in different power states -system.physmem_1.memoryStateTime::REF 40361880000 # Time in different power states +system.physmem_1.actEnergy 7131423600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3891153750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7874224800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3379812480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 78951397200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 426560774805 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 351089866500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 878878653135 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.081103 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 581228871000 # Time in different power states +system.physmem_1.memoryStateTime::REF 40363700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 587357637250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 587184084000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 246098302 # Number of BP lookups -system.cpu.branchPred.condPredicted 186353272 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15586995 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 167674122 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165197435 # Number of BTB hits +system.cpu.branchPred.lookups 246097965 # Number of BP lookups +system.cpu.branchPred.condPredicted 186356162 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15588061 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167640085 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165196337 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.522916 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18413853 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104375 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.542265 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18413332 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104391 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 297 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 67 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 230 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 98 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452860961 # DTB read hits -system.cpu.dtb.read_misses 4979889 # DTB read misses +system.cpu.dtb.read_hits 452860657 # DTB read hits +system.cpu.dtb.read_misses 4979867 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457840850 # DTB read accesses -system.cpu.dtb.write_hits 161378751 # DTB write hits -system.cpu.dtb.write_misses 1709377 # DTB write misses +system.cpu.dtb.read_accesses 457840524 # DTB read accesses +system.cpu.dtb.write_hits 161378231 # DTB write hits +system.cpu.dtb.write_misses 1709431 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163088128 # DTB write accesses -system.cpu.dtb.data_hits 614239712 # DTB hits -system.cpu.dtb.data_misses 6689266 # DTB misses +system.cpu.dtb.write_accesses 163087662 # DTB write accesses +system.cpu.dtb.data_hits 614238888 # DTB hits +system.cpu.dtb.data_misses 6689298 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620928978 # DTB accesses -system.cpu.itb.fetch_hits 597989879 # ITB hits +system.cpu.dtb.data_accesses 620928186 # DTB accesses +system.cpu.itb.fetch_hits 597989612 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 597989898 # ITB accesses +system.cpu.itb.fetch_accesses 597989631 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -336,82 +340,117 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2417457399 # number of cpu cycles simulated +system.cpu.numCycles 2417555389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 51810559 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 51811935 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.323634 # CPI: cycles per instruction -system.cpu.ipc 0.755496 # IPC: instructions per cycle -system.cpu.tickCycles 2075240271 # Number of cycles that the object actually ticked -system.cpu.idleCycles 342217128 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9121937 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.725777 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601539424 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126033 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.914667 # Average number of references to valid blocks. +system.cpu.cpi 1.323688 # CPI: cycles per instruction +system.cpu.ipc 0.755465 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction +system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction +system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 66.45% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 805244 0.04% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 13 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 100 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatMult 11 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 24 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::MemRead 449492741 24.61% 91.11% # Class of committed instruction +system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 1826378509 # Class of committed instruction +system.cpu.tickCycles 2075251932 # Number of cycles that the object actually ticked +system.cpu.idleCycles 342303457 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121974 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.726355 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601538856 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126070 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.914337 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 16821281500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.725777 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.726355 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.996271 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1547 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2403 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1562 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2407 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231276891 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231276891 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 443057425 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443057425 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158481999 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158481999 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 601539424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601539424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 601539424 # number of overall hits -system.cpu.dcache.overall_hits::total 601539424 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7289502 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289502 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2246503 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2246503 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9536005 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9536005 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9536005 # number of overall misses -system.cpu.dcache.overall_misses::total 9536005 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 185435901500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 185435901500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108411798000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108411798000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 293847699500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 293847699500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 293847699500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 293847699500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 450346927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450346927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231275880 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231275880 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 443056865 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443056865 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158481991 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158481991 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 601538856 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601538856 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 601538856 # number of overall hits +system.cpu.dcache.overall_hits::total 601538856 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7289538 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289538 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2246511 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2246511 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9536049 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9536049 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9536049 # number of overall misses +system.cpu.dcache.overall_misses::total 9536049 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 185480529000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 185480529000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108417025500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108417025500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 293897554500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 293897554500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 293897554500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 293897554500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 450346403 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450346403 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 611075429 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611075429 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 611075429 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611075429 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016186 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016186 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 611074905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611074905 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611074905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611074905 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016187 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013977 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013977 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.015605 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015605 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015605 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015605 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25438.761317 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25438.761317 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48258.025028 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48258.025028 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30814.549646 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30814.549646 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30814.549646 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30814.549646 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25444.757816 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25444.757816 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48260.180119 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48260.180119 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30819.635522 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30819.635522 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30819.635522 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30819.635522 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,32 +459,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3686592 # number of writebacks -system.cpu.dcache.writebacks::total 3686592 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50797 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50797 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359175 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 359175 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 409972 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 409972 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 409972 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 409972 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238705 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238705 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887328 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887328 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126033 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126033 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126033 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126033 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176973816500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 176973816500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83260117500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83260117500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260233934000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 260233934000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260233934000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 260233934000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3686603 # number of writebacks +system.cpu.dcache.writebacks::total 3686603 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50808 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50808 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359171 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 359171 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 409979 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 409979 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 409979 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 409979 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238730 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238730 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887340 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887340 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126070 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126070 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126070 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126070 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 177011068000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 177011068000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83258719000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83258719000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260269787000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 260269787000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260269787000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 260269787000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016074 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016074 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses @@ -454,66 +493,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014934 system.cpu.dcache.demand_mshr_miss_rate::total 0.014934 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014934 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24448.270305 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24448.270305 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44115.340577 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44115.340577 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28515.559170 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28515.559170 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28515.559170 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28515.559170 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24453.332007 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24453.332007 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44114.319095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44114.319095 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 749.290154 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 597988922 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 957 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 624857.807732 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 750.173547 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 597988654 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 624205.275574 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 749.290154 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.365864 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.365864 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 750.173547 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366296 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366296 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1195980715 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1195980715 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 597988922 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 597988922 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 597988922 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 597988922 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 597988922 # number of overall hits -system.cpu.icache.overall_hits::total 597988922 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses -system.cpu.icache.overall_misses::total 957 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 76621000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 76621000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 76621000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 76621000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 76621000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 76621000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 597989879 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 597989879 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 597989879 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 597989879 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 597989879 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 597989879 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1195980182 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1195980182 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 597988654 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 597988654 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 597988654 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 597988654 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 597988654 # number of overall hits +system.cpu.icache.overall_hits::total 597988654 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses +system.cpu.icache.overall_misses::total 958 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 76338000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 76338000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 76338000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 76338000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 76338000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 76338000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 597989612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 597989612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 597989612 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 597989612 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 597989612 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 597989612 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80063.740857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80063.740857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80063.740857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80063.740857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80063.740857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80063.740857 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79684.759916 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 79684.759916 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 79684.759916 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 79684.759916 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 79684.759916 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 79684.759916 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,107 +563,107 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 3 # number of writebacks system.cpu.icache.writebacks::total 3 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 957 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 957 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 957 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75664000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75664000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75664000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75664000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75664000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75664000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75380000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75380000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75380000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75380000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75380000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75380000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79063.740857 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79063.740857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79063.740857 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79063.740857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79063.740857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79063.740857 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78684.759916 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78684.759916 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1920885 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30765.167230 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14409636 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1950689 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.386947 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1920891 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30765.315888 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14409692 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1950696 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.386949 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 89219766000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14798.522218 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.781155 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15923.863857 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.451615 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001306 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.485958 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.938878 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29804 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12864 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 14798.392410 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.817395 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15924.106083 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.451611 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001307 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.485965 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.938883 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29805 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1217 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12865 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15532 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149829457 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149829457 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 3686592 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3686592 # number of WritebackDirty hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 149830076 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149830076 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3686603 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3686603 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1106819 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1106819 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6066562 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6066562 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7173381 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7173381 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7173381 # number of overall hits -system.cpu.l2cache.overall_hits::total 7173381 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 780509 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 780509 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 957 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 957 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1172143 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1172143 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 957 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1952652 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1953609 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 957 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1952652 # number of overall misses -system.cpu.l2cache.overall_misses::total 1953609 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68736259500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 68736259500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 74227500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 74227500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102389221500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 102389221500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 74227500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 171125481000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 171199708500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 74227500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 171125481000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 171199708500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3686592 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3686592 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 1106830 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1106830 # number of ReadExReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6066582 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6066582 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 7173412 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7173412 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7173412 # number of overall hits +system.cpu.l2cache.overall_hits::total 7173412 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 780510 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 780510 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 958 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 958 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1172148 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1172148 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 958 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1952658 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1953616 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 958 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1952658 # number of overall misses +system.cpu.l2cache.overall_misses::total 1953616 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68734828000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 68734828000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 73941000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 73941000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102426227000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 102426227000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 73941000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 171161055000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 171234996000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 73941000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 171161055000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 171234996000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3686603 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3686603 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887328 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1887328 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 957 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 957 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7238705 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7238705 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 957 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9126033 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9126990 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 957 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9126033 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9126990 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413552 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.413552 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887340 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1887340 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 958 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 958 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7238730 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7238730 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 958 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9126070 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9127028 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 958 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9126070 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9127028 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413550 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413550 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161927 # miss rate for ReadSharedReq accesses @@ -635,18 +674,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.214047 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.213965 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214047 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88065.940944 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88065.940944 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77562.695925 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77562.695925 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87352.158824 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87352.158824 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77562.695925 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87637.469964 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87632.534709 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77562.695925 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87637.469964 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87632.534709 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88063.994055 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88063.994055 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77182.672234 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77182.672234 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87383.356880 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87383.356880 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77182.672234 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87655.418921 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87650.283372 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77182.672234 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87655.418921 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87650.283372 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,38 +694,38 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1022134 # number of writebacks -system.cpu.l2cache.writebacks::total 1022134 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1022139 # number of writebacks +system.cpu.l2cache.writebacks::total 1022139 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780509 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 780509 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 957 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 957 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1172143 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1172143 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1952652 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1953609 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1952652 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1953609 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60931169500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60931169500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64657500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64657500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90667791500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90667791500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64657500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151598961000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 151663618500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64657500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151598961000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 151663618500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780510 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 780510 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 958 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 958 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1172148 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1172148 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1952658 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1953616 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1952658 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1953616 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60929728000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60929728000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64361000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64361000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90704747000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90704747000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64361000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151634475000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 151698836000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64361000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151634475000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 151698836000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413552 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413552 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413550 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413550 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161927 # mshr miss rate for ReadSharedReq accesses @@ -697,81 +736,81 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214047 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214047 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78065.940944 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78065.940944 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67562.695925 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67562.695925 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77352.158824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77352.158824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67562.695925 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77637.469964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77632.534709 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67562.695925 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77637.469964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77632.534709 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78063.994055 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78063.994055 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67182.672234 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67182.672234 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77383.356880 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77383.356880 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67182.672234 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77655.418921 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77650.283372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67182.672234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77655.418921 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77650.283372 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 18248930 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121940 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 18249005 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121977 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1268 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7239662 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4708726 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4708742 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6334096 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 957 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238705 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1917 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374003 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27375920 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820008000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820069440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1920885 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 11047875 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::CleanEvict 6334123 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238730 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374114 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27376033 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820011072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820072576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1920891 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11047919 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.010713 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11046607 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11046651 99.99% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1268 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11047875 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12811060000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11047919 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12811108500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1435500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1437000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13689049500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13689105000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1173100 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1022134 # Transaction distribution -system.membus.trans_dist::CleanEvict 897725 # Transaction distribution -system.membus.trans_dist::ReadExReq 780509 # Transaction distribution -system.membus.trans_dist::ReadExResp 780509 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1173100 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827077 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5827077 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190447552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190447552 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1173106 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1022139 # Transaction distribution +system.membus.trans_dist::CleanEvict 897726 # Transaction distribution +system.membus.trans_dist::ReadExReq 780510 # Transaction distribution +system.membus.trans_dist::ReadExResp 780510 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1173106 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827097 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5827097 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190448320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190448320 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3873468 # Request fanout histogram +system.membus.snoop_fanout::samples 3873481 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3873468 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3873481 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3873468 # Request fanout histogram -system.membus.reqLayer0.occupancy 8428126500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3873481 # Request fanout histogram +system.membus.reqLayer0.occupancy 8428417500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 10685578000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10685410500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index f994e016c..f0b14c5aa 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.669525 # Number of seconds simulated -sim_ticks 669525393000 # Number of ticks simulated -final_tick 669525393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.669588 # Number of seconds simulated +sim_ticks 669587683000 # Number of ticks simulated +final_tick 669587683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161577 # Simulator instruction rate (inst/s) -host_op_rate 161577 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62314021 # Simulator tick rate (ticks/s) -host_mem_usage 300544 # Number of bytes of host memory used -host_seconds 10744.38 # Real time elapsed on the host +host_inst_rate 206275 # Simulator instruction rate (inst/s) +host_op_rate 206275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79559671 # Simulator tick rate (ticks/s) +host_mem_usage 254664 # Number of bytes of host memory used +host_seconds 8416.17 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125490432 # Number of bytes read from this memory -system.physmem.bytes_read::total 125551424 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65555904 # Number of bytes written to this memory -system.physmem.bytes_written::total 65555904 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960788 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961741 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1024311 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1024311 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 91097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 187431923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 187523021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 97913992 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 97913992 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 97913992 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 187431923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 285437013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961741 # Number of read requests accepted -system.physmem.writeReqs 1024311 # Number of write requests accepted -system.physmem.readBursts 1961741 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1024311 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125468352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83072 # Total number of bytes read from write queue -system.physmem.bytesWritten 65554688 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125551424 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65555904 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1298 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125489536 # Number of bytes read from this memory +system.physmem.bytes_read::total 125550272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65555456 # Number of bytes written to this memory +system.physmem.bytes_written::total 65555456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 949 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960774 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961723 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1024304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1024304 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 90707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 187413149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 187503855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97904214 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97904214 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97904214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 187413149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 285408070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961723 # Number of read requests accepted +system.physmem.writeReqs 1024304 # Number of write requests accepted +system.physmem.readBursts 1961723 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1024304 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125465280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 84992 # Total number of bytes read from write queue +system.physmem.bytesWritten 65553920 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125550272 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65555456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1328 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118677 # Per bank write bursts -system.physmem.perBankRdBursts::1 113900 # Per bank write bursts -system.physmem.perBankRdBursts::2 116118 # Per bank write bursts -system.physmem.perBankRdBursts::3 117645 # Per bank write bursts -system.physmem.perBankRdBursts::4 117762 # Per bank write bursts -system.physmem.perBankRdBursts::5 117513 # Per bank write bursts -system.physmem.perBankRdBursts::6 119856 # Per bank write bursts -system.physmem.perBankRdBursts::7 124646 # Per bank write bursts -system.physmem.perBankRdBursts::8 127338 # Per bank write bursts -system.physmem.perBankRdBursts::9 130111 # Per bank write bursts -system.physmem.perBankRdBursts::10 128791 # Per bank write bursts -system.physmem.perBankRdBursts::11 130502 # Per bank write bursts -system.physmem.perBankRdBursts::12 126296 # Per bank write bursts -system.physmem.perBankRdBursts::13 125424 # Per bank write bursts -system.physmem.perBankRdBursts::14 122633 # Per bank write bursts -system.physmem.perBankRdBursts::15 123231 # Per bank write bursts -system.physmem.perBankWrBursts::0 61509 # Per bank write bursts -system.physmem.perBankWrBursts::1 61765 # Per bank write bursts -system.physmem.perBankWrBursts::2 60825 # Per bank write bursts -system.physmem.perBankWrBursts::3 61513 # Per bank write bursts -system.physmem.perBankWrBursts::4 61969 # Per bank write bursts -system.physmem.perBankWrBursts::5 63433 # Per bank write bursts -system.physmem.perBankWrBursts::6 64481 # Per bank write bursts -system.physmem.perBankWrBursts::7 65997 # Per bank write bursts -system.physmem.perBankWrBursts::8 65770 # Per bank write bursts -system.physmem.perBankWrBursts::9 66158 # Per bank write bursts -system.physmem.perBankWrBursts::10 65809 # Per bank write bursts -system.physmem.perBankWrBursts::11 66082 # Per bank write bursts -system.physmem.perBankWrBursts::12 64703 # Per bank write bursts -system.physmem.perBankWrBursts::13 64664 # Per bank write bursts -system.physmem.perBankWrBursts::14 65021 # Per bank write bursts -system.physmem.perBankWrBursts::15 64593 # Per bank write bursts +system.physmem.perBankRdBursts::0 118674 # Per bank write bursts +system.physmem.perBankRdBursts::1 113905 # Per bank write bursts +system.physmem.perBankRdBursts::2 116110 # Per bank write bursts +system.physmem.perBankRdBursts::3 117640 # Per bank write bursts +system.physmem.perBankRdBursts::4 117758 # Per bank write bursts +system.physmem.perBankRdBursts::5 117504 # Per bank write bursts +system.physmem.perBankRdBursts::6 119855 # Per bank write bursts +system.physmem.perBankRdBursts::7 124644 # Per bank write bursts +system.physmem.perBankRdBursts::8 127350 # Per bank write bursts +system.physmem.perBankRdBursts::9 130115 # Per bank write bursts +system.physmem.perBankRdBursts::10 128783 # Per bank write bursts +system.physmem.perBankRdBursts::11 130505 # Per bank write bursts +system.physmem.perBankRdBursts::12 126282 # Per bank write bursts +system.physmem.perBankRdBursts::13 125429 # Per bank write bursts +system.physmem.perBankRdBursts::14 122618 # Per bank write bursts +system.physmem.perBankRdBursts::15 123223 # Per bank write bursts +system.physmem.perBankWrBursts::0 61508 # Per bank write bursts +system.physmem.perBankWrBursts::1 61766 # Per bank write bursts +system.physmem.perBankWrBursts::2 60822 # Per bank write bursts +system.physmem.perBankWrBursts::3 61512 # Per bank write bursts +system.physmem.perBankWrBursts::4 61965 # Per bank write bursts +system.physmem.perBankWrBursts::5 63432 # Per bank write bursts +system.physmem.perBankWrBursts::6 64483 # Per bank write bursts +system.physmem.perBankWrBursts::7 65996 # Per bank write bursts +system.physmem.perBankWrBursts::8 65772 # Per bank write bursts +system.physmem.perBankWrBursts::9 66160 # Per bank write bursts +system.physmem.perBankWrBursts::10 65806 # Per bank write bursts +system.physmem.perBankWrBursts::11 66084 # Per bank write bursts +system.physmem.perBankWrBursts::12 64700 # Per bank write bursts +system.physmem.perBankWrBursts::13 64663 # Per bank write bursts +system.physmem.perBankWrBursts::14 65022 # Per bank write bursts +system.physmem.perBankWrBursts::15 64589 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 669525297500 # Total gap between requests +system.physmem.totGap 669587587500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961741 # Read request sizes (log2) +system.physmem.readPktSize::6 1961723 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1024311 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1618506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 241044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1024304 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1618543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 241060 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 63632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 65011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 26257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 63644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 65120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 191 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,55 +193,58 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1769975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.923423 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.935475 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 137.553027 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1375598 77.72% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 270762 15.30% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53515 3.02% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21283 1.20% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12968 0.73% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6460 0.36% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4828 0.27% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3885 0.22% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20676 1.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1769975 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60095 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.621932 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 151.728866 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 59931 99.73% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 120 0.20% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 12 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 4 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 5 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 5 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 4 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1769781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.933083 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.950192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 137.486388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1375005 77.69% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 271238 15.33% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53445 3.02% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21262 1.20% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12891 0.73% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6578 0.37% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4909 0.28% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3869 0.22% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20584 1.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1769781 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60104 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.614784 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 150.080179 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 59932 99.71% 99.71% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 127 0.21% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 7 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 3 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 1 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-9727 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60095 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60095 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.044546 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.002519 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.231700 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 31758 52.85% 52.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1379 2.29% 55.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 21272 35.40% 90.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4591 7.64% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 816 1.36% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 185 0.31% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 43 0.07% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 20 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::14848-15359 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60104 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60104 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.041794 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.999820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.231211 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31815 52.93% 52.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1444 2.40% 55.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 21085 35.08% 90.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4727 7.86% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 762 1.27% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 188 0.31% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 35 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 13 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32 3 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::33 2 0.00% 99.98% # Writes before turning the bus around for reads @@ -254,87 +257,91 @@ system.physmem.wrPerTurnAround::39 1 0.00% 100.00% # Wr system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60095 # Writes before turning the bus around for reads -system.physmem.totQLat 40550197000 # Total ticks spent queuing -system.physmem.totMemAccLat 77308503250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9802215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20684.20 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 60104 # Writes before turning the bus around for reads +system.physmem.totQLat 40549512750 # Total ticks spent queuing +system.physmem.totMemAccLat 77306919000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9801975000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20684.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39434.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 187.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 97.91 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 187.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 97.91 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39434.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 187.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 97.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 187.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 97.90 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.23 # Data bus utilization in percentage system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing -system.physmem.readRowHits 792754 # Number of row buffer hits during reads -system.physmem.writeRowHits 422001 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.20 # Row buffer hit rate for writes -system.physmem.avgGap 224217.56 # Average gap between requests +system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing +system.physmem.readRowHits 792652 # Number of row buffer hits during reads +system.physmem.writeRowHits 422237 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.22 # Row buffer hit rate for writes +system.physmem.avgGap 224240.30 # Average gap between requests system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6484552200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3538198125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7379689200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3249668160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 43730057280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 304192019700 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134879490000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 503453674665 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.957257 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 222404009750 # Time in different power states -system.physmem_0.memoryStateTime::REF 22356880000 # Time in different power states +system.physmem_0.actEnergy 6484506840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3538173375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7379478600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3249616320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43734125760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 304395031755 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134738783250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 503519715900 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.985934 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 222173701250 # Time in different power states +system.physmem_0.memoryStateTime::REF 22358960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 424763715750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 425054234250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6896443680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3762940500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7911594600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3387744000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 43730057280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 311181502770 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 128748364500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 505618647330 # Total energy per rank (pJ) -system.physmem_1.averagePower 755.190855 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 212167441250 # Time in different power states -system.physmem_1.memoryStateTime::REF 22356880000 # Time in different power states +system.physmem_1.actEnergy 6895022400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3762165000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7911430800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3387718080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43734125760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 311120339490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 128839390500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 505650192030 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.167712 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 212315780250 # Time in different power states +system.physmem_1.memoryStateTime::REF 22358960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 435000017500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 434911888500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 409350195 # Number of BP lookups -system.cpu.branchPred.condPredicted 318164532 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15963584 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 282308187 # Number of BTB lookups -system.cpu.branchPred.BTBHits 278578841 # Number of BTB hits +system.cpu.branchPred.lookups 409349783 # Number of BP lookups +system.cpu.branchPred.condPredicted 318159413 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15962959 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282310323 # Number of BTB lookups +system.cpu.branchPred.BTBHits 278567233 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.678981 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26172152 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.674122 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26172089 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 47 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 12632 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1004 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 11628 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 76 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 644938332 # DTB read hits -system.cpu.dtb.read_misses 12159455 # DTB read misses +system.cpu.dtb.read_hits 644930756 # DTB read hits +system.cpu.dtb.read_misses 12159240 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 657097787 # DTB read accesses -system.cpu.dtb.write_hits 218091822 # DTB write hits -system.cpu.dtb.write_misses 7511788 # DTB write misses +system.cpu.dtb.read_accesses 657089996 # DTB read accesses +system.cpu.dtb.write_hits 218090963 # DTB write hits +system.cpu.dtb.write_misses 7511655 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225603610 # DTB write accesses -system.cpu.dtb.data_hits 863030154 # DTB hits -system.cpu.dtb.data_misses 19671243 # DTB misses +system.cpu.dtb.write_accesses 225602618 # DTB write accesses +system.cpu.dtb.data_hits 863021719 # DTB hits +system.cpu.dtb.data_misses 19670895 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 882701397 # DTB accesses -system.cpu.itb.fetch_hits 420624983 # ITB hits +system.cpu.dtb.data_accesses 882692614 # DTB accesses +system.cpu.itb.fetch_hits 420612911 # ITB hits system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 420625020 # ITB accesses +system.cpu.itb.fetch_accesses 420612948 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -348,138 +355,138 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1339050787 # number of cpu cycles simulated +system.cpu.numCycles 1339175367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 431760433 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3409990757 # Number of instructions fetch has processed -system.cpu.fetch.Branches 409350195 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 304750993 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 884524854 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45382362 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 431750962 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3410040939 # Number of instructions fetch has processed +system.cpu.fetch.Branches 409349783 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 304740326 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 884658040 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45380368 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1660 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 420624983 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8290664 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1338978167 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.546711 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.150697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 420612911 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8286314 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1339100880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.546515 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.150664 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 713970324 53.32% 53.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47658259 3.56% 56.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24222568 1.81% 58.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45103345 3.37% 62.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142790906 10.66% 72.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 65943786 4.92% 77.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43594409 3.26% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29428241 2.20% 83.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226266329 16.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 714090223 53.33% 53.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47658538 3.56% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24213511 1.81% 58.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45104764 3.37% 62.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142790793 10.66% 72.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 65948937 4.92% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43596223 3.26% 80.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29427236 2.20% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226270655 16.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1338978167 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305702 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.546573 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 353776569 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 403484138 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 524228681 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34798314 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22690465 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62024721 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 1339100880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305673 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.546374 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 353769972 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 403619551 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 524217734 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34804152 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22689471 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62026814 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3256106209 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2093 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22690465 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 372012141 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 212467548 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7342 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 537162613 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 194638058 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3173768927 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1816422 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20455726 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 148599653 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30860374 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2371827952 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4117690277 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4117553850 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 136426 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 3256105292 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2070 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22689471 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 372006695 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 212568628 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7422 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 537155412 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 194673252 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3173749438 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1811256 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20472342 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 148588016 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30888023 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2371822708 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4117670877 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4117534302 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 136574 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 995624989 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 146 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 145 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99592668 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 717246268 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272455740 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90411000 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58626283 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2884178650 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 125 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2620049271 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1544769 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1148134993 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 502709027 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 96 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1338978167 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.956753 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.148253 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 995619745 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 151 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 149 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99632674 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 717246724 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272457234 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90451892 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58631522 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2884174304 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 130 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2620036143 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1544818 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1148130652 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 502718906 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 101 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1339100880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.956564 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.148176 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 535496202 39.99% 39.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169647302 12.67% 52.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 157966093 11.80% 64.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149142376 11.14% 75.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126023638 9.41% 85.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84181895 6.29% 91.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68010869 5.08% 96.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34104922 2.55% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14404870 1.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 535608565 40.00% 40.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169639715 12.67% 52.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 157955882 11.80% 64.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149207498 11.14% 75.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126008488 9.41% 85.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84159132 6.28% 91.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68020206 5.08% 96.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34099830 2.55% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14401564 1.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1338978167 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1339100880 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13158801 35.84% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18966749 51.66% 87.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4591786 12.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13158046 35.85% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18960543 51.65% 87.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4589272 12.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1716928227 65.53% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1716921702 65.53% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 112 0.00% 65.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896664 0.03% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896133 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 22 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued @@ -502,82 +509,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 671542182 25.63% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230681845 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 671538399 25.63% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230679552 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2620049271 # Type of FU issued -system.cpu.iq.rate 1.956647 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36717336 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014014 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6615397697 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4031207578 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2518612422 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1941117 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1249905 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 887144 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2655798760 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 967847 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69398293 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2620036143 # Type of FU issued +system.cpu.iq.rate 1.956455 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36707861 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014010 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6615486651 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4031199558 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2518604332 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1939194 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1248781 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 886609 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2655777108 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 966896 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69396468 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 272650605 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 374228 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 146038 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 111727238 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 272651061 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 372885 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 145563 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 111728732 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 239 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6310160 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 286 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6308614 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22690465 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149836338 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 21229362 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3035183152 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6595413 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 717246268 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272455740 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 125 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 801803 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 20684202 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 146038 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10633994 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8701055 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19335049 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2574897906 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 657097795 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45151365 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22689471 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149827283 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 21278630 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3035173177 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6594541 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 717246724 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272457234 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 130 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 801857 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 20733670 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 145563 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10633550 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8701156 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19334706 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2574881369 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 657090005 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45154774 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151004377 # number of nop insts executed -system.cpu.iew.exec_refs 882701473 # number of memory reference insts executed -system.cpu.iew.exec_branches 315482828 # Number of branches executed -system.cpu.iew.exec_stores 225603678 # Number of stores executed -system.cpu.iew.exec_rate 1.922928 # Inst execution rate -system.cpu.iew.wb_sent 2549323154 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2519499566 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1487497634 # num instructions producing a value -system.cpu.iew.wb_consumers 1918379503 # num instructions consuming a value -system.cpu.iew.wb_rate 1.881556 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775393 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 998640819 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 150998743 # number of nop insts executed +system.cpu.iew.exec_refs 882692691 # number of memory reference insts executed +system.cpu.iew.exec_branches 315484112 # Number of branches executed +system.cpu.iew.exec_stores 225602686 # Number of stores executed +system.cpu.iew.exec_rate 1.922737 # Inst execution rate +system.cpu.iew.wb_sent 2549313271 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2519490941 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1487485532 # num instructions producing a value +system.cpu.iew.wb_consumers 1918368513 # num instructions consuming a value +system.cpu.iew.wb_rate 1.881375 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775391 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 998632615 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15962868 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1200994355 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.515228 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.548533 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15962246 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1201120469 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.515069 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.548329 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 712309125 59.31% 59.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159609736 13.29% 72.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79494019 6.62% 79.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52028691 4.33% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28473987 2.37% 85.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19488340 1.62% 87.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19957354 1.66% 89.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23050317 1.92% 91.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106582786 8.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 712379439 59.31% 59.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159650119 13.29% 72.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79517213 6.62% 79.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52024602 4.33% 83.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28479101 2.37% 85.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19489140 1.62% 87.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19970906 1.66% 89.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23045357 1.92% 91.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106564592 8.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1200994355 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1201120469 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -623,265 +630,265 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106582786 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3827053314 # The number of ROB reads -system.cpu.rob.rob_writes 5774960362 # The number of ROB writes -system.cpu.timesIdled 711 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 72620 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 106564592 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3827189418 # The number of ROB reads +system.cpu.rob.rob_writes 5774940551 # The number of ROB writes +system.cpu.timesIdled 705 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 74487 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.771323 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.771323 # CPI: Total CPI of All Threads -system.cpu.ipc 1.296473 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.296473 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3463595596 # number of integer regfile reads -system.cpu.int_regfile_writes 2019348323 # number of integer regfile writes -system.cpu.fp_regfile_reads 39740 # number of floating regfile reads -system.cpu.fp_regfile_writes 588 # number of floating regfile writes +system.cpu.cpi 0.771395 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.771395 # CPI: Total CPI of All Threads +system.cpu.ipc 1.296353 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.296353 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3463571137 # number of integer regfile reads +system.cpu.int_regfile_writes 2019338951 # number of integer regfile writes +system.cpu.fp_regfile_reads 39668 # number of floating regfile reads +system.cpu.fp_regfile_writes 612 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9207181 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.441061 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 712353360 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9211277 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.334919 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9207202 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.451175 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 712346624 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9211298 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.334011 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5127954500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.441061 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997910 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997910 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.451175 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997913 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997913 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 698 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2969 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 699 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2968 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1470163219 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1470163219 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 556855010 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 556855010 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155498347 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155498347 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 712353357 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 712353357 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 712353357 # number of overall hits -system.cpu.dcache.overall_hits::total 712353357 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12892455 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12892455 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5230155 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5230155 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1470154674 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1470154674 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 556848448 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 556848448 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155498172 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155498172 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 712346620 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 712346620 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 712346620 # number of overall hits +system.cpu.dcache.overall_hits::total 712346620 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12894733 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12894733 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5230330 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5230330 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 18122610 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 18122610 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 18122610 # number of overall misses -system.cpu.dcache.overall_misses::total 18122610 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 411787652500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 411787652500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 315044398573 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 315044398573 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 72500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 726832051073 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 726832051073 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 726832051073 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 726832051073 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 569747465 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 569747465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 18125063 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 18125063 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 18125063 # number of overall misses +system.cpu.dcache.overall_misses::total 18125063 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 412093066500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 412093066500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 315139193599 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 315139193599 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 85500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 727232260099 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 727232260099 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 727232260099 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 727232260099 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 569743181 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 569743181 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 730475967 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 730475967 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 730475967 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 730475967 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022628 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022628 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032540 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032540 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024809 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024809 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024809 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024809 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31940.204755 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31940.204755 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60236.149516 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60236.149516 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40106.367188 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40106.367188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40106.367188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40106.367188 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15689743 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9578184 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1104687 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 68028 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.202886 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 140.797672 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 730471683 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 730471683 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 730471683 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 730471683 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022633 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022633 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032541 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032541 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024813 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024813 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024813 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024813 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31958.247332 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31958.247332 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60252.258194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60252.258194 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40123.019716 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40123.019716 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40123.019716 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40123.019716 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15672953 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9573691 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1104455 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 68040 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.190667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 140.706805 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3727717 # number of writebacks -system.cpu.dcache.writebacks::total 3727717 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5560371 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5560371 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3350963 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3350963 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8911334 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8911334 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8911334 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8911334 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332084 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7332084 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879192 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879192 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3727750 # number of writebacks +system.cpu.dcache.writebacks::total 3727750 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5562625 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5562625 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3351141 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3351141 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8913766 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8913766 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8913766 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8913766 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332108 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7332108 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879189 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879189 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9211276 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9211276 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9211276 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9211276 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182956640000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 182956640000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84332021587 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84332021587 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 71500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 71500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267288661587 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 267288661587 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267288661587 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 267288661587 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9211297 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9211297 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9211297 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9211297 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182971511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 182971511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84313777567 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84313777567 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267285289067 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 267285289067 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267285289067 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 267285289067 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24952.883791 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24952.883791 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.745743 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.745743 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 71500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 71500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.549967 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.549967 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.549967 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.549967 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24954.830384 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24954.830384 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44867.108932 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44867.108932 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 755.122971 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 420623501 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 953 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 441367.786988 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 753.790798 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 420611422 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 949 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 443215.407798 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 755.122971 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.368712 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.368712 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 952 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 753.790798 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.368062 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.368062 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 948 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 886 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.464844 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 841250919 # Number of tag accesses -system.cpu.icache.tags.data_accesses 841250919 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 420623501 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 420623501 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 420623501 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 420623501 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 420623501 # number of overall hits -system.cpu.icache.overall_hits::total 420623501 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1482 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1482 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1482 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1482 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1482 # number of overall misses -system.cpu.icache.overall_misses::total 1482 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 113433000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 113433000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 113433000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 113433000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 113433000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 113433000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 420624983 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 420624983 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 420624983 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 420624983 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 420624983 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 420624983 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 882 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 841226771 # Number of tag accesses +system.cpu.icache.tags.data_accesses 841226771 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 420611422 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 420611422 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 420611422 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 420611422 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 420611422 # number of overall hits +system.cpu.icache.overall_hits::total 420611422 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1489 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1489 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1489 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1489 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1489 # number of overall misses +system.cpu.icache.overall_misses::total 1489 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 114620499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 114620499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 114620499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 114620499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 114620499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 114620499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 420612911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 420612911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 420612911 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 420612911 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 420612911 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 420612911 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76540.485830 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76540.485830 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76540.485830 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76540.485830 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76540.485830 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76540.485830 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 290 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76978.172599 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76978.172599 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76978.172599 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76978.172599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76978.172599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76978.172599 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 274 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1 # number of writebacks system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 529 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 529 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 529 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 529 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 529 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 953 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 953 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 953 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 953 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 953 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79168000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 79168000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79168000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 79168000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79168000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 79168000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 540 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 540 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 540 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 540 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 540 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 949 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 949 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 949 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 949 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79774499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 79774499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79774499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 79774499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79774499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 79774499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83072.402938 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83072.402938 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83072.402938 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83072.402938 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83072.402938 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83072.402938 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84061.642782 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84061.642782 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1929037 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31408.501295 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14580101 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1958824 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.443293 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1929018 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31408.626842 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14580161 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1958805 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.443396 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 28140218000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14352.871617 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.846080 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 17029.783598 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.438015 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000789 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.519708 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958511 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14352.619403 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.692409 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 17030.315030 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.438007 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000784 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.519724 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958515 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29787 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 977 # Occupied blocks per task id @@ -889,84 +896,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 615 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17550 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10488 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909027 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 151193328 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 151193328 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 3727717 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3727717 # number of WritebackDirty hits +system.cpu.l2cache.tags.tag_accesses 151193610 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 151193610 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3727750 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3727750 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1106791 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1106791 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6143698 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6143698 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7250489 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7250489 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7250489 # number of overall hits -system.cpu.l2cache.overall_hits::total 7250489 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 772417 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 772417 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 953 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 953 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1188371 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1188371 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 953 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1960788 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1961741 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 953 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1960788 # number of overall misses -system.cpu.l2cache.overall_misses::total 1961741 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 69331694500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 69331694500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 77733500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 77733500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106499450500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 106499450500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 77733500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 175831145000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 175908878500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 77733500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 175831145000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 175908878500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3727717 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3727717 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 1106786 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1106786 # number of ReadExReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6143738 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6143738 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 7250524 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7250524 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7250524 # number of overall hits +system.cpu.l2cache.overall_hits::total 7250524 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 772419 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 772419 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 949 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 949 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1188355 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1188355 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 949 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1960774 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1961723 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 949 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1960774 # number of overall misses +system.cpu.l2cache.overall_misses::total 1961723 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 69313632000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 69313632000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 78342500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 78342500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106514273500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 106514273500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 78342500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 175827905500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 175906248000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 78342500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 175827905500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 175906248000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3727750 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3727750 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879208 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1879208 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 953 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 953 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7332069 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7332069 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 953 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9211277 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9212230 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 953 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9211277 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9212230 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411033 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.411033 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1879205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 949 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 949 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7332093 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7332093 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 949 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9211298 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9212247 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 949 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9211298 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9212247 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411035 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.411035 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162079 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162079 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162076 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162076 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.212868 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.212950 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.212866 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.212947 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.212868 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.212950 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89759.410396 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89759.410396 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81567.156348 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81567.156348 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89618.015334 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89618.015334 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81567.156348 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89673.715363 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89669.777254 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81567.156348 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89673.715363 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89669.777254 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.212866 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.212947 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89735.793656 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89735.793656 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82552.687039 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82552.687039 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89631.695495 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89631.695495 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82552.687039 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89672.703483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89669.259116 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82552.687039 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89672.703483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89669.259116 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -975,123 +982,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1024311 # number of writebacks -system.cpu.l2cache.writebacks::total 1024311 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1024304 # number of writebacks +system.cpu.l2cache.writebacks::total 1024304 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 240 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772417 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 772417 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 953 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 953 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188371 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1188371 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 953 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1960788 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1961741 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 953 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1960788 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1961741 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61607524500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61607524500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68203500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68203500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 94615740500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 94615740500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68203500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156223265000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 156291468500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68203500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156223265000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 156291468500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772419 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 772419 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 949 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 949 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188355 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1188355 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1960774 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961723 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1960774 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961723 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61589442000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61589442000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68852500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68852500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 94630723500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 94630723500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68852500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156220165500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 156289018000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68852500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156220165500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 156289018000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411033 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411033 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411035 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411035 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162079 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162079 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162076 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162076 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212868 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.212950 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212866 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.212947 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212868 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.212950 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79759.410396 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79759.410396 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71567.156348 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71567.156348 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79618.015334 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79618.015334 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71567.156348 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79673.715363 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.777254 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71567.156348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79673.715363 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.777254 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212866 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.212947 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79735.793656 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79735.793656 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72552.687039 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72552.687039 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79631.695495 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79631.695495 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72552.687039 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79672.703483 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.259116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72552.687039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79672.703483 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.259116 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 18419412 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207182 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 18419450 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207203 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1280 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1275 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1275 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7333022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4752028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7333042 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4752054 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6384190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332069 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1907 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629735 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27631642 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828095616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 828156672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1929037 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 11141267 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010718 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::CleanEvict 6384166 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 949 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332093 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629798 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27631697 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828099072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 828159872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1929018 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11141265 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000114 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010697 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11139987 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1280 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11139990 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1275 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11141267 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12937424000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11141265 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12937476000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1429500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1423999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13816915500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13816947000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1189324 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1024311 # Transaction distribution -system.membus.trans_dist::CleanEvict 903686 # Transaction distribution -system.membus.trans_dist::ReadExReq 772417 # Transaction distribution -system.membus.trans_dist::ReadExResp 772417 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1189324 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851479 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5851479 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191107328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191107328 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1189304 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1024304 # Transaction distribution +system.membus.trans_dist::CleanEvict 903679 # Transaction distribution +system.membus.trans_dist::ReadExReq 772419 # Transaction distribution +system.membus.trans_dist::ReadExResp 772419 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1189304 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851429 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5851429 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191105728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191105728 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3889738 # Request fanout histogram +system.membus.snoop_fanout::samples 3889706 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3889738 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3889706 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3889738 # Request fanout histogram -system.membus.reqLayer0.occupancy 8475624000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3889706 # Request fanout histogram +system.membus.reqLayer0.occupancy 8475680000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 10684646000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10684396000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 0ee27457c..0b0903e3c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,68 +1,68 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.116861 # Number of seconds simulated -sim_ticks 1116860578500 # Number of ticks simulated -final_tick 1116860578500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.116866 # Number of seconds simulated +sim_ticks 1116865668500 # Number of ticks simulated +final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 228405 # Simulator instruction rate (inst/s) -host_op_rate 246072 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 165157932 # Simulator tick rate (ticks/s) -host_mem_usage 318996 # Number of bytes of host memory used -host_seconds 6762.38 # Real time elapsed on the host +host_inst_rate 315195 # Simulator instruction rate (inst/s) +host_op_rate 339575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 227915704 # Simulator tick rate (ticks/s) +host_mem_usage 272300 # Number of bytes of host memory used +host_seconds 4900.35 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 50176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory -system.physmem.bytes_read::total 130981888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50176 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2045808 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2046592 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 44926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117231922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117276848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 44926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 44926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60175704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60175704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60175704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 44926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117231922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177452552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2046592 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 44868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117231388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 44868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 44868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 44868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117231388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2046591 # Number of read requests accepted system.physmem.writeReqs 1050123 # Number of write requests accepted -system.physmem.readBursts 2046592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 130898112 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83776 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 130898176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83648 # Total number of bytes read from write queue system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130981888 # Total read bytes from the system interface side +system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1309 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 1307 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 127279 # Per bank write bursts system.physmem.perBankRdBursts::1 124661 # Per bank write bursts system.physmem.perBankRdBursts::2 121601 # Per bank write bursts -system.physmem.perBankRdBursts::3 123659 # Per bank write bursts +system.physmem.perBankRdBursts::3 123656 # Per bank write bursts system.physmem.perBankRdBursts::4 122620 # Per bank write bursts -system.physmem.perBankRdBursts::5 122678 # Per bank write bursts +system.physmem.perBankRdBursts::5 122679 # Per bank write bursts system.physmem.perBankRdBursts::6 123247 # Per bank write bursts -system.physmem.perBankRdBursts::7 123768 # Per bank write bursts -system.physmem.perBankRdBursts::8 131395 # Per bank write bursts +system.physmem.perBankRdBursts::7 123770 # Per bank write bursts +system.physmem.perBankRdBursts::8 131396 # Per bank write bursts system.physmem.perBankRdBursts::9 133511 # Per bank write bursts -system.physmem.perBankRdBursts::10 132082 # Per bank write bursts -system.physmem.perBankRdBursts::11 133309 # Per bank write bursts +system.physmem.perBankRdBursts::10 132081 # Per bank write bursts +system.physmem.perBankRdBursts::11 133308 # Per bank write bursts system.physmem.perBankRdBursts::12 133249 # Per bank write bursts -system.physmem.perBankRdBursts::13 133361 # Per bank write bursts -system.physmem.perBankRdBursts::14 129308 # Per bank write bursts +system.physmem.perBankRdBursts::13 133362 # Per bank write bursts +system.physmem.perBankRdBursts::14 129309 # Per bank write bursts system.physmem.perBankRdBursts::15 129555 # Per bank write bursts system.physmem.perBankWrBursts::0 66136 # Per bank write bursts system.physmem.perBankWrBursts::1 64410 # Per bank write bursts @@ -71,25 +71,25 @@ system.physmem.perBankWrBursts::3 63006 # Pe system.physmem.perBankWrBursts::4 63000 # Per bank write bursts system.physmem.perBankWrBursts::5 63100 # Per bank write bursts system.physmem.perBankWrBursts::6 64443 # Per bank write bursts -system.physmem.perBankWrBursts::7 65435 # Per bank write bursts -system.physmem.perBankWrBursts::8 67311 # Per bank write bursts -system.physmem.perBankWrBursts::9 67795 # Per bank write bursts -system.physmem.perBankWrBursts::10 67548 # Per bank write bursts +system.physmem.perBankWrBursts::7 65436 # Per bank write bursts +system.physmem.perBankWrBursts::8 67310 # Per bank write bursts +system.physmem.perBankWrBursts::9 67797 # Per bank write bursts +system.physmem.perBankWrBursts::10 67549 # Per bank write bursts system.physmem.perBankWrBursts::11 67882 # Per bank write bursts -system.physmem.perBankWrBursts::12 67328 # Per bank write bursts +system.physmem.perBankWrBursts::12 67326 # Per bank write bursts system.physmem.perBankWrBursts::13 67793 # Per bank write bursts -system.physmem.perBankWrBursts::14 66483 # Per bank write bursts +system.physmem.perBankWrBursts::14 66482 # Per bank write bursts system.physmem.perBankWrBursts::15 65854 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1116860484000 # Total gap between requests +system.physmem.totGap 1116865574000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2046592 # Read request sizes (log2) +system.physmem.readPktSize::6 2046591 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1050123 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1916633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1916619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56911 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 61204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see @@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1910141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.711749 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.835384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.555895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485377 77.76% 77.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305179 15.98% 93.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52494 2.75% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21040 1.10% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13364 0.70% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7561 0.40% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5492 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5154 0.27% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14480 0.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1910141 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61138 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.410579 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 159.595244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61092 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1910138 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.711175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.836423 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.540224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1485349 77.76% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305158 15.98% 93.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52532 2.75% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21047 1.10% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13374 0.70% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7565 0.40% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5491 0.29% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5162 0.27% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14460 0.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1910138 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61136 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.411672 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 159.590236 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61090 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 21 0.03% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes @@ -219,27 +219,27 @@ system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61138 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61138 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.175897 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.140866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.098115 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27038 44.22% 44.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1118 1.83% 46.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28658 46.87% 92.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3907 6.39% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 362 0.59% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 47 0.08% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61136 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.176459 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.141461 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.097536 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27008 44.18% 44.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1128 1.85% 46.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28688 46.92% 92.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3895 6.37% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 363 0.59% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 46 0.08% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61138 # Writes before turning the bus around for reads -system.physmem.totQLat 38118822750 # Total ticks spent queuing -system.physmem.totMemAccLat 76467879000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10226415000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18637.43 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 61136 # Writes before turning the bus around for reads +system.physmem.totQLat 38124700750 # Total ticks spent queuing +system.physmem.totMemAccLat 76473775750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10226420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18640.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37387.43 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37390.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s @@ -250,49 +250,53 @@ system.physmem.busUtilRead 0.92 # Da system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing -system.physmem.readRowHits 773327 # Number of row buffer hits during reads -system.physmem.writeRowHits 411912 # Number of row buffer hits during writes +system.physmem.readRowHits 773341 # Number of row buffer hits during reads +system.physmem.writeRowHits 411895 # Number of row buffer hits during writes system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.23 # Row buffer hit rate for writes -system.physmem.avgGap 360659.76 # Average gap between requests +system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes +system.physmem.avgGap 360661.52 # Average gap between requests system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7038745560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3840585375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7718170200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3318446880 # Energy for write commands per rank (pJ) +system.physmem_0.actEnergy 7039078200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3840766875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7717881600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 420695682570 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 301084680000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 816644156985 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.196552 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 498171573500 # Time in different power states +system.physmem_0.actBackEnergy 420697412235 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301083150000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 816644588670 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.196952 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 498171344000 # Time in different power states system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 581394006750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 581396539000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7401920400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4038746250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8234982600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3486201120 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 7401549960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4038544125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8234959200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 429157184085 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 293662305750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 818929186605 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.242498 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 485776924250 # Time in different power states +system.physmem_1.actBackEnergy 429293377035 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 293542830000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 818945301360 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.256935 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 485580062750 # Time in different power states system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 593789084750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 239639085 # Number of BP lookups -system.cpu.branchPred.condPredicted 186342301 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14526140 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 130646105 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122079391 # Number of BTB hits +system.cpu.branchPred.lookups 239639355 # Number of BP lookups +system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 130646338 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122079091 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.442809 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15657029 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 93.442413 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15657057 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 537 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 230 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 307 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,68 +415,103 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2233721157 # number of cpu cycles simulated +system.cpu.numCycles 2233731337 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41470128 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41470388 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446183 # CPI: cycles per instruction -system.cpu.ipc 0.691475 # IPC: instructions per cycle -system.cpu.tickCycles 1834122800 # Number of cycles that the object actually ticked -system.cpu.idleCycles 399598357 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.446190 # CPI: cycles per instruction +system.cpu.ipc 0.691472 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction +system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction +system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 1664032481 # Class of committed instruction +system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked +system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 9221041 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.616187 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624218895 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.665000 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.665004 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616187 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616095 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 245 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276841907 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276841907 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453887715 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453887715 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331057 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331057 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331073 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624218772 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624218772 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624218773 # number of overall hits -system.cpu.dcache.overall_hits::total 624218773 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 624218805 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624218805 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624218806 # number of overall hits +system.cpu.dcache.overall_hits::total 624218806 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7334498 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7334498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254990 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254990 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254974 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254974 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9589488 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9589488 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9589490 # number of overall misses -system.cpu.dcache.overall_misses::total 9589490 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 190927662500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 190927662500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109073789000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109073789000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 300001451500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 300001451500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 300001451500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 300001451500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461222213 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461222213 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9589472 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9589472 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9589474 # number of overall misses +system.cpu.dcache.overall_misses::total 9589474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 190926660000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 190926660000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109083916000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109083916000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 300010576000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 300010576000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 300010576000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 300010576000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461222230 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461222230 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -481,10 +520,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633808260 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633808260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633808263 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633808263 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633808277 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633808277 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633808280 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633808280 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses @@ -495,14 +534,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.456072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.456072 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48369.965720 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48369.965720 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31284.407624 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31284.407624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.401100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31284.401100 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.319390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.319390 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48374.799887 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48374.799887 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.411334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31285.411334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.404809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31285.404809 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,16 +550,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3684566 # number of writebacks -system.cpu.dcache.writebacks::total 3684566 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3684567 # number of writebacks +system.cpu.dcache.writebacks::total 3684567 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364137 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364137 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364352 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364352 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364352 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364352 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364121 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364121 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364336 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364336 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364336 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364336 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334283 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7334283 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890853 # number of WriteReq MSHR misses @@ -531,16 +570,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9225136 system.cpu.dcache.demand_mshr_misses::total 9225136 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9225137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9225137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183587623500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 183587623500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84772423500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84772423500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183586477500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 183586477500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84779361000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84779361000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268360047000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 268360047000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268360121000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 268360121000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268365838500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 268365838500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268365912500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 268365912500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -551,69 +590,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.434361 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.434361 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44832.900019 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44832.900019 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.278109 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.278109 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.091138 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.091138 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.096006 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.096006 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.384835 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 465281420 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567416.365854 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.384835 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322942 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322942 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 660.385482 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322454 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322454 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 930565300 # Number of tag accesses -system.cpu.icache.tags.data_accesses 930565300 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 465281420 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 465281420 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 465281420 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 465281420 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 465281420 # number of overall hits -system.cpu.icache.overall_hits::total 465281420 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses -system.cpu.icache.overall_misses::total 820 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62291000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62291000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62291000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62291000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62291000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62291000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 465282240 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 465282240 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 465282240 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 465282240 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 465282240 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 465282240 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses +system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 465281510 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 465281510 # number of overall hits +system.cpu.icache.overall_hits::total 465281510 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 819 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 819 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 819 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 819 # number of overall misses +system.cpu.icache.overall_misses::total 819 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62402500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62402500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62402500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62402500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62402500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62402500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465282329 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465282329 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465282329 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465282329 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465282329 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465282329 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75964.634146 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75964.634146 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75964.634146 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75964.634146 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75964.634146 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75964.634146 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76193.528694 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76193.528694 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76193.528694 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76193.528694 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -624,133 +663,133 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 29 # number of writebacks system.cpu.icache.writebacks::total 29 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61471000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 61471000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61471000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 61471000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61471000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 61471000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61583500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 61583500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61583500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 61583500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61583500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61583500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74964.634146 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74964.634146 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74964.634146 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74964.634146 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74964.634146 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74964.634146 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2013920 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31258.306174 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14509192 # Total number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2013919 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.099490 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14832.753669 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.505297 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.047209 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.452660 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.500459 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.953928 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16398.892088 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.452664 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000807 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.500454 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.953926 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1251 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1250 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 151498012 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 151498012 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 3684566 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3684566 # number of WritebackDirty hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 29 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1089694 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1089694 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 35 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 35 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089631 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6089631 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 35 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7179325 # number of demand (read+write) hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 36 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7179324 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 7179360 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 35 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7179325 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 36 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7179324 # number of overall hits system.cpu.l2cache.overall_hits::total 7179360 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 801159 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 801159 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 785 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 785 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244653 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1244653 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 785 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2045812 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2046597 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2045812 # number of overall misses -system.cpu.l2cache.overall_misses::total 2046597 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70434494500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 70434494500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59842000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 59842000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108638363500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 108638363500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 59842000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 179072858000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179132700000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 59842000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 179072858000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179132700000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3684566 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3684566 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 783 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 783 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244654 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1244654 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 783 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2045813 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2046596 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 783 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2045813 # number of overall misses +system.cpu.l2cache.overall_misses::total 2046596 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70441435500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70441435500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59945000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 59945000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108637226500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 108637226500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 59945000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 179078662000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 179138607000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 59945000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 179078662000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 179138607000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3684567 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3684567 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 29 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 29 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890853 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1890853 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 820 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 820 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 819 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 819 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7334284 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 7334284 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 820 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 819 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 9225137 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9225957 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 820 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9225956 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 819 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9225137 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9225957 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9225956 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423702 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.423702 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.957317 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.957317 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169703 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169703 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.957317 # miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.956044 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.956044 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169704 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169704 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956044 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.221765 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.221830 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.957317 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956044 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87915.750182 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87915.750182 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76231.847134 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76231.847134 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87284.057083 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87284.057083 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76231.847134 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87531.433973 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87527.099864 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76231.847134 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87531.433973 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87527.099864 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87924.413880 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87924.413880 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76558.109834 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76558.109834 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87283.073449 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87283.073449 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76558.109834 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87530.028887 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76558.109834 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87530.028887 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -761,131 +800,127 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks system.cpu.l2cache.writebacks::total 1050123 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 214 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 214 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801159 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 801159 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 784 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 784 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 783 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 783 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 784 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2045808 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2046592 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 784 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2046591 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2045808 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2046592 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62422904500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62422904500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 51986500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 51986500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96191610000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96191610000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51986500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158614514500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 158666501000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51986500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158614514500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158666501000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 2046591 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62429845500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62429845500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52115000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52115000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96190393500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96190393500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52115000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158620239000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158672354000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52115000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158620239000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158672354000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423702 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423702 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956098 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956098 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956044 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169703 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169703 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956098 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956098 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77915.750182 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77915.750182 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66309.311224 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66309.311224 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77284.125886 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77284.125886 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66309.311224 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77531.476316 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77527.177376 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66309.311224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77531.476316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77527.177376 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77924.413880 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77924.413880 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66558.109834 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66558.109834 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77283.148502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77283.148502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 18447027 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1287 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1281 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7335104 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4734689 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6500272 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6500270 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 820 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1669 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1667 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671315 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27672984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27672982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826221056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2013920 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 11239877 # Request fanout histogram +system.cpu.toL2Bus.snoops 2013919 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11239875 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.016091 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.016088 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11236984 99.97% 99.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2887 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11236983 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2886 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11239877 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12908108500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11239875 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12908109000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1230499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13837707496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1245433 # Transaction distribution +system.membus.trans_dist::ReadResp 1245432 # Transaction distribution system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution system.membus.trans_dist::CleanEvict 962724 # Transaction distribution system.membus.trans_dist::ReadExReq 801159 # Transaction distribution system.membus.trans_dist::ReadExResp 801159 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1245433 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106031 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6106031 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198189760 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1245432 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106029 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6106029 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4059439 # Request fanout histogram +system.membus.snoop_fanout::samples 4059438 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4059439 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4059438 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4059439 # Request fanout histogram -system.membus.reqLayer0.occupancy 8663213500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4059438 # Request fanout histogram +system.membus.reqLayer0.occupancy 8663216000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11191513500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11191487250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 659d2c639..ad14d9d64 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.767851 # Number of seconds simulated -sim_ticks 767851412000 # Number of ticks simulated -final_tick 767851412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.767804 # Number of seconds simulated +sim_ticks 767803843500 # Number of ticks simulated +final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96147 # Simulator instruction rate (inst/s) -host_op_rate 103584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47797800 # Simulator tick rate (ticks/s) -host_mem_usage 342312 # Number of bytes of host memory used -host_seconds 16064.58 # Real time elapsed on the host +host_inst_rate 188017 # Simulator instruction rate (inst/s) +host_op_rate 202560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93463451 # Simulator tick rate (ticks/s) +host_mem_usage 313392 # Number of bytes of host memory used +host_seconds 8215.02 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 64960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 235334976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63685504 # Number of bytes read from this memory -system.physmem.bytes_read::total 299085440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104625984 # Number of bytes written to this memory -system.physmem.bytes_written::total 104625984 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1015 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3677109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 995086 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4673210 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1634781 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1634781 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 84600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 306485047 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82939880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 389509527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 84600 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84600 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136258112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136258112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136258112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 84600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 306485047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82939880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 525767639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4673210 # Number of read requests accepted -system.physmem.writeReqs 1634781 # Number of write requests accepted -system.physmem.readBursts 4673210 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1634781 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 298595648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 489792 # Total number of bytes read from write queue -system.physmem.bytesWritten 104623680 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299085440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104625984 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7653 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 16 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory +system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory +system.physmem.bytes_written::total 104697344 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3676881 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 995485 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4673385 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1635896 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1635896 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 84938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 306485030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82978277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 389548245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 84938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136359495 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136359495 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136359495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 84938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 306485030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82978277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 525907740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4673385 # Number of read requests accepted +system.physmem.writeReqs 1635896 # Number of write requests accepted +system.physmem.readBursts 4673385 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1635896 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 298598336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 498304 # Total number of bytes read from write queue +system.physmem.bytesWritten 104693696 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299096640 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104697344 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7786 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301092 # Per bank write bursts -system.physmem.perBankRdBursts::1 298585 # Per bank write bursts -system.physmem.perBankRdBursts::2 284412 # Per bank write bursts -system.physmem.perBankRdBursts::3 287553 # Per bank write bursts -system.physmem.perBankRdBursts::4 288019 # Per bank write bursts -system.physmem.perBankRdBursts::5 285340 # Per bank write bursts -system.physmem.perBankRdBursts::6 281024 # Per bank write bursts -system.physmem.perBankRdBursts::7 277791 # Per bank write bursts -system.physmem.perBankRdBursts::8 293545 # Per bank write bursts -system.physmem.perBankRdBursts::9 299289 # Per bank write bursts -system.physmem.perBankRdBursts::10 291195 # Per bank write bursts -system.physmem.perBankRdBursts::11 297241 # Per bank write bursts -system.physmem.perBankRdBursts::12 298946 # Per bank write bursts -system.physmem.perBankRdBursts::13 298565 # Per bank write bursts -system.physmem.perBankRdBursts::14 293948 # Per bank write bursts -system.physmem.perBankRdBursts::15 289012 # Per bank write bursts -system.physmem.perBankWrBursts::0 103815 # Per bank write bursts -system.physmem.perBankWrBursts::1 101663 # Per bank write bursts -system.physmem.perBankWrBursts::2 99081 # Per bank write bursts -system.physmem.perBankWrBursts::3 99729 # Per bank write bursts -system.physmem.perBankWrBursts::4 98947 # Per bank write bursts -system.physmem.perBankWrBursts::5 98825 # Per bank write bursts -system.physmem.perBankWrBursts::6 102537 # Per bank write bursts -system.physmem.perBankWrBursts::7 104314 # Per bank write bursts -system.physmem.perBankWrBursts::8 105187 # Per bank write bursts -system.physmem.perBankWrBursts::9 104412 # Per bank write bursts -system.physmem.perBankWrBursts::10 101681 # Per bank write bursts -system.physmem.perBankWrBursts::11 102588 # Per bank write bursts -system.physmem.perBankWrBursts::12 102740 # Per bank write bursts -system.physmem.perBankWrBursts::13 102708 # Per bank write bursts -system.physmem.perBankWrBursts::14 104126 # Per bank write bursts -system.physmem.perBankWrBursts::15 102392 # Per bank write bursts +system.physmem.perBankRdBursts::0 301126 # Per bank write bursts +system.physmem.perBankRdBursts::1 298685 # Per bank write bursts +system.physmem.perBankRdBursts::2 284250 # Per bank write bursts +system.physmem.perBankRdBursts::3 287696 # Per bank write bursts +system.physmem.perBankRdBursts::4 287908 # Per bank write bursts +system.physmem.perBankRdBursts::5 285921 # Per bank write bursts +system.physmem.perBankRdBursts::6 280645 # Per bank write bursts +system.physmem.perBankRdBursts::7 277366 # Per bank write bursts +system.physmem.perBankRdBursts::8 293768 # Per bank write bursts +system.physmem.perBankRdBursts::9 299240 # Per bank write bursts +system.physmem.perBankRdBursts::10 292091 # Per bank write bursts +system.physmem.perBankRdBursts::11 297828 # Per bank write bursts +system.physmem.perBankRdBursts::12 299005 # Per bank write bursts +system.physmem.perBankRdBursts::13 298032 # Per bank write bursts +system.physmem.perBankRdBursts::14 293386 # Per bank write bursts +system.physmem.perBankRdBursts::15 288652 # Per bank write bursts +system.physmem.perBankWrBursts::0 103980 # Per bank write bursts +system.physmem.perBankWrBursts::1 101811 # Per bank write bursts +system.physmem.perBankWrBursts::2 99205 # Per bank write bursts +system.physmem.perBankWrBursts::3 99712 # Per bank write bursts +system.physmem.perBankWrBursts::4 99000 # Per bank write bursts +system.physmem.perBankWrBursts::5 99026 # Per bank write bursts +system.physmem.perBankWrBursts::6 102693 # Per bank write bursts +system.physmem.perBankWrBursts::7 104157 # Per bank write bursts +system.physmem.perBankWrBursts::8 105172 # Per bank write bursts +system.physmem.perBankWrBursts::9 104159 # Per bank write bursts +system.physmem.perBankWrBursts::10 102137 # Per bank write bursts +system.physmem.perBankWrBursts::11 102620 # Per bank write bursts +system.physmem.perBankWrBursts::12 102863 # Per bank write bursts +system.physmem.perBankWrBursts::13 102594 # Per bank write bursts +system.physmem.perBankWrBursts::14 104213 # Per bank write bursts +system.physmem.perBankWrBursts::15 102497 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 767851370500 # Total gap between requests +system.physmem.totGap 767803802500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4673210 # Read request sizes (log2) +system.physmem.readPktSize::6 4673385 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1634781 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2763298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1028318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 325143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 231238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 149204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 81551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37590 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23700 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18069 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1700 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1635896 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2761676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1029435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 325938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 231496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 148985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 81565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 107211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 109230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 110922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 111311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 100806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 100214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 73202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 109489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 111204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 101152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,116 +197,120 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4241219 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 95.071143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.963204 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.762534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3377855 79.64% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 665363 15.69% 95.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 95455 2.25% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35191 0.83% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22820 0.54% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12430 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7284 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5212 0.12% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19609 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4241219 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97672 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.767497 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 100.584321 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95276 97.55% 97.55% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1151 1.18% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 710 0.73% 99.45% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 401 0.41% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 104 0.11% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4243508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 95.037234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.939445 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.771916 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3380789 79.67% 79.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 664864 15.67% 95.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95298 2.25% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35170 0.83% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22966 0.54% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12163 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7344 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19569 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4243508 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97753 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.727814 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 100.001834 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95363 97.56% 97.56% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1154 1.18% 98.74% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 681 0.70% 99.43% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 412 0.42% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 112 0.11% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 14 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 8 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3840-4095 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-4863 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97672 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97672 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.737089 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.693249 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.262570 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 68211 69.84% 69.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2039 2.09% 71.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18248 18.68% 90.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5781 5.92% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 2040 2.09% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 736 0.75% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 303 0.31% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 177 0.18% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 71 0.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 35 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 22 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 97753 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97753 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.734412 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.690766 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.259650 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 68350 69.92% 69.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1981 2.03% 71.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18352 18.77% 90.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5702 5.83% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2016 2.06% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 741 0.76% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 311 0.32% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 155 0.16% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 75 0.08% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 43 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 16 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97672 # Writes before turning the bus around for reads -system.physmem.totQLat 128403949042 # Total ticks spent queuing -system.physmem.totMemAccLat 215883142792 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23327785000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27521.68 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::35 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97753 # Writes before turning the bus around for reads +system.physmem.totQLat 128478496877 # Total ticks spent queuing +system.physmem.totMemAccLat 215958478127 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23327995000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27537.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46271.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 388.87 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 136.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 389.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.26 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46287.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 388.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 136.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 389.55 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.36 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.10 # Data bus utilization in percentage system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing -system.physmem.readRowHits 1711348 # Number of row buffer hits during reads -system.physmem.writeRowHits 347723 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.27 # Row buffer hit rate for writes -system.physmem.avgGap 121726.77 # Average gap between requests -system.physmem.pageHitRate 32.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15936283440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8695392750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 17969468400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5241691440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50152152960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 414929915685 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 96735845250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 609660749925 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.985115 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 158402074288 # Time in different power states -system.physmem_0.memoryStateTime::REF 25640160000 # Time in different power states +system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing +system.physmem.readRowHits 1710736 # Number of row buffer hits during reads +system.physmem.writeRowHits 347188 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.22 # Row buffer hit rate for writes +system.physmem.avgGap 121694.34 # Average gap between requests +system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15941658600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8698325625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 17967846000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5246104320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 414557114310 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 97034832000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 609594982455 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.947771 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 158900831773 # Time in different power states +system.physmem_0.memoryStateTime::REF 25638600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 583806871462 # Time in different power states +system.physmem_0.memoryStateTime::ACT 583262954477 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16127249040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8799590250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18421525200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5351352480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50152152960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 410152468095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100926587250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 609930925275 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.336977 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165409997970 # Time in different power states -system.physmem_1.memoryStateTime::REF 25640160000 # Time in different power states +system.physmem_1.actEnergy 16139254320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8806140750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18423607800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5354132400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 410075734410 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.363055 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states +system.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 576799157530 # Time in different power states +system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286283871 # Number of BP lookups -system.cpu.branchPred.condPredicted 223409198 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14630000 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157660833 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150354422 # Number of BTB hits +system.cpu.branchPred.lookups 286292198 # Number of BP lookups +system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150355883 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.365741 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16641462 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1888 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -425,128 +429,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1535702825 # number of cpu cycles simulated +system.cpu.numCycles 1535607688 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13928194 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067545272 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286283871 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166995884 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1507053814 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29284843 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 194 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 878 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656961352 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 924 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1535625501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.442414 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29287239 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 992 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656968436 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 958 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1535531474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.442524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228151 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 453179554 29.51% 29.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465452437 30.31% 59.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101425758 6.60% 66.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515567752 33.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 453078112 29.51% 29.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465445913 30.31% 59.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101427094 6.61% 66.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515580355 33.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1535625501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.186419 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.346319 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74705832 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 538167437 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849914387 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58196125 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14641720 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42203366 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 738 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037249572 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52491206 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14641720 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139798655 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 457197163 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837846796 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86126990 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976444651 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26741715 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45304447 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126733 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1592000 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25068959 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985917884 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128448478 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432959376 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 137 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1535531474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.186436 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.346420 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74706893 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 538056624 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849925630 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58199384 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14642943 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42203258 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 730 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037275151 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52500118 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14642943 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139803593 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 457092273 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13624 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837854747 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86124294 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976468269 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26746953 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45300136 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126625 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1588286 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25069373 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985943496 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128568325 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432995559 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 145 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 311018939 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 156 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 147 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111499439 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542575800 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199311764 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26984794 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29485637 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1948029914 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 213 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857440521 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13485383 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283997711 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647527066 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1535625501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.209566 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150575 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 311044551 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 174 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111502635 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542585286 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199312070 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26927303 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29234152 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1948047142 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857492479 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13497229 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 284014957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647584155 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1535531474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.209674 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150607 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 582643896 37.94% 37.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326148429 21.24% 59.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378192784 24.63% 83.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219661214 14.30% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28973008 1.89% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6170 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 582548107 37.94% 37.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326134076 21.24% 59.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378190631 24.63% 83.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219663672 14.31% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28988815 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6173 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1535625501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1535531474 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166041601 41.02% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1966 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191453028 47.29% 88.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47322574 11.69% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166038532 40.99% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1976 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191466165 47.27% 88.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47567904 11.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138257310 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800951 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138257084 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800920 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -568,88 +572,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532072663 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186309545 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532121986 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186312436 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857440521 # Type of FU issued -system.cpu.iq.rate 1.209505 # Inst issue rate -system.cpu.iq.fu_busy_cnt 404819169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.217945 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5668810855 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2232040657 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805715757 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 1857492479 # Type of FU issued +system.cpu.iq.rate 1.209614 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405074577 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218076 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5669087998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2232075127 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805719723 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 240 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262259556 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262566922 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17798811 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 17809734 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84269466 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66606 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13290 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24464719 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84278952 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66732 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13280 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24465025 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4470256 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4868274 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4505677 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4870984 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14641720 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25371637 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1306573 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1948030205 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14642943 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25375759 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1295309 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1948047519 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542575800 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199311764 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 151 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159252 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1145955 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13290 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7700252 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8704527 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16404779 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827784428 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516894749 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29656093 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542585286 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199312070 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159534 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1134383 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13280 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7701154 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8705181 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16406335 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827826675 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516940315 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29665804 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 78 # number of nop insts executed -system.cpu.iew.exec_refs 698647521 # number of memory reference insts executed -system.cpu.iew.exec_branches 229543891 # Number of branches executed -system.cpu.iew.exec_stores 181752772 # Number of stores executed -system.cpu.iew.exec_rate 1.190194 # Inst execution rate -system.cpu.iew.wb_sent 1808752237 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805715827 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169206310 # num instructions producing a value -system.cpu.iew.wb_consumers 1689633446 # num instructions consuming a value -system.cpu.iew.wb_rate 1.175824 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691988 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258099424 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 146 # number of nop insts executed +system.cpu.iew.exec_refs 698692225 # number of memory reference insts executed +system.cpu.iew.exec_branches 229542687 # Number of branches executed +system.cpu.iew.exec_stores 181751910 # Number of stores executed +system.cpu.iew.exec_rate 1.190295 # Inst execution rate +system.cpu.iew.wb_sent 1808754463 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805719795 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169207800 # num instructions producing a value +system.cpu.iew.wb_consumers 1689618799 # num instructions consuming a value +system.cpu.iew.wb_rate 1.175899 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 258113026 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14629299 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1496131949 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.112223 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.027889 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14630522 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1496036001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.112294 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.028030 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 915820639 61.21% 61.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250646763 16.75% 77.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110056209 7.36% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55261288 3.69% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29350080 1.96% 90.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34099698 2.28% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24719772 1.65% 94.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18148053 1.21% 96.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58029447 3.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 915722932 61.21% 61.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250663462 16.76% 77.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110062832 7.36% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55282207 3.70% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29306686 1.96% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34079757 2.28% 93.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24721963 1.65% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18129916 1.21% 96.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58066246 3.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1496131949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1496036001 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -695,76 +699,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58029447 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3360233761 # The number of ROB reads -system.cpu.rob.rob_writes 3883762364 # The number of ROB writes -system.cpu.timesIdled 834 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 77324 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58066246 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3360114616 # The number of ROB reads +system.cpu.rob.rob_writes 3883791528 # The number of ROB writes +system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76214 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.994264 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.994264 # CPI: Total CPI of All Threads -system.cpu.ipc 1.005769 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.005769 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175773439 # number of integer regfile reads -system.cpu.int_regfile_writes 1261589366 # number of integer regfile writes -system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 52 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965635020 # number of cc regfile reads -system.cpu.cc_regfile_writes 551858996 # number of cc regfile writes -system.cpu.misc_regfile_reads 675848866 # number of misc regfile reads +system.cpu.cpi 0.994202 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.994202 # CPI: Total CPI of All Threads +system.cpu.ipc 1.005832 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.005832 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads +system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes +system.cpu.fp_regfile_reads 42 # number of floating regfile reads +system.cpu.fp_regfile_writes 54 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads +system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes +system.cpu.misc_regfile_reads 675853701 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17003597 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964807 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638080633 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17004109 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.525085 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 77932500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964807 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 17003710 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 408 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335734207 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335734207 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469362265 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469362265 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168718228 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168718228 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638080493 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638080493 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638080493 # number of overall hits -system.cpu.dcache.overall_hits::total 638080493 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17416613 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17416613 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3867819 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3867819 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638076218 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638076218 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638076218 # number of overall hits +system.cpu.dcache.overall_hits::total 638076218 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17418310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17418310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3867432 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3867432 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21284432 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21284432 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21284434 # number of overall misses -system.cpu.dcache.overall_misses::total 21284434 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 412110560500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 412110560500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 148910053049 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 148910053049 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 21285742 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21285742 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21285744 # number of overall misses +system.cpu.dcache.overall_misses::total 21285744 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 411945425500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 148954509432 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 561020613549 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 561020613549 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 561020613549 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 561020613549 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486778878 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486778878 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 560899934932 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 560899934932 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 560899934932 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 560899934932 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486775913 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486775913 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -773,72 +777,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659364925 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659364925 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659364927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659364927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022411 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022411 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659361960 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659361960 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659361962 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659361962 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022409 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022409 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032280 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032280 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032280 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032280 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23661.923274 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23661.923274 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38499.747028 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38499.747028 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26358.260984 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26358.260984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26358.258507 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26358.258507 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20478587 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3417945 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 942442 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67202 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.729281 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50.860763 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26350.969345 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 17003597 # number of writebacks -system.cpu.dcache.writebacks::total 17003597 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150032 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3150032 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130287 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1130287 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks +system.cpu.dcache.writebacks::total 17003710 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4280319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4280319 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4280319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4280319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266581 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14266581 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737532 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737532 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4281515 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4281515 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4281515 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4281515 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266638 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14266638 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737589 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737589 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17004113 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17004113 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17004114 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17004114 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331850986000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 331850986000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115586978404 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 115586978404 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17004227 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17004227 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17004228 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17004228 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447437964404 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 447437964404 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447438032404 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 447438032404 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 447484732765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 447484800765 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses @@ -849,393 +853,394 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23260.722804 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23260.722804 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42223.060189 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42223.060189 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26313.513937 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26313.513937 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26313.516388 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26313.516388 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 586 # number of replacements -system.cpu.icache.tags.tagsinuse 444.620453 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656959766 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1072 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 612835.602612 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 589 # number of replacements +system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 444.620453 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.868399 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.868399 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313923770 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313923770 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656959766 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656959766 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656959766 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656959766 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656959766 # number of overall hits -system.cpu.icache.overall_hits::total 656959766 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1583 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1583 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1583 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1583 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1583 # number of overall misses -system.cpu.icache.overall_misses::total 1583 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 101448987 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 101448987 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 101448987 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 101448987 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 101448987 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 101448987 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656961349 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656961349 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656961349 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656961349 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656961349 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656961349 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits +system.cpu.icache.overall_hits::total 656966815 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1620 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1620 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1620 # number of overall misses +system.cpu.icache.overall_misses::total 1620 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 98788987 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 98788987 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 98788987 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 98788987 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 98788987 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 98788987 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656968435 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656968435 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656968435 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656968435 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656968435 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656968435 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64086.536323 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64086.536323 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64086.536323 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64086.536323 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64086.536323 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64086.536323 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 16918 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 173 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 89.513228 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 34.600000 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60980.856173 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60980.856173 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17260 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 439 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 586 # number of writebacks -system.cpu.icache.writebacks::total 586 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 509 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 509 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 509 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 509 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 509 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 509 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1074 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1074 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1074 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1074 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1074 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74582990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 74582990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74582990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 74582990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74582990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 74582990 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 589 # number of writebacks +system.cpu.icache.writebacks::total 589 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 544 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 544 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 544 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 544 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73759491 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 73759491 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73759491 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 73759491 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73759491 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 73759491 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69444.124767 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69444.124767 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69444.124767 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69444.124767 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69444.124767 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69444.124767 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 11607728 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11635838 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 19050 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 5 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4655842 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 4705864 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16099.842459 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 22826032 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4721788 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.834192 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 54104143500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 13102.285184 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2.119304 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2995.437971 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.799700 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000129 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.182827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.982656 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 773 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15151 # Occupied blocks per task id +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 4706089 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4722015 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.834615 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 54111720000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2.290302 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2999.119162 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.799460 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000140 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183052 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.982651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15097 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 599 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2950 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4343 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5551 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1838 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.047180 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.924744 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 552240776 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 552240776 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 4834377 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 4834377 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 12148517 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 12148517 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1758217 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1758217 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 57 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 57 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11520794 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 11520794 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 57 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13279011 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13279068 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 57 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13279011 # number of overall hits -system.cpu.l2cache.overall_hits::total 13279068 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 979355 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 979355 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1017 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1017 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2745743 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2745743 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3725098 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3726115 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1017 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3725098 # number of overall misses -system.cpu.l2cache.overall_misses::total 3726115 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 100500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 100500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98934121000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 98934121000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 73094500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 73094500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234186702000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 234186702000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 73094500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 333120823000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 333193917500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 73094500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 333120823000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 333193917500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 4834377 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 4834377 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 12148517 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 12148517 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737572 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737572 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1074 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1074 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266537 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 14266537 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1074 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17004109 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17005183 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1074 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17004109 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17005183 # number of overall (read+write) accesses +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 636 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 191 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 453 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 12149903 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1757087 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1757087 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 56 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 56 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11522367 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 11522367 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 56 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 13279454 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13279510 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 56 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 13279454 # number of overall hits +system.cpu.l2cache.overall_hits::total 13279510 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 980546 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 980546 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1020 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1020 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2744222 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 2744222 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1020 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3724768 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3725788 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1020 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3724768 # number of overall misses +system.cpu.l2cache.overall_misses::total 3725788 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 121000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 121000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99083213500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 99083213500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72272000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 72272000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234079710000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 234079710000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 72272000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 333162923500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 333235195500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 72272000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 333162923500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 333235195500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 4833112 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 4833112 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 12149903 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 12149903 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737633 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2737633 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266589 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 14266589 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 17004222 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17005298 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 17004222 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17005298 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.357746 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.357746 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.946927 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.946927 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192460 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192460 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.946927 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.219070 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.219116 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.946927 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.219070 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.219116 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20100 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20100 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101019.672131 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101019.672131 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71872.664700 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71872.664700 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85290.830934 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85290.830934 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71872.664700 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89426.056174 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89421.265178 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71872.664700 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89426.056174 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89421.265178 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 398 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358173 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.358173 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947955 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947955 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192353 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192353 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947955 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.219050 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.219096 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947955 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.219050 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.219096 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101049.021158 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101049.021158 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70854.901961 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70854.901961 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85299.115742 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85299.115742 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89440.192383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89440.192383 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1634781 # number of writebacks -system.cpu.l2cache.writebacks::total 1634781 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3953 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3953 # number of ReadExReq MSHR hits +system.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks +system.cpu.l2cache.writebacks::total 1635896 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3915 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3915 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45302 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45302 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45253 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45253 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 49255 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 49256 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 49168 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 49169 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 49255 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 49256 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1144188 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1144188 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 975402 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 975402 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1016 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1016 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2700441 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2700441 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1016 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3675843 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3676859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1016 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3675843 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1144188 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4821047 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72422793987 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72422793987 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 70500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 70500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92707545500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92707545500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66931500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66931500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215168959000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215168959000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66931500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307876504500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 307943436000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66931500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307876504500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72422793987 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 380366229987 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 49168 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 49169 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1145204 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976631 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 976631 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1019 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1019 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2698969 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2698969 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3675600 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3676619 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3675600 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4821823 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72434619378 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 85000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 85000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92854351000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92854351000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66085000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66085000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215091513500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215091513500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66085000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307945864500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 308011949500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66085000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307945864500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 380446568878 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356302 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356302 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.945996 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189285 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189285 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216174 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216220 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216174 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356743 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356743 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947026 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189181 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189181 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216204 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.283505 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63296.236271 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14100 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14100 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95045.474071 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95045.474071 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65877.460630 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65877.460630 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79679.192769 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79679.192769 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65877.460630 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83756.706829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83751.766385 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65877.460630 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83756.706829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78897.017595 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.283548 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 34009371 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004197 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21289 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2918881 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2900097 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18784 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 14267609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6469158 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12169806 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5772538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1435459 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737572 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737572 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1074 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266537 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2732 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011834 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51014566 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176493760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176599872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 8842787 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 25847966 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.114476 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.320662 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737633 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737633 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266589 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51012175 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51014915 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 8842499 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 25847794 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.114446 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.320627 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22907787 88.63% 88.63% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2921395 11.30% 99.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 18784 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22908415 88.63% 88.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2920592 11.30% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 18787 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25847966 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34008868522 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25847794 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 13530 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1609497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25506170491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3697667 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1634781 # Transaction distribution -system.membus.trans_dist::CleanEvict 3002759 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 975542 # Transaction distribution -system.membus.trans_dist::ReadExResp 975542 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3697668 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13983964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13983964 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403711360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 403711360 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3696594 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution +system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 976790 # Transaction distribution +system.membus.trans_dist::ReadExResp 976790 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13984484 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403793920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 403793920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9310755 # Request fanout histogram +system.membus.snoop_fanout::samples 9311100 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9310755 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9311100 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9310755 # Request fanout histogram -system.membus.reqLayer0.occupancy 17653458992 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9311100 # Request fanout histogram +system.membus.reqLayer0.occupancy 17657610874 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 25411663187 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25413256779 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |