diff options
Diffstat (limited to 'tests/long/se/60.bzip2')
8 files changed, 75 insertions, 74 deletions
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index e5390bdb7..64ac15724 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -77,7 +77,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -128,6 +128,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 2b9587722..654ed6b82 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atom gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 17:13:04 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -26,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2846007227000 because target called exit() +Exiting @ tick 2846007227500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index b864f8ff9..7cb3ea1a2 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.846007 # Number of seconds simulated -sim_ticks 2846007227000 # Number of ticks simulated -final_tick 2846007227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2846007227500 # Number of ticks simulated +final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1019064 # Simulator instruction rate (inst/s) -host_op_rate 1587794 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 964157561 # Simulator tick rate (ticks/s) -host_mem_usage 283172 # Number of bytes of host memory used -host_seconds 2951.81 # Real time elapsed on the host +host_inst_rate 922936 # Simulator instruction rate (inst/s) +host_op_rate 1438019 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 873209138 # Simulator tick rate (ticks/s) +host_mem_usage 283960 # Number of bytes of host memory used +host_seconds 3259.25 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated -sim_ops 4686862595 # Number of ops (including micro ops) simulated +sim_ops 4686862596 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5023868343 # Number of bytes read from this memory -system.physmem.bytes_read::total 37129731399 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory +system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1239184745 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5252417627 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1239184746 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5252417628 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11281019511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 11281019509 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13046253378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11281019511 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11281019511 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13046253376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11281019509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11281019509 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11281019511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13588998589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 5692014455 # number of cpu cycles simulated +system.cpu.numCycles 5692014456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed -system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses +system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4686862525 # number of integer instructions +system.cpu.num_int_insts 4686862527 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read -system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written +system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read +system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1677713083 # number of memory refs -system.cpu.num_load_insts 1239184745 # Number of load instructions +system.cpu.num_mem_refs 1677713084 # number of memory refs +system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5692014455 # Number of busy cycles +system.cpu.num_busy_cycles 5692014456 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 55b9fc1a9..dfbf80a27 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -168,6 +168,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -200,6 +201,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index b6532688b..88a0bc2fc 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 18:35:45 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -26,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 5882580525000 because target called exit() +Exiting @ tick 5882580526000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 790f1ac3e..914311460 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.882581 # Number of seconds simulated -sim_ticks 5882580525000 # Number of ticks simulated -final_tick 5882580525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5882580526000 # Number of ticks simulated +final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 639726 # Simulator instruction rate (inst/s) -host_op_rate 996751 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1251043124 # Simulator tick rate (ticks/s) -host_mem_usage 291744 # Number of bytes of host memory used -host_seconds 4702.14 # Real time elapsed on the host +host_inst_rate 579739 # Simulator instruction rate (inst/s) +host_op_rate 903286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1133733281 # Simulator tick rate (ticks/s) +host_mem_usage 291512 # Number of bytes of host memory used +host_seconds 5188.68 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated -sim_ops 4686862595 # Number of ops (including micro ops) simulated +sim_ops 4686862596 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory @@ -35,26 +35,26 @@ system.physmem.bw_total::cpu.inst 7344 # To system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11765161050 # number of cpu cycles simulated +system.cpu.numCycles 11765161052 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed -system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses +system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4686862525 # number of integer instructions +system.cpu.num_int_insts 4686862527 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read -system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written +system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read +system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1677713083 # number of memory refs -system.cpu.num_load_insts 1239184745 # Number of load instructions +system.cpu.num_mem_refs 1677713084 # number of memory refs +system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11765161050 # Number of busy cycles +system.cpu.num_busy_cycles 11765161052 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10 # number of replacements @@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1926197 # number of replacements -system.cpu.l2cache.tagsinuse 31136.249384 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31136.249379 # Cycle average of tags in use system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 340768634000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15396.795536 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15713.812833 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy @@ -271,22 +271,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668600406 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4084.587030 # Cycle average of tags in use +system.cpu.dcache.total_refs 1668600407 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58853921000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1668600406 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1668600406 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1668600406 # number of overall hits -system.cpu.dcache.overall_hits::total 1668600406 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits +system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses @@ -303,14 +303,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1677713083 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1677713083 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1677713083 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1677713083 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses |