diff options
Diffstat (limited to 'tests/long/se/60.bzip2')
10 files changed, 162 insertions, 50 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index a81e64eec..e74f79662 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.208778 # Nu sim_ticks 1208777694500 # Number of ticks simulated final_tick 1208777694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239767 # Simulator instruction rate (inst/s) -host_op_rate 239767 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158688267 # Simulator tick rate (ticks/s) -host_mem_usage 248760 # Number of bytes of host memory used -host_seconds 7617.31 # Real time elapsed on the host +host_inst_rate 530685 # Simulator instruction rate (inst/s) +host_op_rate 530685 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 351230785 # Simulator tick rate (ticks/s) +host_mem_usage 297332 # Number of bytes of host memory used +host_seconds 3441.55 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124970112 # Number of bytes read from this memory system.physmem.bytes_read::total 125031424 # Number of bytes read from this memory @@ -293,6 +294,7 @@ system.physmem_1.memoryStateTime::REF 40363700000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 587184084000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 246097965 # Number of BP lookups system.cpu.branchPred.condPredicted 186356162 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15588061 # Number of conditional branches incorrect @@ -340,6 +342,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2417555389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -386,6 +389,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 1826378509 # Class of committed instruction system.cpu.tickCycles 2075251932 # Number of cycles that the object actually ticked system.cpu.idleCycles 342303457 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9121974 # number of replacements system.cpu.dcache.tags.tagsinuse 4080.726355 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 601538856 # Total number of references to valid blocks. @@ -403,6 +407,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1231275880 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1231275880 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 443056865 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 443056865 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158481991 # number of WriteReq hits @@ -499,6 +504,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194 system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3 # number of replacements system.cpu.icache.tags.tagsinuse 750.173547 # Cycle average of tags in use system.cpu.icache.tags.total_refs 597988654 # Total number of references to valid blocks. @@ -514,6 +520,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 874 system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1195980182 # Number of tag accesses system.cpu.icache.tags.data_accesses 1195980182 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 597988654 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 597988654 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 597988654 # number of demand (read+write) hits @@ -582,6 +589,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916 system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1920891 # number of replacements system.cpu.l2cache.tags.tagsinuse 30765.315888 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14409692 # Total number of references to valid blocks. @@ -604,6 +612,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15532 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149830076 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149830076 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3686603 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3686603 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits @@ -746,6 +755,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1268 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7239688 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4708742 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution @@ -778,6 +788,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1437000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13689105000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1173106 # Transaction distribution system.membus.trans_dist::WritebackDirty 1022139 # Transaction distribution system.membus.trans_dist::CleanEvict 897726 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 12610c445..6c06e7b34 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.669588 # Nu sim_ticks 669587683000 # Number of ticks simulated final_tick 669587683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147374 # Simulator instruction rate (inst/s) -host_op_rate 147374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56841738 # Simulator tick rate (ticks/s) -host_mem_usage 250296 # Number of bytes of host memory used -host_seconds 11779.86 # Real time elapsed on the host +host_inst_rate 268815 # Simulator instruction rate (inst/s) +host_op_rate 268815 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103681118 # Simulator tick rate (ticks/s) +host_mem_usage 297332 # Number of bytes of host memory used +host_seconds 6458.15 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125489536 # Number of bytes read from this memory system.physmem.bytes_read::total 125550272 # Number of bytes read from this memory @@ -308,6 +309,7 @@ system.physmem_1.memoryStateTime::REF 22358960000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 434911888500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 409349783 # Number of BP lookups system.cpu.branchPred.condPredicted 318159413 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15962959 # Number of conditional branches incorrect @@ -355,6 +357,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 669587683000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1339175367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -647,6 +650,7 @@ system.cpu.fp_regfile_reads 39668 # nu system.cpu.fp_regfile_writes 612 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9207202 # number of replacements system.cpu.dcache.tags.tagsinuse 4087.451175 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 712346624 # Total number of references to valid blocks. @@ -664,6 +668,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1470154674 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1470154674 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 556848448 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 556848448 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 155498172 # number of WriteReq hits @@ -780,6 +785,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 753.790798 # Cycle average of tags in use system.cpu.icache.tags.total_refs 420611422 # Total number of references to valid blocks. @@ -796,6 +802,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 882 system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 841226771 # Number of tag accesses system.cpu.icache.tags.data_accesses 841226771 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 420611422 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 420611422 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 420611422 # number of demand (read+write) hits @@ -870,6 +877,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782 system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1929018 # number of replacements system.cpu.l2cache.tags.tagsinuse 31408.626842 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14580161 # Total number of references to valid blocks. @@ -892,6 +900,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10488 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909027 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 151193610 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 151193610 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3727750 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3727750 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits @@ -1034,6 +1043,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1275 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1275 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7333042 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4752054 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution @@ -1066,6 +1076,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1423999 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13816947000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1189304 # Transaction distribution system.membus.trans_dist::WritebackDirty 1024304 # Transaction distribution system.membus.trans_dist::CleanEvict 903679 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 01aa62af6..1bae4420d 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1469307 # Simulator instruction rate (inst/s) -host_op_rate 1469307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 737317476 # Simulator tick rate (ticks/s) -host_mem_usage 238516 # Number of bytes of host memory used -host_seconds 1238.53 # Real time elapsed on the host +host_inst_rate 3169811 # Simulator instruction rate (inst/s) +host_op_rate 3169811 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1590652371 # Simulator tick rate (ticks/s) +host_mem_usage 285272 # Number of bytes of host memory used +host_seconds 574.10 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 906468506 # Wr system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 913189263000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1826378527 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution system.membus.trans_dist::WriteReq 160728502 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index e31f2fa37..d98d61e9c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.636720 # Nu sim_ticks 2636719559500 # Number of ticks simulated final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 874013 # Simulator instruction rate (inst/s) -host_op_rate 874013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1266376533 # Simulator tick rate (ticks/s) -host_mem_usage 247480 # Number of bytes of host memory used -host_seconds 2082.10 # Real time elapsed on the host +host_inst_rate 1821657 # Simulator instruction rate (inst/s) +host_op_rate 1821657 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2639438336 # Simulator tick rate (ticks/s) +host_mem_usage 295280 # Number of bytes of host memory used +host_seconds 998.97 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory @@ -36,6 +37,7 @@ system.physmem.bw_total::writebacks 24805660 # To system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,6 +72,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5273439119 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -128,6 +131,7 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9107638 # number of replacements system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. @@ -146,6 +150,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -234,6 +239,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. @@ -250,6 +256,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 730 system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -318,6 +325,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1919525 # number of replacements system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks. @@ -340,6 +348,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27302 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits @@ -482,6 +491,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution @@ -514,6 +524,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1203000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1169857 # Transaction distribution system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution system.membus.trans_dist::CleanEvict 896683 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 836b1fb8a..d91451297 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.116866 # Nu sim_ticks 1116865668500 # Number of ticks simulated final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243832 # Simulator instruction rate (inst/s) -host_op_rate 262692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 176313668 # Simulator tick rate (ticks/s) -host_mem_usage 266900 # Number of bytes of host memory used -host_seconds 6334.54 # Real time elapsed on the host +host_inst_rate 380135 # Simulator instruction rate (inst/s) +host_op_rate 409538 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 274873670 # Simulator tick rate (ticks/s) +host_mem_usage 314372 # Number of bytes of host memory used +host_seconds 4063.20 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory @@ -284,6 +285,7 @@ system.physmem_1.memoryStateTime::REF 37294400000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 239639355 # Number of BP lookups system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect @@ -298,6 +300,7 @@ system.cpu.branchPred.indirectHits 230 # Nu system.cpu.branchPred.indirectMisses 307 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -327,6 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,6 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -385,6 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -415,6 +421,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2233731337 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -461,6 +468,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 1664032481 # Class of committed instruction system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9221041 # number of replacements system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks. @@ -478,6 +486,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits @@ -598,6 +607,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 29 # number of replacements system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. @@ -614,6 +624,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 753 system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits @@ -682,6 +693,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 2013919 # number of replacements system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. @@ -704,6 +716,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits @@ -856,6 +869,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution @@ -888,6 +902,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1228500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1245432 # Transaction distribution system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution system.membus.trans_dist::CleanEvict 962724 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index d2e653fdf..bd5e79823 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.767804 # Nu sim_ticks 767803843500 # Number of ticks simulated final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 232866 # Simulator instruction rate (inst/s) -host_op_rate 250878 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115757951 # Simulator tick rate (ticks/s) -host_mem_usage 355612 # Number of bytes of host memory used -host_seconds 6632.84 # Real time elapsed on the host +host_inst_rate 232978 # Simulator instruction rate (inst/s) +host_op_rate 250999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115813638 # Simulator tick rate (ticks/s) +host_mem_usage 356264 # Number of bytes of host memory used +host_seconds 6629.65 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory @@ -298,6 +299,7 @@ system.physmem_1.memoryStateTime::REF 25638600000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 286292198 # Number of BP lookups system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect @@ -312,6 +314,7 @@ system.cpu.branchPred.indirectHits 1888 # Nu system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,6 +344,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,6 +374,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,6 +404,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -429,6 +435,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 767803843500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1535607688 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -718,6 +725,7 @@ system.cpu.cc_regfile_reads 6965778765 # nu system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes system.cpu.misc_regfile_reads 675853616 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 17003710 # number of replacements system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. @@ -733,6 +741,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits @@ -861,6 +870,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 589 # number of replacements system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. @@ -877,6 +887,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 441 system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits @@ -951,12 +962,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 4706089 # number of replacements system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks. @@ -984,6 +997,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits @@ -1169,6 +1183,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution @@ -1207,6 +1222,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1613498 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3696594 # Transaction distribution system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index cac059bf6..9d26db066 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490500 # Number of ticks simulated final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2181717 # Simulator instruction rate (inst/s) -host_op_rate 2350469 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1175236125 # Simulator tick rate (ticks/s) -host_mem_usage 301652 # Number of bytes of host memory used -host_seconds 707.96 # Real time elapsed on the host +host_inst_rate 2178318 # Simulator instruction rate (inst/s) +host_op_rate 2346807 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1173405208 # Simulator tick rate (ticks/s) +host_mem_usage 302320 # Number of bytes of host memory used +host_seconds 709.06 # Real time elapsed on the host sim_insts 1544563042 # Number of instructions simulated sim_ops 1664032434 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 750174605 # Wr system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 832017490500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1664034982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution system.membus.trans_dist::WriteReq 172586047 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index e1d79bb9d..59601069e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.377030 # Nu sim_ticks 2377029670500 # Number of ticks simulated final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1359798 # Simulator instruction rate (inst/s) -host_op_rate 1465373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2100575394 # Simulator tick rate (ticks/s) -host_mem_usage 311664 # Number of bytes of host memory used -host_seconds 1131.61 # Real time elapsed on the host +host_inst_rate 1373046 # Simulator instruction rate (inst/s) +host_op_rate 1479650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2121040557 # Simulator tick rate (ticks/s) +host_mem_usage 312336 # Number of bytes of host memory used +host_seconds 1120.69 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory @@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks 27493190 # To system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -154,6 +160,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 4754059341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9111140 # number of replacements system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. @@ -232,6 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits @@ -342,6 +351,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 7 # number of replacements system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. @@ -358,6 +368,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 606 system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits @@ -426,6 +437,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1919027 # number of replacements system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks. @@ -448,6 +460,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits @@ -594,6 +607,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution @@ -626,6 +640,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 957000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1169580 # Transaction distribution system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution system.membus.trans_dist::CleanEvict 897056 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 65376a235..3f6006735 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 786137 # Simulator instruction rate (inst/s) -host_op_rate 1224873 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 743780816 # Simulator tick rate (ticks/s) -host_mem_usage 258352 # Number of bytes of host memory used -host_seconds 3826.41 # Real time elapsed on the host +host_inst_rate 1672243 # Simulator instruction rate (inst/s) +host_op_rate 2605507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1582143797 # Simulator tick rate (ticks/s) +host_mem_usage 305608 # Number of bytes of host memory used +host_seconds 1798.83 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory @@ -35,9 +36,14 @@ system.physmem.bw_write::total 542745211 # Wr system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2846007227500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5692014456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -98,6 +104,7 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution system.membus.trans_dist::WriteReq 438528338 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index e4e1963fc..5b0c36dc3 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 5.895948 # Nu sim_ticks 5895947852500 # Number of ticks simulated final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 545612 # Simulator instruction rate (inst/s) -host_op_rate 850113 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1069419451 # Simulator tick rate (ticks/s) -host_mem_usage 268340 # Number of bytes of host memory used -host_seconds 5513.22 # Real time elapsed on the host +host_inst_rate 1001702 # Simulator instruction rate (inst/s) +host_op_rate 1560742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1963371956 # Simulator tick rate (ticks/s) +host_mem_usage 316648 # Number of bytes of host memory used +host_seconds 3002.97 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory @@ -36,9 +37,14 @@ system.physmem.bw_total::writebacks 11096858 # To system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 11791895705 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -99,6 +105,7 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9108581 # number of replacements system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. @@ -117,6 +124,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits @@ -205,6 +213,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 10 # number of replacements system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. @@ -220,6 +229,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 632 system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits @@ -288,6 +298,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1919169 # number of replacements system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks. @@ -310,6 +321,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits @@ -452,6 +464,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution @@ -484,6 +497,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1012500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1169437 # Transaction distribution system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution system.membus.trans_dist::CleanEvict 896090 # Transaction distribution |