diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index aad21c6d0..feb13ce30 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.042001 # Nu sim_ticks 42001440000 # Number of ticks simulated final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75192 # Simulator instruction rate (inst/s) -host_op_rate 75192 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34364250 # Simulator tick rate (ticks/s) -host_mem_usage 223172 # Number of bytes of host memory used -host_seconds 1222.24 # Real time elapsed on the host +host_inst_rate 134131 # Simulator instruction rate (inst/s) +host_op_rate 134131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61300636 # Simulator tick rate (ticks/s) +host_mem_usage 216520 # Number of bytes of host memory used +host_seconds 685.17 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -174,11 +174,11 @@ system.cpu.icache.demand_avg_miss_latency::total 24215.288412 system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 92000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 184 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 15333.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits @@ -270,11 +270,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 54653.714005 system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41228500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 82457 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49853.083434 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 99.706167 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks |