diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 05e39f173..fcad1aab0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.051906 # Nu sim_ticks 51905634500 # Number of ticks simulated final_tick 51905634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 261291 # Simulator instruction rate (inst/s) -host_op_rate 261291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 147573427 # Simulator tick rate (ticks/s) -host_mem_usage 252408 # Number of bytes of host memory used -host_seconds 351.73 # Real time elapsed on the host +host_inst_rate 509703 # Simulator instruction rate (inst/s) +host_op_rate 509703 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 287873591 # Simulator tick rate (ticks/s) +host_mem_usage 300976 # Number of bytes of host memory used +host_seconds 180.31 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory system.physmem.bytes_read::total 340480 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 1733160000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1011440250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 11440185 # Number of BP lookups system.cpu.branchPred.condPredicted 8207191 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765027 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 51905634500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 103811269 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -343,6 +346,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 91903089 # Class of committed instruction system.cpu.tickCycles 102098443 # Number of cycles that the object actually ticked system.cpu.idleCycles 1712826 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements system.cpu.dcache.tags.tagsinuse 1447.414267 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26572424 # Total number of references to valid blocks. @@ -361,6 +365,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 53153936 # Number of tag accesses system.cpu.dcache.tags.data_accesses 53153936 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 20074229 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20074229 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits @@ -457,6 +462,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543 system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13853 # number of replacements system.cpu.icache.tags.tagsinuse 1642.330146 # Cycle average of tags in use system.cpu.icache.tags.total_refs 22935687 # Total number of references to valid blocks. @@ -475,6 +481,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 946 system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 45918830 # Number of tag accesses system.cpu.icache.tags.data_accesses 45918830 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 22935687 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 22935687 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 22935687 # number of demand (read+write) hits @@ -543,6 +550,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269 system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2479.710860 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 26619 # Total number of references to valid blocks. @@ -565,6 +573,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2507 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111908 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 261876 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 261876 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 13853 # number of WritebackClean hits @@ -705,6 +714,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 16303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13853 # Transaction distribution @@ -737,6 +747,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 23727000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3601 # Transaction distribution system.membus.trans_dist::ReadExReq 1719 # Transaction distribution system.membus.trans_dist::ReadExResp 1719 # Transaction distribution |