diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt | 345 |
1 files changed, 181 insertions, 164 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 478ad3d97..6b0be7058 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.051523 # Nu sim_ticks 51522973500 # Number of ticks simulated final_tick 51522973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 335661 # Simulator instruction rate (inst/s) -host_op_rate 335661 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188179142 # Simulator tick rate (ticks/s) -host_mem_usage 271092 # Number of bytes of host memory used -host_seconds 273.80 # Real time elapsed on the host +host_inst_rate 356175 # Simulator instruction rate (inst/s) +host_op_rate 356175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 199679816 # Simulator tick rate (ticks/s) +host_mem_usage 295568 # Number of bytes of host memory used +host_seconds 258.03 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 389 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 970 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 349.690722 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.310004 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.842695 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 314 32.37% 32.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 200 20.62% 52.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 99 10.21% 63.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 77 7.94% 71.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 82 8.45% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 28 2.89% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 30 3.09% 85.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 24 2.47% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 116 11.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 970 # Bytes accessed per row activation -system.physmem.totQLat 35079750 # Total ticks spent queuing -system.physmem.totMemAccLat 134717250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 352.232606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.271932 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.609683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 308 31.98% 31.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 198 20.56% 52.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 99 10.28% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 77 8.00% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 83 8.62% 79.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 29 3.01% 82.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 26 2.70% 85.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 2.91% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 115 11.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 963 # Bytes accessed per row activation +system.physmem.totQLat 35638500 # Total ticks spent queuing +system.physmem.totMemAccLat 135276000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6601.38 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6706.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25351.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25456.53 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.60 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.60 # Average system read bandwidth in MiByte/s @@ -212,41 +212,49 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4339 # Number of row buffer hits during reads +system.physmem.readRowHits 4346 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.65 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 9695689.12 # Average gap between requests -system.physmem.pageHitRate 81.65 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 48460480000 # Time in different power states +system.physmem.pageHitRate 81.78 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 48467499750 # Time in different power states system.physmem.memoryStateTime::REF 1720420000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1340990000 # Time in different power states +system.physmem.memoryStateTime::ACT 1333970250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6600861 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3595 # Transaction distribution system.membus.trans_dist::ReadResp 3595 # Transaction distribution system.membus.trans_dist::ReadExReq 1719 # Transaction distribution system.membus.trans_dist::ReadExResp 1719 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10628 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 10628 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 340096 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6107000 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5314 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5314 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5314 # Request fanout histogram +system.membus.reqLayer0.occupancy 6106500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49715750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49715250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 11407320 # Number of BP lookups +system.cpu.branchPred.lookups 11407319 # Number of BP lookups system.cpu.branchPred.condPredicted 8177175 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 788662 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 6672694 # Number of BTB lookups system.cpu.branchPred.BTBHits 5348459 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 80.154417 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1172953 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 1172952 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -264,10 +272,10 @@ system.cpu.dtb.data_hits 26969994 # DT system.cpu.dtb.data_misses 47245 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 27017239 # DTB accesses -system.cpu.itb.fetch_hits 22956162 # ITB hits +system.cpu.itb.fetch_hits 22956157 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22956250 # ITB accesses +system.cpu.itb.fetch_accesses 22956245 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -286,21 +294,21 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2250216 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2250214 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.121246 # CPI: cycles per instruction system.cpu.ipc 0.891865 # IPC: instructions per cycle -system.cpu.tickCycles 100852685 # Number of cycles that the object actually ticked -system.cpu.idleCycles 2193262 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 100852672 # Number of cycles that the object actually ticked +system.cpu.idleCycles 2193275 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 13697 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.300457 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22940501 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1640.302767 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22940496 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15661 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1464.817125 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1464.816806 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.300457 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.800928 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.800928 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.302767 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800929 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800929 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id @@ -308,44 +316,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 670 system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45927985 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45927985 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22940501 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22940501 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22940501 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22940501 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22940501 # number of overall hits -system.cpu.icache.overall_hits::total 22940501 # number of overall hits +system.cpu.icache.tags.tag_accesses 45927975 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45927975 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22940496 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22940496 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22940496 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22940496 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22940496 # number of overall hits +system.cpu.icache.overall_hits::total 22940496 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15661 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15661 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15661 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15661 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15661 # number of overall misses system.cpu.icache.overall_misses::total 15661 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 385791500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 385791500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 385791500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 385791500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 385791500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 385791500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22956162 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22956162 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22956162 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22956162 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22956162 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22956162 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 386976750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 386976750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 386976750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 386976750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 386976750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 386976750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22956157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22956157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22956157 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22956157 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22956157 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22956157 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24633.899496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24633.899496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24633.899496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24633.899496 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24709.581125 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24709.581125 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24709.581125 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24709.581125 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24709.581125 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24709.581125 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -360,26 +368,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15661 system.cpu.icache.demand_mshr_misses::total 15661 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15661 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15661 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353105500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 353105500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353105500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 353105500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353105500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 353105500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 354287250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 354287250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 354287250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 354287250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 354287250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 354287250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22546.804163 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22546.804163 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22622.262308 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22622.262308 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22622.262308 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22622.262308 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22622.262308 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22622.262308 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 22356474 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 16146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 16146 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -388,25 +395,35 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31322 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 35889 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1002304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1151872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1151872 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1002304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1151872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 17998 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 17998 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 17998 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 9106000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24173500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24175250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3734250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2477.580697 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2477.584038 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12565 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3661 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.432122 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.790277 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.790419 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.793761 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075067 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.075610 # Average percentage of cache occupancy @@ -437,14 +454,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 5314 # system.cpu.l2cache.demand_misses::total 5314 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 5314 # number of overall misses system.cpu.l2cache.overall_misses::total 5314 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245013750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 245013750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 117202000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 117202000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 362215750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 362215750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 362215750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 362215750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 246128750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 246128750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 116497000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 116497000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 362625750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 362625750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 362625750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 362625750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 16146 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 16146 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) @@ -463,14 +480,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.297021 system.cpu.l2cache.demand_miss_rate::total 0.297021 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.297021 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.297021 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68154.033380 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68154.033380 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68180.337405 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68180.337405 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68162.542341 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68162.542341 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68464.186370 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68464.186370 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67770.215241 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67770.215241 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68239.697027 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68239.697027 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68239.697027 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68239.697027 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,14 +504,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 5314 system.cpu.l2cache.demand_mshr_misses::total 5314 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 5314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5314 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 199838750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199838750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95648000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95648000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295486750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 295486750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295486750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 295486750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200952250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200952250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 94943500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94943500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295895750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 295895750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295895750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 295895750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222656 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222656 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses @@ -503,22 +520,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.297021 system.cpu.l2cache.demand_mshr_miss_rate::total 0.297021 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.297021 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55587.969402 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55587.969402 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55641.652123 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55641.652123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55897.705146 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55897.705146 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55231.820826 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55231.820826 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55682.301468 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55682.301468 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55682.301468 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55682.301468 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.553115 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1448.555792 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26545428 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11903.779372 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.553115 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.555792 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.353651 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353651 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id @@ -546,14 +563,14 @@ system.cpu.dcache.demand_misses::cpu.inst 3430 # n system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36876750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36876750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 198611000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 198611000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 235487750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235487750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 235487750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235487750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37054000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37054000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 196991000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 196991000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 234045000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 234045000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 234045000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 234045000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 20047755 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20047755 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) @@ -570,14 +587,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71053.468208 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71053.468208 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68227.756785 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68227.756785 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68655.320700 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68655.320700 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71394.990366 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71394.990366 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67671.246994 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67671.246994 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68234.693878 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68234.693878 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68234.693878 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68234.693878 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -604,14 +621,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33572250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33572250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 119207500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 119207500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152779750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 152779750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152779750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 152779750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 118502500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 118502500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152008500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 152008500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152008500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 152008500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses @@ -620,14 +637,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69221.134021 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69221.134021 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68313.753582 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68313.753582 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69084.536082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69084.536082 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67909.742120 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67909.742120 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68165.246637 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68165.246637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68165.246637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68165.246637 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |