diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt | 992 |
1 files changed, 496 insertions, 496 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 98d3f1024..2c6817645 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,479 +1,43 @@ ---------- Begin Simulation Statistics ---------- -final_tick 51810521500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 191326 # Simulator instruction rate (inst/s) -host_mem_usage 251752 # Number of bytes of host memory used -host_op_rate 191326 # Simulator op (including micro ops) rate (op/s) -host_seconds 480.35 # Real time elapsed on the host -host_tick_rate 107860315 # Simulator tick rate (ticks/s) +sim_seconds 0.051523 # Number of seconds simulated +sim_ticks 51522973500 # Number of ticks simulated +final_tick 51522973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 192794 # Simulator instruction rate (inst/s) +host_op_rate 192794 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108084557 # Simulator tick rate (ticks/s) +host_mem_usage 244692 # Number of bytes of host memory used +host_seconds 476.69 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated -sim_seconds 0.051811 # Number of seconds simulated -sim_ticks 51810521500 # Number of ticks simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.960972 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 5346983 # Number of BTB hits -system.cpu.branchPred.BTBLookups 6686991 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 788623 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 8172556 # Number of conditional branches predicted -system.cpu.branchPred.lookups 11403069 # Number of BP lookups -system.cpu.branchPred.usedRAS 1173096 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 91903089 # Number of instructions committed -system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.cpi 1.127503 # CPI: cycles per instruction -system.cpu.dcache.ReadReq_accesses::cpu.inst 20044127 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20044127 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 69928.365385 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69928.365385 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 68014.432990 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68014.432990 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 20043607 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20043607 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36362750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36362750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 520 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 520 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 32987000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32987000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 485 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67476.975945 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67476.975945 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68165.329513 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68165.329513 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 6498193 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498193 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 196358000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 196358000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 2910 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2910 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1165 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1165 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 118948500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 118948500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1745 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 26545230 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26545230 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67848.615160 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67848.615160 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68132.511211 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68132.511211 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 26541800 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26541800 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 232720750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 232720750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 3430 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151935500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151935500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 26545230 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26545230 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67848.615160 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67848.615160 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68132.511211 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68132.511211 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 26541800 # number of overall hits -system.cpu.dcache.overall_hits::total 26541800 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 232720750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 232720750 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses -system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 1200 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151935500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151935500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 11902.152466 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 53092690 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.584633 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.353658 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353658 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 53092690 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 1448.584633 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26541800 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.discardedOps 2238069 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dtb.data_accesses 27017530 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 26970236 # DTB hits -system.cpu.dtb.data_misses 47294 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 20437728 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 20390711 # DTB read hits -system.cpu.dtb.read_misses 47017 # DTB read misses -system.cpu.dtb.write_accesses 6579802 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 6579525 # DTB write hits -system.cpu.dtb.write_misses 277 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 22978908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22978908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24673.484027 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24673.484027 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22586.223937 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22586.223937 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 22963225 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22963225 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 386954250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 386954250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 15683 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15683 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 354219750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 354219750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15683 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15683 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 22978908 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22978908 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24673.484027 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24673.484027 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22586.223937 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22586.223937 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 22963225 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22963225 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 386954250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 386954250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 15683 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15683 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 354219750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 354219750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 15683 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15683 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 22978908 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22978908 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24673.484027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24673.484027 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22586.223937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22586.223937 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 22963225 # number of overall hits -system.cpu.icache.overall_hits::total 22963225 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 386954250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 386954250 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 15683 # number of overall misses -system.cpu.icache.overall_misses::total 15683 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 354219750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 354219750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 15683 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15683 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 668 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 1464.211248 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 45973499 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.514711 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801521 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801521 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 13718 # number of replacements -system.cpu.icache.tags.sampled_refs 15683 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 45973499 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1641.514711 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22963225 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 2226173 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.886915 # IPC: instructions per cycle -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 22978996 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 22978908 # ITB hits -system.cpu.itb.fetch_misses 88 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68029.959279 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68029.959279 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55498.836533 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55498.836533 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 116943500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 116943500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.985100 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 1719 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95402500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95402500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1719 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16168 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 16168 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68200.931332 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68200.931332 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55638.518210 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55638.518210 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 12571 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 12571 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245318750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 245318750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.222476 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.222476 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3597 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200131750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200131750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222476 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222476 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3597 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 17913 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17913 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68145.645222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68145.645222 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55593.350263 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55593.350263 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 12597 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 12597 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 362262250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 362262250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.296768 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.296768 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 5316 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5316 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295534250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 295534250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296768 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.296768 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5316 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5316 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 17913 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17913 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68145.645222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68145.645222 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55593.350263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55593.350263 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 12597 # number of overall hits -system.cpu.l2cache.overall_hits::total 12597 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 362262250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 362262250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.296768 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.296768 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 5316 # number of overall misses -system.cpu.l2cache.overall_misses::total 5316 # number of overall misses -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295534250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 295534250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296768 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.296768 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5316 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5316 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 767 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2506 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 3.435708 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 149568 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 17.784221 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.008081 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075135 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.075677 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3663 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 3663 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 149568 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 2479.792302 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 12585 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 103621043 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 101394870 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 1153280 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31366 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 35933 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 9117000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24208750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3732500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 22259571 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1003712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1153280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 16168 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 16168 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 340224 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10632 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 6066000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49708250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 6566697 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340224 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 340224 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 3597 # Transaction distribution -system.membus.trans_dist::ReadResp 3597 # Transaction distribution -system.membus.trans_dist::ReadExReq 1719 # Transaction distribution -system.membus.trans_dist::ReadExResp 1719 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 9746132.43 # Average gap between requests -system.physmem.avgMemAccLat 25349.60 # Average memory access latency per DRAM burst -system.physmem.avgQLat 6599.60 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 6.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.57 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 3909631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3909631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 6566697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6566697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6566697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6566697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 980 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 346.710204 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 212.810529 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.902824 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 318 32.45% 32.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 196 20.00% 52.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 101 10.31% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 95 9.69% 72.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 76 7.76% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 3.78% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 22 2.24% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 2.14% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 114 11.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 980 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 340224 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 340224 # Total read bytes from the system interface side +system.physmem.bytes_read::cpu.inst 340096 # Number of bytes read from this memory +system.physmem.bytes_read::total 340096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202432 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 5314 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5314 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 6600861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6600861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3928966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3928966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6600861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6600861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5314 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5314 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 340096 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 340096 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 202560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202560 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 340224 # Number of bytes read from this memory -system.physmem.bytes_read::total 340224 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 48729835000 # Time in different power states -system.physmem.memoryStateTime::REF 1730040000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1350106250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 5316 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5316 # Number of read requests responded to by this memory -system.physmem.pageHitRate 81.55 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 469 # Per bank write bursts +system.physmem.perBankRdBursts::0 468 # Per bank write bursts system.physmem.perBankRdBursts::1 295 # Per bank write bursts system.physmem.perBankRdBursts::2 307 # Per bank write bursts system.physmem.perBankRdBursts::3 523 # Per bank write bursts @@ -485,7 +49,7 @@ system.physmem.perBankRdBursts::8 251 # Pe system.physmem.perBankRdBursts::9 282 # Per bank write bursts system.physmem.perBankRdBursts::10 255 # Per bank write bursts system.physmem.perBankRdBursts::11 260 # Per bank write bursts -system.physmem.perBankRdBursts::12 409 # Per bank write bursts +system.physmem.perBankRdBursts::12 408 # Per bank write bursts system.physmem.perBankRdBursts::13 344 # Per bank write bursts system.physmem.perBankRdBursts::14 500 # Per bank write bursts system.physmem.perBankRdBursts::15 448 # Per bank write bursts @@ -505,9 +69,26 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 4911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 51522892000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5314 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4908 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -537,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 5316 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5316 # Read request sizes (log2) -system.physmem.readReqs 5316 # Number of read requests accepted -system.physmem.readRowHitRate 81.55 # Row buffer hit rate for reads -system.physmem.readRowHits 4335 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 26580000 # Total ticks spent in databus transfers -system.physmem.totGap 51810440000 # Total gap between requests -system.physmem.totMemAccLat 134758500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 35083500 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -617,17 +182,452 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 970 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 349.690722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.310004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.842695 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 314 32.37% 32.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 200 20.62% 52.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 99 10.21% 63.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 77 7.94% 71.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 82 8.45% 79.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 28 2.89% 82.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 3.09% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 24 2.47% 88.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 116 11.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 970 # Bytes accessed per row activation +system.physmem.totQLat 35128750 # Total ticks spent queuing +system.physmem.totMemAccLat 134766250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6610.60 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25360.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.60 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.60 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4339 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 81.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 9695689.12 # Average gap between requests +system.physmem.pageHitRate 81.65 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 48460398500 # Time in different power states +system.physmem.memoryStateTime::REF 1720420000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1341071500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 6600861 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3595 # Transaction distribution +system.membus.trans_dist::ReadResp 3595 # Transaction distribution +system.membus.trans_dist::ReadExReq 1719 # Transaction distribution +system.membus.trans_dist::ReadExResp 1719 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10628 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10628 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 340096 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 6106000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 49717250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 11407310 # Number of BP lookups +system.cpu.branchPred.condPredicted 8177170 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 788660 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6672659 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5348436 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 80.154493 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1172954 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 20390002 # DTB read hits +system.cpu.dtb.read_misses 46972 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 20436974 # DTB read accesses +system.cpu.dtb.write_hits 6579989 # DTB write hits +system.cpu.dtb.write_misses 273 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 6580262 # DTB write accesses +system.cpu.dtb.data_hits 26969991 # DTB hits +system.cpu.dtb.data_misses 47245 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 27017236 # DTB accesses +system.cpu.itb.fetch_hits 22956123 # ITB hits +system.cpu.itb.fetch_misses 88 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 22956211 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 103045947 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 91903089 # Number of instructions committed +system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2250201 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.121246 # CPI: cycles per instruction +system.cpu.ipc 0.891865 # IPC: instructions per cycle +system.cpu.tickCycles 100852498 # Number of cycles that the object actually ticked +system.cpu.idleCycles 2193449 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 13697 # number of replacements +system.cpu.icache.tags.tagsinuse 1640.300459 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22940462 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15661 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1464.814635 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.300459 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800928 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800928 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 670 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45927907 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45927907 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22940462 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22940462 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22940462 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22940462 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22940462 # number of overall hits +system.cpu.icache.overall_hits::total 22940462 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15661 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15661 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15661 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15661 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15661 # number of overall misses +system.cpu.icache.overall_misses::total 15661 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 385817000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 385817000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 385817000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 385817000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 385817000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 385817000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22956123 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22956123 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22956123 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22956123 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22956123 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22956123 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24635.527744 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24635.527744 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24635.527744 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24635.527744 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24635.527744 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24635.527744 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15661 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15661 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15661 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15661 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15661 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15661 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353131000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 353131000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353131000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 353131000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353131000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 353131000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22548.432412 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22548.432412 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22548.432412 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22548.432412 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22548.432412 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22548.432412 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 22356474 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 16146 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 16146 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31322 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 35889 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1002304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1151872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1151872 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 9106000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 24173500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3734250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2477.580709 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 12565 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3661 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.432122 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.790278 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.790431 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075067 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.075610 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3661 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 181 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2504 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111725 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 149390 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149390 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 12551 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 12551 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12577 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 12577 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12577 # number of overall hits +system.cpu.l2cache.overall_hits::total 12577 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3595 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3595 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 1719 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 5314 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5314 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 5314 # number of overall misses +system.cpu.l2cache.overall_misses::total 5314 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245039250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 245039250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 117228000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 117228000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 362267250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 362267250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 362267250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 362267250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 16146 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 16146 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 17891 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17891 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 17891 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17891 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.222656 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.222656 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.985100 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.297021 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.297021 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.297021 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.297021 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68161.126565 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.126565 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68195.462478 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68195.462478 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68172.233722 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68172.233722 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68172.233722 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68172.233722 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3595 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3595 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1719 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5314 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5314 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 199861250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199861250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95675500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95675500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295536750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 295536750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295536750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 295536750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222656 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222656 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.297021 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297021 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55594.228095 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55594.228095 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55657.649796 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55657.649796 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55614.744072 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55614.744072 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55614.744072 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55614.744072 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1448.553123 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26545427 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11903.778924 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.553123 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.353651 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353651 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 53099944 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53099944 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 20047235 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20047235 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 6498192 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 26545427 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26545427 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 26545427 # number of overall hits +system.cpu.dcache.overall_hits::total 26545427 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2911 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2911 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 3430 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses +system.cpu.dcache.overall_misses::total 3430 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36876750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36876750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 198662500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 198662500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 235539250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235539250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 235539250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235539250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 20047754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20047754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 26548857 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26548857 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 26548857 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26548857 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71053.468208 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71053.468208 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68245.448300 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68245.448300 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68670.335277 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68670.335277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68670.335277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68670.335277 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 34 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 34 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1166 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1166 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 1200 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 1200 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 485 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1745 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33572250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33572250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 119233500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 119233500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152805750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 152805750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152805750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 152805750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69221.134021 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69221.134021 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68328.653295 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68328.653295 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68522.757848 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68522.757848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68522.757848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68522.757848 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |