diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/minor-timing')
3 files changed, 315 insertions, 294 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini index 5e0a983c6..35828777f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout index 9e68a8154..4b089cf00 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout @@ -3,11 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4311 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:43 +gem5 executing on e108600-lin, pid 28042 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/minor-timing +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -24,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 53344764500 because target called exit() +122 123 124 Exiting @ tick 53437621500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index d3e370d8a..2c8dfca63 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.053349 # Number of seconds simulated -sim_ticks 53349450500 # Number of ticks simulated -final_tick 53349450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.053438 # Number of seconds simulated +sim_ticks 53437621500 # Number of ticks simulated +final_tick 53437621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 273465 # Simulator instruction rate (inst/s) -host_op_rate 273465 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158745564 # Simulator tick rate (ticks/s) -host_mem_usage 258296 # Number of bytes of host memory used -host_seconds 336.07 # Real time elapsed on the host +host_inst_rate 247892 # Simulator instruction rate (inst/s) +host_op_rate 247892 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 144138078 # Simulator tick rate (ticks/s) +host_mem_usage 256712 # Number of bytes of host memory used +host_seconds 370.74 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory system.physmem.bytes_read::total 340608 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 202880 # Nu system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3802851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6384471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3802851 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3802851 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3802851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2581620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6384471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3796576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2577360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6373936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3796576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3796576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3796576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2577360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6373936 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5322 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 53349362500 # Total gap between requests +system.physmem.totGap 53437285500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4860 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 449 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 345.743381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.338865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.606559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 303 30.86% 30.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 220 22.40% 53.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94 9.57% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 105 10.69% 73.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 62 6.31% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 3.67% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 2.95% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 22 2.24% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 111 11.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation -system.physmem.totQLat 40016750 # Total ticks spent queuing -system.physmem.totMemAccLat 139804250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 347.009174 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.710292 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.985210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 311 31.70% 31.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 198 20.18% 51.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 103 10.50% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 115 11.72% 74.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 57 5.81% 79.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 30 3.06% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 3.06% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 2.65% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 111 11.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 981 # Bytes accessed per row activation +system.physmem.totQLat 132267250 # Total ticks spent queuing +system.physmem.totMemAccLat 232054750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7519.12 # Average queueing delay per DRAM burst +system.physmem.avgQLat 24852.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26269.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 43602.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.38 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -217,49 +217,59 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4333 # Number of row buffer hits during reads +system.physmem.readRowHits 4338 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10024307.12 # Average gap between requests -system.physmem.pageHitRate 81.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3462480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1889250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 10040827.79 # Average gap between requests +system.physmem.pageHitRate 81.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3348660 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1772265 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18335520 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1795262310 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30431523750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 35736125550 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.920144 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 50622338000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1781260000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 940274500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3923640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2140875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21247200 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 173328480.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64638000 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9138240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 468346770 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 218747040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12435217200 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 13392872175 # Total energy per rank (pJ) +system.physmem_0.averagePower 250.626273 # Core power per rank (mW) +system.physmem_0.totalIdleTime 53271099000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 16953500 # Time in different power states +system.physmem_0.memoryStateTime::REF 73680000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51675337000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 569631000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 74922500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1027097500 # Time in different power states +system.physmem_1.actEnergy 3677100 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1950630 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19663560 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1822659075 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 30407483250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 35741598600 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.022916 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 50582866250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1781260000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 980601250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11450641 # Number of BP lookups -system.cpu.branchPred.condPredicted 8210938 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 765018 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6085190 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5320739 # Number of BTB hits +system.physmem_1.refreshEnergy 191767680.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68393160 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 9924480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 510653310 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 251520000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12393371550 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 13451137230 # Total energy per rank (pJ) +system.physmem_1.averagePower 251.716611 # Core power per rank (mW) +system.physmem_1.totalIdleTime 53261175500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 18732000 # Time in different power states +system.physmem_1.memoryStateTime::REF 81534000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51486455000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 654968250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 76126500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1119805750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 11450652 # Number of BP lookups +system.cpu.branchPred.condPredicted 8210942 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765019 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6085116 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5320742 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.437516 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176674 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.438629 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1176677 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits. @@ -282,10 +292,10 @@ system.cpu.dtb.data_hits 26995130 # DT system.cpu.dtb.data_misses 43659 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 27038789 # DTB accesses -system.cpu.itb.fetch_hits 22968614 # ITB hits +system.cpu.itb.fetch_hits 22968644 # ITB hits system.cpu.itb.fetch_misses 90 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22968704 # ITB accesses +system.cpu.itb.fetch_accesses 22968734 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +309,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53349450500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 106698901 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 53437621500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 106875243 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2191321 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2191333 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.160994 # CPI: cycles per instruction -system.cpu.ipc 0.861331 # IPC: instructions per cycle +system.cpu.cpi 1.162912 # CPI: cycles per instruction +system.cpu.ipc 0.859910 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction @@ -344,76 +354,76 @@ system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91903089 # Class of committed instruction -system.cpu.tickCycles 103791781 # Number of cycles that the object actually ticked -system.cpu.idleCycles 2907120 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 103792204 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3083039 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.584590 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26572201 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1447.203649 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26572187 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11910.444195 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11910.437920 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584590 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353414 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353414 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.203649 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353321 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353321 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53153439 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53153439 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20074005 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20074005 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498196 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498196 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26572201 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26572201 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26572201 # number of overall hits -system.cpu.dcache.overall_hits::total 26572201 # number of overall hits +system.cpu.dcache.tags.tag_accesses 53153435 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53153435 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20074003 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20074003 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498184 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498184 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26572187 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26572187 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26572187 # number of overall hits +system.cpu.dcache.overall_hits::total 26572187 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2907 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2907 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3403 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3403 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3403 # number of overall misses -system.cpu.dcache.overall_misses::total 3403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37687000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37687000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 223750000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 223750000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 261437000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 261437000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 261437000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 261437000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20074501 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20074501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 2919 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2919 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3415 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3415 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3415 # number of overall misses +system.cpu.dcache.overall_misses::total 3415 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58822000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58822000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 274731500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 274731500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 333553500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 333553500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 333553500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 333553500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20074499 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20074499 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26575604 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26575604 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26575604 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26575604 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26575602 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26575602 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26575602 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26575602 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75981.854839 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75981.854839 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76969.384245 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76969.384245 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76825.448134 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76825.448134 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000449 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000449 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 118592.741935 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 118592.741935 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94118.362453 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 94118.362453 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 97673.060029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 97673.060029 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +434,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1164 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1164 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1172 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1172 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1172 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1172 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1176 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1176 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1184 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1184 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1184 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1184 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses @@ -438,14 +448,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2231 system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36777500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36777500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 140150000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 140150000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176927500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 176927500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176927500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 176927500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 57888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 57888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 165966000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 165966000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 223854500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 223854500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 223854500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 223854500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -454,70 +464,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75363.729508 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75363.729508 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80407.343660 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80407.343660 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 118623.975410 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 118623.975410 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95218.588640 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95218.588640 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13865 # number of replacements -system.cpu.icache.tags.tagsinuse 1642.701416 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22952783 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1642.239495 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22952813 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1449.954706 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1449.956601 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1642.701416 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.802100 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.802100 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1642.239495 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801875 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801875 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 670 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45953058 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45953058 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22952783 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22952783 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22952783 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22952783 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22952783 # number of overall hits -system.cpu.icache.overall_hits::total 22952783 # number of overall hits +system.cpu.icache.tags.tag_accesses 45953118 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45953118 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22952813 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22952813 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22952813 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22952813 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22952813 # number of overall hits +system.cpu.icache.overall_hits::total 22952813 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses system.cpu.icache.overall_misses::total 15831 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 411111000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 411111000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 411111000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 411111000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 411111000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 411111000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22968614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22968614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22968614 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22968614 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22968614 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22968614 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 456439000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 456439000 # 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miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25968.732234 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25968.732234 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25968.732234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25968.732234 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28831.975238 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28831.975238 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28831.975238 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28831.975238 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,46 +542,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15831 system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 395281000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 395281000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 395281000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 395281000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 395281000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 395281000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 440609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 440609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 440609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 440609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440609000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 440609000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24968.795401 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24968.795401 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27832.038406 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27832.038406 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3575.444447 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3574.446973 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.450993 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.993454 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064162 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.044952 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.109114 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.836656 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.610316 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064143 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.044941 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.109083 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits @@ -600,18 +610,18 @@ system.cpu.l2cache.demand_misses::total 5322 # nu system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses system.cpu.l2cache.overall_misses::total 5322 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 137262000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 137262000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 238604500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 238604500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35483000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 35483000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 238604500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 172745000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 411349500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 238604500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 172745000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 411349500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163078000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 163078000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 283932500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 283932500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 56594000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 56594000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 283932500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 219672000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 503604500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 283932500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 219672000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 503604500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses) @@ -640,18 +650,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.294668 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79942.923704 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79942.923704 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75269.558360 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75269.558360 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81570.114943 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81570.114943 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77292.277339 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77292.277339 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94978.450786 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94978.450786 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89568.611987 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89568.611987 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 130101.149425 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 130101.149425 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94626.925968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94626.925968 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,18 +680,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5322 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120092000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120092000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 206904500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 206904500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31133000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31133000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206904500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151225000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 358129500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206904500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151225000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 358129500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 145908000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 145908000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252232500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252232500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 52244000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 52244000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252232500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 198152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 450384500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252232500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 198152000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 450384500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses @@ -694,25 +704,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69942.923704 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69942.923704 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65269.558360 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65269.558360 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71570.114943 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71570.114943 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84978.450786 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84978.450786 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79568.611987 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79568.611987 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 120101.149425 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 120101.149425 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution @@ -752,7 +762,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3605 # Transaction distribution system.membus.trans_dist::ReadExReq 1717 # Transaction distribution system.membus.trans_dist::ReadExResp 1717 # Transaction distribution @@ -773,9 +783,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5322 # Request fanout histogram -system.membus.reqLayer0.occupancy 6421000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6424500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28180500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28175000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |