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-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt1044
1 files changed, 524 insertions, 520 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 002e3eec9..720778178 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.021909 # Number of seconds simulated
-sim_ticks 21909208500 # Number of ticks simulated
-final_tick 21909208500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.021906 # Number of seconds simulated
+sim_ticks 21906070500 # Number of ticks simulated
+final_tick 21906070500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 183723 # Simulator instruction rate (inst/s)
-host_op_rate 183723 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47816944 # Simulator tick rate (ticks/s)
-host_mem_usage 254944 # Number of bytes of host memory used
-host_seconds 458.19 # Real time elapsed on the host
+host_inst_rate 201237 # Simulator instruction rate (inst/s)
+host_op_rate 201237 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 52367931 # Simulator tick rate (ticks/s)
+host_mem_usage 260088 # Number of bytes of host memory used
+host_seconds 418.31 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory
system.physmem.bytes_read::total 334528 # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 195968 # Nu
system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 8944550 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 6324281 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15268831 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 8944550 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 8944550 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 8944550 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 6324281 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 15268831 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 8945831 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 6325187 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15271018 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 8945831 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 8945831 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 8945831 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 6325187 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 15271018 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 5227 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue
@@ -43,7 +43,7 @@ system.physmem.servicedByWrQ 0 # Nu
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 470 # Per bank write bursts
-system.physmem.perBankRdBursts::1 291 # Per bank write bursts
+system.physmem.perBankRdBursts::1 292 # Per bank write bursts
system.physmem.perBankRdBursts::2 302 # Per bank write bursts
system.physmem.perBankRdBursts::3 523 # Per bank write bursts
system.physmem.perBankRdBursts::4 220 # Per bank write bursts
@@ -55,7 +55,7 @@ system.physmem.perBankRdBursts::9 278 # Pe
system.physmem.perBankRdBursts::10 249 # Per bank write bursts
system.physmem.perBankRdBursts::11 251 # Per bank write bursts
system.physmem.perBankRdBursts::12 395 # Per bank write bursts
-system.physmem.perBankRdBursts::13 339 # Per bank write bursts
+system.physmem.perBankRdBursts::13 338 # Per bank write bursts
system.physmem.perBankRdBursts::14 492 # Per bank write bursts
system.physmem.perBankRdBursts::15 449 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 21909113500 # Total gap between requests
+system.physmem.totGap 21905974500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 3269 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 232 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 3276 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1193 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 227 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 857 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 387.435239 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 233.348968 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 357.138574 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 246 28.70% 28.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 186 21.70% 50.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 85 9.92% 60.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 65 7.58% 67.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 37 4.32% 72.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 35 4.08% 76.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 34 3.97% 80.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 49 5.72% 86.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 120 14.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 857 # Bytes accessed per row activation
-system.physmem.totQLat 42496500 # Total ticks spent queuing
-system.physmem.totMemAccLat 140502750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 862 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 385.707657 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 229.399691 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 360.883028 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 260 30.16% 30.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 179 20.77% 50.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 93 10.79% 61.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 57 6.61% 68.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 30 3.48% 71.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 37 4.29% 76.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 31 3.60% 79.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 50 5.80% 85.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 125 14.50% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 862 # Bytes accessed per row activation
+system.physmem.totQLat 40339750 # Total ticks spent queuing
+system.physmem.totMemAccLat 138346000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8130.19 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 7717.57 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26880.19 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 26467.57 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 15.27 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 15.27 # Average system read bandwidth in MiByte/s
@@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.12 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 4359 # Number of row buffer hits during reads
+system.physmem.readRowHits 4357 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.39 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 4191527.36 # Average gap between requests
-system.physmem.pageHitRate 83.39 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3076920 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1678875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 19468800 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 4190926.82 # Average gap between requests
+system.physmem.pageHitRate 83.36 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3129840 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1707750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 19570200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 930163050 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 12325856250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 14710823175 # Total energy per rank (pJ)
-system.physmem_0.averagePower 671.635656 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 20502630500 # Time in different power states
+system.physmem_0.actBackEnergy 905463810 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 12347522250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 14707973130 # Total energy per rank (pJ)
+system.physmem_0.averagePower 671.505534 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 20538678250 # Time in different power states
system.physmem_0.memoryStateTime::REF 731380000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 668984500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 632936750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 20771400 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 3333960 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1819125 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 20779200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 904676355 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 12348213000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 14709404805 # Total energy per rank (pJ)
-system.physmem_1.averagePower 671.570899 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 20540502500 # Time in different power states
+system.physmem_1.actBackEnergy 902236185 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 12350353500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 14709101250 # Total energy per rank (pJ)
+system.physmem_1.averagePower 671.557040 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 20543762750 # Time in different power states
system.physmem_1.memoryStateTime::REF 731380000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 632027000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 628284250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 16102191 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11688099 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 930994 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8963309 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7508263 # Number of BTB hits
+system.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 16102243 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11688063 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 931000 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 8962915 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7507921 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 83.766642 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1594548 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 465 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 29370 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 3646 # Number of indirect misses.
+system.cpu.branchPred.BTBHitPct 83.766509 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1594308 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 466 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 29379 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 25730 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 3649 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 24064579 # DTB read hits
-system.cpu.dtb.read_misses 206327 # DTB read misses
-system.cpu.dtb.read_acv 4 # DTB read access violations
-system.cpu.dtb.read_accesses 24270906 # DTB read accesses
-system.cpu.dtb.write_hits 7168860 # DTB write hits
-system.cpu.dtb.write_misses 1193 # DTB write misses
+system.cpu.dtb.read_hits 24059471 # DTB read hits
+system.cpu.dtb.read_misses 206747 # DTB read misses
+system.cpu.dtb.read_acv 6 # DTB read access violations
+system.cpu.dtb.read_accesses 24266218 # DTB read accesses
+system.cpu.dtb.write_hits 7167964 # DTB write hits
+system.cpu.dtb.write_misses 1190 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 7170053 # DTB write accesses
-system.cpu.dtb.data_hits 31233439 # DTB hits
-system.cpu.dtb.data_misses 207520 # DTB misses
-system.cpu.dtb.data_acv 4 # DTB access violations
-system.cpu.dtb.data_accesses 31440959 # DTB accesses
-system.cpu.itb.fetch_hits 15932703 # ITB hits
+system.cpu.dtb.write_accesses 7169154 # DTB write accesses
+system.cpu.dtb.data_hits 31227435 # DTB hits
+system.cpu.dtb.data_misses 207937 # DTB misses
+system.cpu.dtb.data_acv 6 # DTB access violations
+system.cpu.dtb.data_accesses 31435372 # DTB accesses
+system.cpu.itb.fetch_hits 15930202 # ITB hits
system.cpu.itb.fetch_misses 79 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 15932782 # ITB accesses
+system.cpu.itb.fetch_accesses 15930281 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -299,140 +299,140 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 21909208500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 43818418 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 21906070500 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 43812142 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 16643559 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 137979359 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16102191 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9128535 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 25956071 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1939868 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2614 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 15932703 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 367699 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 43572351 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.166672 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.433625 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 16640800 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 137955116 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16102243 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9127959 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 25951378 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1939862 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2284 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 15930202 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 367997 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 43564561 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.166682 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.433652 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 19392056 44.51% 44.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2618542 6.01% 50.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1330036 3.05% 53.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1934112 4.44% 58.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 3001913 6.89% 64.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1292242 2.97% 67.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1355704 3.11% 70.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 886645 2.03% 73.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 11761101 26.99% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 19388904 44.51% 44.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2617971 6.01% 50.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1329653 3.05% 53.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1933242 4.44% 58.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 3001866 6.89% 64.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1292154 2.97% 67.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1355153 3.11% 70.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 885983 2.03% 73.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 11759635 26.99% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 43572351 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.367475 # Number of branch fetches per cycle
-system.cpu.fetch.rate 3.148890 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 12867028 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 8206518 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19434084 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 2106116 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 958605 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2654233 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 11853 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 132149690 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 49712 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 958605 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13986113 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4641138 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 10397 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 20305818 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 3670280 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 128777120 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 70822 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2026790 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 1359443 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 54939 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 94599417 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 167333836 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 159779688 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 7554147 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 43564561 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.367529 # Number of branch fetches per cycle
+system.cpu.fetch.rate 3.148787 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 12866207 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 8201064 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19435677 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 2103016 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 958597 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2653560 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 11864 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 132121785 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 49799 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 958597 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 13983011 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4637206 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 10599 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 20305280 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 3669868 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 128752916 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 70736 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2012785 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 1367413 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 56554 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 94580122 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 167299448 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 159747069 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 7552378 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 26172056 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 950 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 8271760 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 26904379 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 8704430 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3459754 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1614105 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 111855372 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1919 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 99762873 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 119457 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 27677581 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 21095041 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1530 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 43572351 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.289591 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.099378 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 26152761 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 954 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 949 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 8254781 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 26901517 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 8704631 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 3463893 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1634991 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 111837286 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1924 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 99746434 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 118591 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 27659500 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 21091403 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1535 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 43564561 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.289623 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.099110 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 11226739 25.77% 25.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 7658694 17.58% 43.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7470474 17.14% 60.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5702469 13.09% 73.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4463101 10.24% 83.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2983064 6.85% 90.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2041659 4.69% 95.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1171062 2.69% 98.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 855089 1.96% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 11223672 25.76% 25.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 7655343 17.57% 43.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7467756 17.14% 60.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5704970 13.10% 73.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4467403 10.25% 83.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2981246 6.84% 90.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2039535 4.68% 95.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1169471 2.68% 98.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 855165 1.96% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 43572351 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 43564561 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 483998 20.16% 20.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 481664 20.16% 20.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 20.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 20.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 522 0.02% 20.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 34928 1.45% 21.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 12187 0.51% 22.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 1012495 42.17% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 694978 28.95% 93.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 161680 6.73% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 34768 1.46% 21.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 12121 0.51% 22.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 1011551 42.34% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 688710 28.83% 93.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 159620 6.68% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 60663003 60.81% 60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 60652801 60.81% 60.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 489881 0.49% 61.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2847512 2.85% 64.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 2443315 2.45% 66.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 314199 0.31% 67.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2847832 2.86% 64.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 115342 0.12% 64.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 2442782 2.45% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 314177 0.31% 67.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 766025 0.77% 67.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued
@@ -454,82 +454,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 24854808 24.91% 92.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 7268585 7.29% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 24850091 24.91% 92.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 7267177 7.29% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 99762873 # Type of FU issued
-system.cpu.iq.rate 2.276734 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2400804 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.024065 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 229929463 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 129921880 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 89757813 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 15688895 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 9653551 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 7189472 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 93781732 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 8381938 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1923340 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 99746434 # Type of FU issued
+system.cpu.iq.rate 2.276685 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2388956 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.023950 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 229877287 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 129889935 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 89741335 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 15687689 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 9649325 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 7189295 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 93754597 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 8380786 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1921314 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 6908181 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 11335 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 40937 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2203327 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 6905319 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 11494 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 40918 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2203528 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 42874 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1494 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 42875 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 958605 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 3611196 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 465334 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 122779718 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 241439 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 26904379 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 8704430 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1919 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 38387 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 421097 # Number of times the LSQ has become full, causing a stall
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-system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 502390 # Number of branches that were predicted not taken incorrectly
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+system.cpu.iew.iewUnblockCycles 461685 # Number of cycles IEW is unblocking
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system.cpu.iew.exec_swp 0 # number of swp insts executed
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-system.cpu.iew.exec_rate 2.246483 # Inst execution rate
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-system.cpu.iew.wb_count 96947285 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 66976790 # num instructions producing a value
-system.cpu.iew.wb_consumers 94960923 # num instructions consuming a value
-system.cpu.iew.wb_rate 2.212478 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.705309 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 30878414 # The number of squashed insts skipped by commit
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+system.cpu.iew.wb_fanout 0.705299 # average fanout of values written-back
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system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 919665 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 39078577 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.351750 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.919984 # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::mean 2.352076 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.920100 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 14680368 37.57% 37.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 8532696 21.83% 59.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3879932 9.93% 69.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 1909819 4.89% 74.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1376650 3.52% 77.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1035169 2.65% 80.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 692226 1.77% 82.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 728499 1.86% 84.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6243218 15.98% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 14677251 37.56% 37.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 8528323 21.83% 59.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3880033 9.93% 69.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 1914323 4.90% 74.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1374739 3.52% 77.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1034073 2.65% 80.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 692942 1.77% 82.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 727068 1.86% 84.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6244406 15.98% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 39078577 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 39073158 # Number of insts commited each cycle
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -575,118 +575,118 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction
-system.cpu.commit.bw_lim_events 6243218 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 155615788 # The number of ROB reads
-system.cpu.rob.rob_writes 250112160 # The number of ROB writes
-system.cpu.timesIdled 4756 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 246067 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 6244406 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 155587477 # The number of ROB reads
+system.cpu.rob.rob_writes 250066312 # The number of ROB writes
+system.cpu.timesIdled 4758 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 247581 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.520534 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.520534 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.921103 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.921103 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 133011224 # number of integer regfile reads
-system.cpu.int_regfile_writes 72905073 # number of integer regfile writes
-system.cpu.fp_regfile_reads 6263399 # number of floating regfile reads
-system.cpu.fp_regfile_writes 6178143 # number of floating regfile writes
-system.cpu.misc_regfile_reads 719113 # number of misc regfile reads
+system.cpu.cpi 0.520460 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.520460 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.921379 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.921379 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_writes 1 # number of misc regfile writes
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system.cpu.dcache.tags.replacements 158 # number of replacements
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system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks.
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+system.cpu.dcache.tags.avg_refs 12733.028062 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001303 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001303 # miss rate for WriteReq accesses
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-system.cpu.dcache.blocked_cycles::no_targets 127 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 392 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
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system.cpu.dcache.writebacks::writebacks 108 # number of writebacks
system.cpu.dcache.writebacks::total 108 # number of writebacks
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-system.cpu.l2cache.tags.occ_percent::cpu.data 0.011633 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.073467 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 3589 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.515587 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.708930 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061265 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.045249 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.106513 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 5227 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1371 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 192294 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 192294 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3517 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.159515 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 192203 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 192203 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 9515 # number of WritebackClean hits
@@ -873,18 +871,18 @@ system.cpu.l2cache.demand_misses::total 5227 # nu
system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses
system.cpu.l2cache.overall_misses::total 5227 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 132876500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 132876500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 231097000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 231097000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38506000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 38506000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 231097000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 171382500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 402479500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 231097000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 171382500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 402479500 # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 133969500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 133969500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 232023500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 232023500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 39550000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 39550000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 232023500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 173519500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 405543000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 232023500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 173519500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 405543000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 108 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 108 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 9515 # number of WritebackClean accesses(hits+misses)
@@ -913,18 +911,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.381561 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267330 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.381561 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78024.955960 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78024.955960 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75472.566950 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75472.566950 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83346.320346 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83346.320346 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75472.566950 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79160.508083 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77000.095657 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75472.566950 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79160.508083 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77000.095657 # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78666.764533 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78666.764533 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75775.146963 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75775.146963 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85606.060606 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85606.060606 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75775.146963 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80147.575058 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77586.187105 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75775.146963 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80147.575058 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77586.187105 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -943,18 +941,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5227
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115846500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115846500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200477000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200477000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33886000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33886000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200477000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149732500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 350209500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200477000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149732500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 350209500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 116939500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 116939500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 201403500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 201403500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34930000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34930000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 201403500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151869500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 353273000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 201403500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151869500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 353273000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984962 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984962 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for ReadCleanReq accesses
@@ -967,25 +965,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.381561
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.381561 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68024.955960 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68024.955960 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65472.566950 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65472.566950 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73346.320346 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73346.320346 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68666.764533 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68666.764533 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65775.146963 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65775.146963 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75606.060606 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75606.060606 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65775.146963 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70147.575058 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67586.187105 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65775.146963 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70147.575058 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67586.187105 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 23372 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9673 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution
@@ -1019,7 +1017,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 17179500 # La
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
+system.membus.snoop_filter.tot_requests 5227 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 3524 # Transaction distribution
system.membus.trans_dist::ReadExReq 1703 # Transaction distribution
system.membus.trans_dist::ReadExResp 1703 # Transaction distribution
@@ -1040,9 +1044,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 5227 # Request fanout histogram
-system.membus.reqLayer0.occupancy 6276500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 6278000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 27456000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 27461750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------