diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 685087aff..1294dcd91 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.021909 # Nu sim_ticks 21909208500 # Number of ticks simulated final_tick 21909208500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161119 # Simulator instruction rate (inst/s) -host_op_rate 161119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41933875 # Simulator tick rate (ticks/s) -host_mem_usage 253948 # Number of bytes of host memory used -host_seconds 522.47 # Real time elapsed on the host +host_inst_rate 299674 # Simulator instruction rate (inst/s) +host_op_rate 299674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 77995222 # Simulator tick rate (ticks/s) +host_mem_usage 302008 # Number of bytes of host memory used +host_seconds 280.90 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory system.physmem.bytes_read::total 334528 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 731380000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 632027000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 16102191 # Number of BP lookups system.cpu.branchPred.condPredicted 11688099 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 930994 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 21909208500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 43818418 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -589,6 +592,7 @@ system.cpu.fp_regfile_reads 6263399 # nu system.cpu.fp_regfile_writes 6178143 # number of floating regfile writes system.cpu.misc_regfile_reads 719113 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 158 # number of replacements system.cpu.dcache.tags.tagsinuse 1457.375474 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 28588753 # Total number of references to valid blocks. @@ -606,6 +610,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 57198843 # Number of tag accesses system.cpu.dcache.tags.data_accesses 57198843 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 22095651 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22095651 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6492632 # number of WriteReq hits @@ -722,6 +727,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9515 # number of replacements system.cpu.icache.tags.tagsinuse 1600.928709 # Cycle average of tags in use system.cpu.icache.tags.total_refs 15918297 # Total number of references to valid blocks. @@ -740,6 +746,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 944 system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 31876857 # Number of tag accesses system.cpu.icache.tags.data_accesses 31876857 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 15918297 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 15918297 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 15918297 # number of demand (read+write) hits @@ -814,6 +821,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858 system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2407.364249 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 18027 # Total number of references to valid blocks. @@ -836,6 +844,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 192294 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 192294 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9515 # number of WritebackClean hits @@ -976,6 +985,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution @@ -1008,6 +1018,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 17179500 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3524 # Transaction distribution system.membus.trans_dist::ReadExReq 1703 # Transaction distribution system.membus.trans_dist::ReadExResp 1703 # Transaction distribution |