diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/o3-timing')
3 files changed, 656 insertions, 637 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index d82573b75..f4beb67d4 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 1d7fd9550..e5a3bf839 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4313 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28064 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/o3-timing Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav @@ -26,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 21909208500 because target called exit() +122 123 124 Exiting @ tick 21954917500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 720778178..2ed297d74 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021906 # Number of seconds simulated -sim_ticks 21906070500 # Number of ticks simulated -final_tick 21906070500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021955 # Number of seconds simulated +sim_ticks 21954917500 # Number of ticks simulated +final_tick 21954917500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201237 # Simulator instruction rate (inst/s) -host_op_rate 201237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52367931 # Simulator tick rate (ticks/s) -host_mem_usage 260088 # Number of bytes of host memory used -host_seconds 418.31 # Real time elapsed on the host +host_inst_rate 181107 # Simulator instruction rate (inst/s) +host_op_rate 181107 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47234568 # Simulator tick rate (ticks/s) +host_mem_usage 257228 # Number of bytes of host memory used +host_seconds 464.81 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory -system.physmem.bytes_read::total 334528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 334464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8945831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6325187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15271018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8945831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8945831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8945831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6325187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15271018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5227 # Number of read requests accepted +system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8923012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6311115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15234127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8923012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8923012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8923012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6311115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15234127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5226 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5226 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334464 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334464 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 470 # Per bank write bursts +system.physmem.perBankRdBursts::0 469 # Per bank write bursts system.physmem.perBankRdBursts::1 292 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts system.physmem.perBankRdBursts::3 523 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21905974500 # Total gap between requests +system.physmem.totGap 21954815500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5227 # Read request sizes (log2) +system.physmem.readPktSize::6 5226 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,105 +187,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 385.707657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.399691 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 360.883028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 260 30.16% 30.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 179 20.77% 50.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 93 10.79% 61.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.61% 68.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 30 3.48% 71.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 4.29% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 31 3.60% 79.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 50 5.80% 85.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 125 14.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 862 # Bytes accessed per row activation -system.physmem.totQLat 40339750 # Total ticks spent queuing -system.physmem.totMemAccLat 138346000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7717.57 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385.932636 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.340491 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 360.649518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 261 30.31% 30.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 173 20.09% 50.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 93 10.80% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 6.62% 67.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37 4.30% 72.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 30 3.48% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 47 5.46% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 3.83% 84.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 130 15.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 861 # Bytes accessed per row activation +system.physmem.totQLat 128746000 # Total ticks spent queuing +system.physmem.totMemAccLat 226733500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26130000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24635.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26467.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 43385.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.23 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4357 # Number of row buffer hits during reads +system.physmem.readRowHits 4356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4190926.82 # Average gap between requests -system.physmem.pageHitRate 83.36 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3129840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1707750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19570200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4201074.53 # Average gap between requests +system.physmem.pageHitRate 83.35 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3034500 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1593900 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18099900 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 905463810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12347522250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14707973130 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.505534 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20538678250 # Time in different power states -system.physmem_0.memoryStateTime::REF 731380000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 632936750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3333960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1819125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20779200 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 118625520.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 48811380 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6176640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 312556080 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 154176960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 5001436845 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 5664547785 # Total energy per rank (pJ) +system.physmem_0.averagePower 258.008156 # Core power per rank (mW) +system.physmem_0.totalIdleTime 21831003750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 11536500 # Time in different power states +system.physmem_0.memoryStateTime::REF 50426000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 20744771750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 401491250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 61308000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 685384000 # Time in different power states +system.physmem_1.actEnergy 3177300 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1673595 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19213740 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 902236185 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12350353500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14709101250 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.557040 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20543762750 # Time in different power states -system.physmem_1.memoryStateTime::REF 731380000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 628284250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16102243 # Number of BP lookups -system.cpu.branchPred.condPredicted 11688063 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 931000 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8962915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7507921 # Number of BTB hits +system.physmem_1.refreshEnergy 106332720.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46621440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 5256960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 301076850 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 131936160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 5018107080 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 5633395845 # Total energy per rank (pJ) +system.physmem_1.averagePower 256.589251 # Core power per rank (mW) +system.physmem_1.totalIdleTime 21838957750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 9258500 # Time in different power states +system.physmem_1.memoryStateTime::REF 45178000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 20835144000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 343577000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 61468500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 660291500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16102182 # Number of BP lookups +system.cpu.branchPred.condPredicted 11688137 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 930988 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8963257 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7508303 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.766509 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1594308 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.767575 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1594537 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 466 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 29379 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25730 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3649 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 29363 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3639 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24059471 # DTB read hits -system.cpu.dtb.read_misses 206747 # DTB read misses -system.cpu.dtb.read_acv 6 # DTB read access violations -system.cpu.dtb.read_accesses 24266218 # DTB read accesses -system.cpu.dtb.write_hits 7167964 # DTB write hits -system.cpu.dtb.write_misses 1190 # DTB write misses +system.cpu.dtb.read_hits 24064359 # DTB read hits +system.cpu.dtb.read_misses 206311 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 24270670 # DTB read accesses +system.cpu.dtb.write_hits 7168837 # DTB write hits +system.cpu.dtb.write_misses 1192 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7169154 # DTB write accesses -system.cpu.dtb.data_hits 31227435 # DTB hits -system.cpu.dtb.data_misses 207937 # DTB misses -system.cpu.dtb.data_acv 6 # DTB access violations -system.cpu.dtb.data_accesses 31435372 # DTB accesses -system.cpu.itb.fetch_hits 15930202 # ITB hits +system.cpu.dtb.write_accesses 7170029 # DTB write accesses +system.cpu.dtb.data_hits 31233196 # DTB hits +system.cpu.dtb.data_misses 207503 # DTB misses +system.cpu.dtb.data_acv 4 # DTB access violations +system.cpu.dtb.data_accesses 31440699 # DTB accesses +system.cpu.itb.fetch_hits 15932695 # ITB hits system.cpu.itb.fetch_misses 79 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15930281 # ITB accesses +system.cpu.itb.fetch_accesses 15932774 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,140 +309,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 43812142 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 43909836 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16640800 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 137955116 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16102243 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9127959 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 25951378 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1939862 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2284 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15930202 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367997 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43564561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.166682 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.433652 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16643979 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137979397 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16102182 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9128564 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 26000321 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1939876 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2307 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 15932695 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367713 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43616730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.163451 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433365 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19388904 44.51% 44.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2617971 6.01% 50.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1329653 3.05% 53.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1933242 4.44% 58.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3001866 6.89% 64.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1292154 2.97% 67.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1355153 3.11% 70.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 885983 2.03% 73.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11759635 26.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19436456 44.56% 44.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2618537 6.00% 50.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1330059 3.05% 53.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1934096 4.43% 58.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3001834 6.88% 64.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1292274 2.96% 67.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1355703 3.11% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 886638 2.03% 73.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11761133 26.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43564561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367529 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.148787 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12866207 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8201064 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19435677 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2103016 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 958597 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2653560 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11864 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132121785 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49799 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 958597 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13983011 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4637206 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10599 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20305280 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3669868 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128752916 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 70736 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2012785 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1367413 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 56554 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 94580122 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 167299448 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 159747069 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7552378 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43616730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.366710 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.142335 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12867029 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8250930 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19434015 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2106147 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 958609 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2654207 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11848 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132149793 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49699 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 958609 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13986200 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4658485 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10631 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20305693 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3697112 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128776944 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 70815 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2027533 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1361651 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 79521 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94599397 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167333600 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159779432 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7554167 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26152761 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 954 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 949 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8254781 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26901517 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8704631 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3463893 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1634991 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111837286 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1924 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99746434 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118591 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27659500 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21091403 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1535 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43564561 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.289623 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.099110 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26172036 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 950 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8272242 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26904484 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8704450 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3461355 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1614052 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111855473 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1918 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99762246 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119439 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27677681 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21095832 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1529 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43616730 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.287247 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099564 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11223672 25.76% 25.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7655343 17.57% 43.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7467756 17.14% 60.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5704970 13.10% 73.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4467403 10.25% 83.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2981246 6.84% 90.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2039535 4.68% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1169471 2.68% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 855165 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11270720 25.84% 25.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7659760 17.56% 43.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7470187 17.13% 60.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5700495 13.07% 73.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4466514 10.24% 83.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2981046 6.83% 90.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2041941 4.68% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1170841 2.68% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 855226 1.96% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43564561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43616730 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 481664 20.16% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 484010 20.16% 20.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 522 0.02% 20.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.18% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34768 1.46% 21.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12121 0.51% 22.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1011551 42.34% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 688710 28.83% 93.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159620 6.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34926 1.45% 21.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12192 0.51% 22.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1012503 42.17% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 694860 28.94% 93.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 162157 6.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60652801 60.81% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 489881 0.49% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60662676 60.81% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2847832 2.86% 64.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115342 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2442782 2.45% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 314177 0.31% 67.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 766025 0.77% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2847523 2.85% 64.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2443321 2.45% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314198 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued @@ -454,82 +464,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24850091 24.91% 92.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7267177 7.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24854622 24.91% 92.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7268455 7.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99746434 # Type of FU issued -system.cpu.iq.rate 2.276685 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2388956 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023950 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229877287 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 129889935 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89741335 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15687689 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9649325 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7189295 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93754597 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8380786 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1921314 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99762246 # Type of FU issued +system.cpu.iq.rate 2.271979 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2401186 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024069 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229973015 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 129921960 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89757276 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15688832 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9653681 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7189481 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93781523 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8381902 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1923320 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6905319 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11494 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 40918 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2203528 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6908286 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11342 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40947 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2203347 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42864 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1503 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 958597 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3610605 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 461685 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 122758059 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 241249 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26901517 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8704631 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1924 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38682 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 417297 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 40918 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 531922 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 502439 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98421413 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24266766 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1325021 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 958609 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3613912 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 479107 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122779790 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 241415 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26904484 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8704450 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1918 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38391 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 434865 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40947 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502384 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034333 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98436741 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24271214 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1325505 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10918849 # number of nop insts executed -system.cpu.iew.exec_refs 31435958 # number of memory reference insts executed -system.cpu.iew.exec_branches 12470734 # Number of branches executed -system.cpu.iew.exec_stores 7169192 # Number of stores executed -system.cpu.iew.exec_rate 2.246441 # Inst execution rate -system.cpu.iew.wb_sent 97629714 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 96930630 # cumulative count of insts written-back -system.cpu.iew.wb_producers 66965531 # num instructions producing a value -system.cpu.iew.wb_consumers 94946242 # num instructions consuming a value -system.cpu.iew.wb_rate 2.212415 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705299 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 30856710 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10922399 # number of nop insts executed +system.cpu.iew.exec_refs 31441282 # number of memory reference insts executed +system.cpu.iew.exec_branches 12471732 # Number of branches executed +system.cpu.iew.exec_stores 7170068 # Number of stores executed +system.cpu.iew.exec_rate 2.241792 # Inst execution rate +system.cpu.iew.wb_sent 97645487 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96946757 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66976137 # num instructions producing a value +system.cpu.iew.wb_consumers 94960144 # num instructions consuming a value +system.cpu.iew.wb_rate 2.207860 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705308 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 30878503 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 919666 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39073158 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.352076 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.920100 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 919659 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39122931 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.349084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.919383 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14677251 37.56% 37.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8528323 21.83% 59.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3880033 9.93% 69.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1914323 4.90% 74.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1374739 3.52% 77.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1034073 2.65% 80.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692942 1.77% 82.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727068 1.86% 84.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6244406 15.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14724541 37.64% 37.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8532800 21.81% 59.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3880104 9.92% 69.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1909784 4.88% 74.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1376640 3.52% 77.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1034511 2.64% 80.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692868 1.77% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 729092 1.86% 84.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6242591 15.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39073158 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39122931 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -575,118 +585,118 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6244406 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 155587477 # The number of ROB reads -system.cpu.rob.rob_writes 250066312 # The number of ROB writes -system.cpu.timesIdled 4758 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 247581 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6242591 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155660858 # The number of ROB reads +system.cpu.rob.rob_writes 250112359 # The number of ROB writes +system.cpu.timesIdled 4774 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 293106 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.520460 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520460 # CPI: Total CPI of All Threads -system.cpu.ipc 1.921379 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.921379 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 132984940 # number of integer regfile reads -system.cpu.int_regfile_writes 72890464 # number of integer regfile writes -system.cpu.fp_regfile_reads 6263699 # number of floating regfile reads -system.cpu.fp_regfile_writes 6177982 # number of floating regfile writes -system.cpu.misc_regfile_reads 719169 # number of misc regfile reads +system.cpu.cpi 0.521620 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.521620 # CPI: Total CPI of All Threads +system.cpu.ipc 1.917104 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.917104 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133010551 # number of integer regfile reads +system.cpu.int_regfile_writes 72904644 # number of integer regfile writes +system.cpu.fp_regfile_reads 6263409 # number of floating regfile reads +system.cpu.fp_regfile_writes 6178123 # number of floating regfile writes +system.cpu.misc_regfile_reads 719113 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.358075 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28585648 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1457.034872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28588531 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12733.028062 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12734.312249 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.358075 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355800 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355800 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.034872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355721 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355721 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57192649 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57192649 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22092545 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22092545 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492630 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492630 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 473 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 473 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28585175 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28585175 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28585175 # number of overall hits -system.cpu.dcache.overall_hits::total 28585175 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1080 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1080 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8473 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8473 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 57198427 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57198427 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22095438 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22095438 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492623 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492623 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 470 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 470 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28588061 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28588061 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28588061 # number of overall hits +system.cpu.dcache.overall_hits::total 28588061 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1079 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1079 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8480 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8480 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9553 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9553 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9553 # number of overall misses -system.cpu.dcache.overall_misses::total 9553 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 72549500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 72549500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 550211742 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 550211742 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 86000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 86000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 622761242 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 622761242 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 622761242 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 622761242 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22093625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22093625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9559 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9559 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9559 # number of overall misses +system.cpu.dcache.overall_misses::total 9559 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87318000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87318000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 649645257 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 649645257 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 106000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 106000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 736963257 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 736963257 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 736963257 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 736963257 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22096517 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22096517 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 474 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 474 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28594728 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28594728 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28594728 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28594728 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 471 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 471 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28597620 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28597620 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28597620 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28597620 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000049 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001303 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001303 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002110 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002110 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002123 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002123 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67175.462963 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67175.462963 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64937.063850 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64937.063850 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 86000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 86000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65190.122684 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65190.122684 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65190.122684 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65190.122684 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33457 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 396 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 84.487374 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80924.930491 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 80924.930491 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76609.110495 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76609.110495 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 106000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 106000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77096.271263 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77096.271263 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77096.271263 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77096.271263 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 43101 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 174 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 350 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 123.145714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 565 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 565 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6744 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6744 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7309 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7309 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7309 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7309 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 564 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 564 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6751 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6751 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7315 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7315 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7315 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7315 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1729 # number of WriteReq MSHR misses @@ -697,232 +707,232 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2244 system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40822500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40822500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 136978995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 136978995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 85000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 85000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177801495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 177801495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177801495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 177801495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47711000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47711000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177283495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 177283495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224994495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 224994495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224994495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 224994495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002110 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002110 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002123 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002123 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79266.990291 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79266.990291 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79224.404280 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79224.404280 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 85000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 85000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79234.177807 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79234.177807 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79234.177807 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79234.177807 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 9515 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.893985 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15915792 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11453 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1389.661399 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92642.718447 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92642.718447 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102535.277617 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102535.277617 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 105000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 105000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100264.926471 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 100264.926471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100264.926471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 100264.926471 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 9511 # number of replacements +system.cpu.icache.tags.tagsinuse 1600.395362 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15918262 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11449 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1390.362652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.893985 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781687 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781687 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.395362 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781443 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781443 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 753 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 943 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 31871855 # Number of tag accesses -system.cpu.icache.tags.data_accesses 31871855 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 15915792 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15915792 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15915792 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15915792 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15915792 # number of overall hits -system.cpu.icache.overall_hits::total 15915792 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14409 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14409 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14409 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14409 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14409 # number of overall misses -system.cpu.icache.overall_misses::total 14409 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 447639000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 447639000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 447639000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 447639000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 447639000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 447639000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15930201 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15930201 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15930201 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15930201 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15930201 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15930201 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000905 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000905 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000905 # 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Number of tag accesses +system.cpu.icache.tags.data_accesses 31876835 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 15918262 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15918262 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15918262 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15918262 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15918262 # number of overall hits +system.cpu.icache.overall_hits::total 15918262 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14431 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14431 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14431 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14431 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14431 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35244.750884 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35244.750884 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35244.750884 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 485 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 89.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 80.833333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 9515 # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29476.863978 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29476.863978 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29476.863978 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29476.863978 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29476.863978 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33078.427948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33078.427948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33078.427948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33078.427948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33078.427948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 33078.427948 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3490.224517 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 18145 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5227 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.471399 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3489.228607 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 18138 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5226 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.470723 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.384585 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061244 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.045239 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106483 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5226 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1370 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3517 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.159515 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 192203 # 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miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267330 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267336 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964365 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.381561 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267330 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.381599 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267336 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.381561 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78666.764533 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78666.764533 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75775.146963 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75775.146963 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85606.060606 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85606.060606 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75775.146963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80147.575058 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77586.187105 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75775.146963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80147.575058 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77586.187105 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.381599 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102333.529066 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102333.529066 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89244.691277 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89244.691277 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100559.523810 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100559.523810 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89244.691277 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101954.965358 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94510.237275 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89244.691277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101954.965358 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94510.237275 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -931,122 +941,122 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1703 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1703 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3062 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3062 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3061 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3061 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 462 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 462 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3062 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3061 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5227 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5226 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3061 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 116939500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 116939500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 201403500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 201403500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34930000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34930000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 201403500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151869500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 353273000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 201403500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151869500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 353273000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 5226 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 157244000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 157244000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 242568000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 242568000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41838500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41838500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 242568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 199082500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 441650500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 242568000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 199082500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 441650500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984962 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984962 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267330 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267336 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267336 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.895349 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.895349 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267336 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.381561 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.381599 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267336 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.381561 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68666.764533 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68666.764533 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65775.146963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65775.146963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75606.060606 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75606.060606 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65775.146963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70147.575058 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67586.187105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65775.146963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70147.575058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67586.187105 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 23372 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9673 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.381599 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92333.529066 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92333.529066 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79244.691277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79244.691277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90559.523810 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90559.523810 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79244.691277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91954.965358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84510.237275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79244.691277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91954.965358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84510.237275 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 23364 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9669 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 11965 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9511 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1729 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1729 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11450 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 516 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32422 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32410 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 37070 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1341952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 37058 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1341440 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1492544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1492032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 13699 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13695 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13699 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13695 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13699 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 21309000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13695 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21301000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17179500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17173500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5227 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 5226 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3524 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3523 # Transaction distribution system.membus.trans_dist::ReadExReq 1703 # Transaction distribution system.membus.trans_dist::ReadExResp 1703 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3524 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3523 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10452 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334464 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5227 # Request fanout histogram +system.membus.snoop_fanout::samples 5226 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5227 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5226 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5227 # Request fanout histogram -system.membus.reqLayer0.occupancy 6278000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5226 # Request fanout histogram +system.membus.reqLayer0.occupancy 6271000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27461750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27424000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |