diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt | 430 |
1 files changed, 215 insertions, 215 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 4e099442b..85445221a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.118729 # Number of seconds simulated -sim_ticks 118729316000 # Number of ticks simulated -final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 118729316500 # Number of ticks simulated +final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1660785 # Simulator instruction rate (inst/s) -host_op_rate 1660785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2145562848 # Simulator tick rate (ticks/s) -host_mem_usage 293264 # Number of bytes of host memory used -host_seconds 55.34 # Real time elapsed on the host +host_inst_rate 1507080 # Simulator instruction rate (inst/s) +host_op_rate 1507080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1946992285 # Simulator tick rate (ticks/s) +host_mem_usage 297820 # Number of bytes of host memory used +host_seconds 60.98 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,29 +29,6 @@ system.physmem.bw_inst_read::total 1412827 # In system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 3043 # Transaction distribution -system.membus.trans_dist::ReadResp 3043 # Transaction distribution -system.membus.trans_dist::ReadExReq 1722 # Transaction distribution -system.membus.trans_dist::ReadExResp 1722 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4765 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4765 # Request fanout histogram -system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237458632 # number of cpu cycles simulated +system.cpu.numCycles 237458633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237458632 # Number of busy cycles +system.cpu.num_busy_cycles 237458633 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched @@ -144,13 +121,122 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1442.043377 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043377 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits +system.cpu.dcache.overall_hits::total 26495078 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses +system.cpu.dcache.overall_misses::total 2223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 115612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48813.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48813.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52875.286041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52875.286041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1418.052759 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052759 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id @@ -174,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 220712000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 220712000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 220712000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 220712000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 220712000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220712500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220712500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220712500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220712500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220712500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -192,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.605170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25935.605170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25935.605170 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.663925 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25935.663925 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25935.663925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25935.663925 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 207947500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 207947500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 207947500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 207947500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 207947500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 207947500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24435.663925 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24435.663925 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2074.070538 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.795177 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.017985 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257376 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy @@ -277,17 +363,17 @@ system.cpu.l2cache.demand_misses::total 4765 # nu system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4765 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 136292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21944000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 158236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 136292000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111488000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 247780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 136292000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111488000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 247780000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137603000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22155000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 159758000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90405000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 90405000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137603000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112560000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 250163000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137603000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112560000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 250163000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses) @@ -312,17 +398,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.443958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.164312 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.104932 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -342,17 +428,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4765 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 121720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 190600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106150500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17091000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 123241500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69741000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69741000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106150500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 192982500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106150500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86832000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 192982500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses @@ -364,127 +450,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits -system.cpu.dcache.overall_hits::total 26495078 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses -system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -514,5 +491,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 12765000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3043 # Transaction distribution +system.membus.trans_dist::ReadResp 3043 # Transaction distribution +system.membus.trans_dist::ReadExReq 1722 # Transaction distribution +system.membus.trans_dist::ReadExResp 1722 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4765 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4765 # Request fanout histogram +system.membus.reqLayer0.occupancy 4765500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 23825500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |