diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64')
4 files changed, 761 insertions, 757 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index ddac6bec8..6032e061b 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:36:18 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:58:42 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 41833966000 because target called exit() +122 123 124 Exiting @ tick 42005374000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 7525585e3..2e73aee88 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041834 # Number of seconds simulated -sim_ticks 41833966000 # Number of ticks simulated -final_tick 41833966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.042005 # Number of seconds simulated +sim_ticks 42005374000 # Number of ticks simulated +final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151560 # Simulator instruction rate (inst/s) -host_op_rate 151560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68989742 # Simulator tick rate (ticks/s) +host_inst_rate 147839 # Simulator instruction rate (inst/s) +host_op_rate 147839 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67571644 # Simulator tick rate (ticks/s) host_mem_usage 213560 # Number of bytes of host memory used -host_seconds 606.38 # Real time elapsed on the host +host_seconds 621.64 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 316032 # Number of bytes read from this memory @@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 4938 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7554436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 4274421 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 7554436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 7523609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 4256979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 7523609 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 26498119 # DT system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 26498152 # DTB accesses -system.cpu.itb.fetch_hits 9991202 # ITB hits +system.cpu.itb.fetch_hits 10037351 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9991251 # ITB accesses +system.cpu.itb.fetch_accesses 10037400 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83667933 # number of cpu cycles simulated +system.cpu.numCycles 84010749 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83292959 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83632403 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10907 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7700653 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75967280 # Number of cycles cpu stages are processed. -system.cpu.activity 90.796172 # Percentage of cycles cpu is active +system.cpu.timesIdled 11097 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7735993 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76274756 # Number of cycles cpu stages are processed. +system.cpu.activity 90.791663 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -74,158 +74,158 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.914124 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads -system.cpu.ipc 1.098426 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.914124 # CPI: Total CPI of All Threads +system.cpu.ipc 1.093944 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.098426 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 13542330 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9941405 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4410938 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 8655858 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 4135478 # Number of BTB hits +system.cpu.ipc_total 1.093944 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 13563923 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9779691 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4496836 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7950423 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3848158 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 47.776639 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 6269254 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7273076 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73609025 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 123 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 48.401928 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5997418 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7566505 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73742077 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136184497 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206079 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136317549 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206798 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8057967 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38654467 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26652325 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3861647 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 548433 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4410080 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5830622 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.064235 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57347630 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 458254 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 8058686 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38530251 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26765541 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3521133 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 974845 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4495978 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5744724 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.903025 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57471384 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 458266 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 27446781 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56221152 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 67.195579 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34307675 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49360258 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.995431 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33744588 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49923345 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.668434 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65638077 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029856 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.549303 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29755825 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53912108 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.435807 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 7551 # number of replacements -system.cpu.icache.tagsinuse 1491.782957 # Cycle average of tags in use -system.cpu.icache.total_refs 9979713 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 27790213 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56220536 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.920646 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34560671 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49450078 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.861608 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34032650 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49978099 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.490124 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65981194 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029555 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.461010 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30068425 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53942324 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.208836 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 8111 # number of replacements +system.cpu.icache.tagsinuse 1492.322334 # Cycle average of tags in use +system.cpu.icache.total_refs 10025618 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9996 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1002.962985 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1491.782957 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728410 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728410 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 9979713 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 9979713 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 9979713 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 9979713 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 9979713 # number of overall hits -system.cpu.icache.overall_hits::total 9979713 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11486 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11486 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11486 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11486 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11486 # number of overall misses -system.cpu.icache.overall_misses::total 11486 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 291407500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 291407500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 291407500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 291407500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 291407500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 291407500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9991199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9991199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9991199 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9991199 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9991199 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9991199 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001150 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001150 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001150 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25370.668640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1492.322334 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728673 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728673 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10025618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10025618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10025618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10025618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10025618 # number of overall hits +system.cpu.icache.overall_hits::total 10025618 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11728 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11728 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11728 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11728 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11728 # number of overall misses +system.cpu.icache.overall_misses::total 11728 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 295393500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 295393500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 295393500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 295393500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 295393500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 295393500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10037346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10037346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10037346 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10037346 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10037346 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10037346 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001168 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001168 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001168 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25187.031037 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 97000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 16166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2050 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2050 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2050 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2050 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2050 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2050 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9436 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9436 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 222700000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 222700000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 222700000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 222700000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 222700000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 222700000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23601.102162 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1732 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1732 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1732 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1732 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1732 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1732 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9996 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9996 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9996 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9996 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9996 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9996 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 228898000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 228898000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 228898000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 228898000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228898000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 228898000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22898.959584 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491206 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.511431 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491208 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.872695 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.532122 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351937 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351937 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995645 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995645 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6495561 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6495561 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491206 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491206 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491206 # number of overall hits -system.cpu.dcache.overall_hits::total 26491206 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 553 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 553 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5542 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5542 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6095 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6095 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6095 # number of overall misses -system.cpu.dcache.overall_misses::total 6095 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28393500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28393500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 303801000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 303801000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 332194500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 332194500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 332194500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 332194500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 1441.511431 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351932 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351932 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995646 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995646 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6495562 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6495562 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26491208 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491208 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491208 # number of overall hits +system.cpu.dcache.overall_hits::total 26491208 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 552 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 552 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5541 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5541 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6093 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6093 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6093 # number of overall misses +system.cpu.dcache.overall_misses::total 6093 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28391500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28391500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 303790500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 303790500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 332182000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 332182000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 332182000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 332182000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -238,28 +238,28 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000230 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51344.484629 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54817.935763 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51433.876812 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54825.933947 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 41043500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 824 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49870.595383 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3794 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3794 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3872 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3872 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3872 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3872 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3793 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3793 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3870 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3870 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3870 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3870 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -268,49 +268,49 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92997500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92997500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 116210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116210500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 116210500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92995500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92995500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116211500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 116211500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116211500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 116211500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48869.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53202.231121 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48875.789474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53201.086957 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6704 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7264 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.213285 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.838059 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.375269 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.040274 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055553 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066811 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 6642 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 17.847253 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.879596 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.003621 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055569 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7202 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6695 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7255 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 6642 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 7202 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6721 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 6642 # number of overall hits +system.cpu.l2cache.demand_hits::total 7281 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7202 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 6721 # number of overall hits +system.cpu.l2cache.overall_hits::total 7281 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses @@ -322,44 +322,44 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146193000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22134500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 168327500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90565000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 90565000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 146193000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112699500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 258892500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 146193000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112699500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 258892500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 9436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146177000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22139000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 168316000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90566000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 90566000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 146177000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112705000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 258882000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 146177000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112705000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 258882000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 9996 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 9911 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 10471 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 9996 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 11659 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9436 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 12219 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9996 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 11659 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.296100 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 12219 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279512 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.296100 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279512 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.296100 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279512 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52323.908375 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52451.421801 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52592.915215 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.181818 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52462.085308 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52593.495935 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,31 +379,31 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112072000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129053500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69344000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69344000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112072000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86325500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 198397500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112072000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86325500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 198397500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112070000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129051000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69345500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69345500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112070000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86326500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 198396500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112070000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86326500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 198396500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40111.667860 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40240.521327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40269.454123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.952040 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40239.336493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40270.325203 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index f5b2c31fd..58e98acc5 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:45:24 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 18:07:15 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 29167093500 because target called exit() +122 123 124 Exiting @ tick 23638033500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 221154573..8502942e2 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.029167 # Number of seconds simulated -sim_ticks 29167093500 # Number of ticks simulated -final_tick 29167093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023638 # Number of seconds simulated +sim_ticks 23638033500 # Number of ticks simulated +final_tick 23638033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 198361 # Simulator instruction rate (inst/s) -host_op_rate 198361 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68729352 # Simulator tick rate (ticks/s) +host_inst_rate 231314 # Simulator instruction rate (inst/s) +host_op_rate 231314 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64954124 # Simulator tick rate (ticks/s) host_mem_usage 214912 # Number of bytes of host memory used -host_seconds 424.38 # Real time elapsed on the host +host_seconds 363.92 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 332416 # Number of bytes read from this memory -system.physmem.bytes_inst_read 193856 # Number of instructions bytes read from this memory +system.physmem.bytes_read 336064 # Number of bytes read from this memory +system.physmem.bytes_inst_read 197952 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5194 # Number of read requests responded to by this memory +system.physmem.num_reads 5251 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11396953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 6646394 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 11396953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 14217088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 8374301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 14217088 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 25236325 # DTB read hits -system.cpu.dtb.read_misses 540509 # DTB read misses +system.cpu.dtb.read_hits 23223377 # DTB read hits +system.cpu.dtb.read_misses 198479 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 25776834 # DTB read accesses -system.cpu.dtb.write_hits 7362909 # DTB write hits -system.cpu.dtb.write_misses 1032 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7363941 # DTB write accesses -system.cpu.dtb.data_hits 32599234 # DTB hits -system.cpu.dtb.data_misses 541541 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 33140775 # DTB accesses -system.cpu.itb.fetch_hits 18604047 # ITB hits -system.cpu.itb.fetch_misses 85 # ITB misses +system.cpu.dtb.read_accesses 23421856 # DTB read accesses +system.cpu.dtb.write_hits 7079825 # DTB write hits +system.cpu.dtb.write_misses 1403 # DTB write misses +system.cpu.dtb.write_acv 5 # DTB write access violations +system.cpu.dtb.write_accesses 7081228 # DTB write accesses +system.cpu.dtb.data_hits 30303202 # DTB hits +system.cpu.dtb.data_misses 199882 # DTB misses +system.cpu.dtb.data_acv 5 # DTB access violations +system.cpu.dtb.data_accesses 30503084 # DTB accesses +system.cpu.itb.fetch_hits 14943347 # ITB hits +system.cpu.itb.fetch_misses 91 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 18604132 # ITB accesses +system.cpu.itb.fetch_accesses 14943438 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,247 +53,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 58334188 # number of cpu cycles simulated +system.cpu.numCycles 47276068 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 18443606 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 13550904 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1909309 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15151906 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11744171 # Number of BTB hits +system.cpu.BPredUnit.lookups 15033034 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10893927 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 965097 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8612659 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7067377 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1797123 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2508 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 19753130 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 155901269 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18443606 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13541294 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 28873870 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8029527 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3519156 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 18604047 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 633220 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 58241050 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.676828 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.252315 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1490279 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6040 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15621230 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128217007 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15033034 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8557656 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22378884 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4633381 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5548401 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14943347 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 336798 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47185446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.717300 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.373013 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29367180 50.42% 50.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2937608 5.04% 55.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2015194 3.46% 58.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3338566 5.73% 64.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4094138 7.03% 71.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1423310 2.44% 74.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1755062 3.01% 77.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1585835 2.72% 79.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11724157 20.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24806562 52.57% 52.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2389979 5.07% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1207538 2.56% 60.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1775063 3.76% 63.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2802024 5.94% 69.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1169800 2.48% 72.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1228019 2.60% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 790135 1.67% 76.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11016326 23.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 58241050 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316171 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.672554 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 21649179 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2708949 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 27144653 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 658698 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6079571 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2969190 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13806 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 150046107 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43597 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6079571 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23241789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 566661 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6095 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 26202396 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2144538 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 144061667 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 244284 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1605069 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 105522995 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 186327738 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 175726328 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10601410 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47185446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317984 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.712091 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17463925 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4249040 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20759249 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090184 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3623048 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2545357 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12255 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125130253 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31826 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3623048 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18629909 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 965094 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8920 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20661182 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3297293 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122152175 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 401388 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2422623 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89685518 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158620062 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148881837 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9738225 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37095634 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 535 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 531 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6071657 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29750182 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9383371 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2457988 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 836885 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 120824169 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 510 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 104934850 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 288533 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35688110 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 27652526 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 58241050 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.801733 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.850509 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21258157 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1427 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1434 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8739521 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25557847 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8301356 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2609711 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 904973 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106143007 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2358 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96975947 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189226 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21491456 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16142477 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1969 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47185446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.055209 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876136 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19806248 34.01% 34.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11039636 18.96% 52.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9348946 16.05% 69.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6752104 11.59% 80.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5521673 9.48% 90.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2974014 5.11% 95.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1775531 3.05% 98.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 852122 1.46% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 170776 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12454883 26.40% 26.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9420722 19.97% 46.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8458741 17.93% 64.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6315379 13.38% 77.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4948925 10.49% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2846998 6.03% 94.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1728154 3.66% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 801160 1.70% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 210484 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 58241050 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47185446 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 161609 9.97% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 218 0.01% 9.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 6469 0.40% 10.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 2295 0.14% 10.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 845619 52.17% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 527151 32.52% 95.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77634 4.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 186828 11.91% 11.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 238 0.02% 11.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7150 0.46% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5464 0.35% 12.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842994 53.75% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 446294 28.45% 94.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79499 5.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 63561145 60.57% 60.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 485535 0.46% 61.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2794061 2.66% 63.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 63.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2411045 2.30% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 308682 0.29% 66.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 763571 0.73% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 318 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27006510 25.74% 92.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7488931 7.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58979048 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480591 0.50% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2800978 2.89% 64.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115548 0.12% 64.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2385848 2.46% 66.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311419 0.32% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759609 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23970757 24.72% 92.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7171823 7.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 104934850 # Type of FU issued -system.cpu.iq.rate 1.798857 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1620995 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015448 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 254843963 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146750024 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 92740043 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15176315 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9791044 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7062550 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 98540004 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8015834 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1319105 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96975947 # Type of FU issued +system.cpu.iq.rate 2.051269 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1568467 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016174 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227768377 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118855856 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87353688 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15126656 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8815414 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7066282 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90552040 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7992367 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1520027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9753984 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15279 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28494 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2882268 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5561649 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19937 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34563 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1800253 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10177 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10514 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6079571 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 81043 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15363 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 132624218 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 876009 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29750182 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9383371 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 510 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 184 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28494 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1787084 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 342134 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2129218 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 102333218 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25777384 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2601632 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3623048 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133924 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17201 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116441723 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 394323 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25557847 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8301356 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2358 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2853 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 36 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34563 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 569788 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508452 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1078240 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95678343 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23422851 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1297604 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11799539 # number of nop insts executed -system.cpu.iew.exec_refs 33141424 # number of memory reference insts executed -system.cpu.iew.exec_branches 12916232 # Number of branches executed -system.cpu.iew.exec_stores 7364040 # Number of stores executed -system.cpu.iew.exec_rate 1.754258 # Inst execution rate -system.cpu.iew.wb_sent 101006568 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99802593 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67789343 # num instructions producing a value -system.cpu.iew.wb_consumers 93484829 # num instructions consuming a value +system.cpu.iew.exec_nop 10296358 # number of nop insts executed +system.cpu.iew.exec_refs 30504278 # number of memory reference insts executed +system.cpu.iew.exec_branches 12076445 # Number of branches executed +system.cpu.iew.exec_stores 7081427 # Number of stores executed +system.cpu.iew.exec_rate 2.023822 # Inst execution rate +system.cpu.iew.wb_sent 94963988 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94419970 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64608180 # num instructions producing a value +system.cpu.iew.wb_consumers 89987821 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.710877 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back +system.cpu.iew.wb_rate 1.997204 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24539814 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 52161479 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.761895 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.510937 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 953116 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43562398 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.109688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.736301 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23655247 45.35% 45.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11195713 21.46% 66.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5070133 9.72% 76.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2810925 5.39% 81.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1675607 3.21% 85.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1392452 2.67% 87.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 795157 1.52% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 831289 1.59% 90.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4734956 9.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17041146 39.12% 39.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9957627 22.86% 61.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4507142 10.35% 72.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2283698 5.24% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1617573 3.71% 81.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1122316 2.58% 83.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722162 1.66% 85.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 820666 1.88% 87.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5490068 12.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43562398 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -304,64 +304,64 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4734956 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5490068 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 180051805 # The number of ROB reads -system.cpu.rob.rob_writes 271380444 # The number of ROB writes -system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 154514159 # The number of ROB reads +system.cpu.rob.rob_writes 236533126 # The number of ROB writes +system.cpu.timesIdled 2183 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 90622 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443060 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443060 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 138495671 # number of integer regfile reads -system.cpu.int_regfile_writes 75435014 # number of integer regfile writes -system.cpu.fp_regfile_reads 6177236 # number of floating regfile reads -system.cpu.fp_regfile_writes 6044349 # number of floating regfile writes -system.cpu.misc_regfile_reads 715554 # number of misc regfile reads +system.cpu.cpi 0.561609 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561609 # CPI: Total CPI of All Threads +system.cpu.ipc 1.780599 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.780599 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129442497 # number of integer regfile reads +system.cpu.int_regfile_writes 70765525 # number of integer regfile writes +system.cpu.fp_regfile_reads 6190739 # number of floating regfile reads +system.cpu.fp_regfile_writes 6047859 # number of floating regfile writes +system.cpu.misc_regfile_reads 714278 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8695 # number of replacements -system.cpu.icache.tagsinuse 1593.002324 # Cycle average of tags in use -system.cpu.icache.total_refs 18592194 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks. +system.cpu.icache.replacements 10359 # number of replacements +system.cpu.icache.tagsinuse 1607.190165 # Cycle average of tags in use +system.cpu.icache.total_refs 14929668 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12297 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1214.090266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1593.002324 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777833 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777833 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 18592194 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18592194 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18592194 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18592194 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18592194 # number of overall hits -system.cpu.icache.overall_hits::total 18592194 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11853 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11853 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11853 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11853 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11853 # number of overall misses -system.cpu.icache.overall_misses::total 11853 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 188036500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 188036500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 188036500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 188036500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 18604047 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 18604047 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 18604047 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 18604047 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000637 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000637 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000637 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15864.042858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1607.190165 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.784761 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.784761 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14929668 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14929668 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14929668 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14929668 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14929668 # number of overall hits +system.cpu.icache.overall_hits::total 14929668 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13679 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13679 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13679 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13679 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13679 # number of overall misses +system.cpu.icache.overall_misses::total 13679 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 203969000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 203969000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 203969000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 203969000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 203969000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 203969000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14943347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14943347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14943347 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14943347 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14943347 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14943347 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14911.104613 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,258 +370,258 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1225 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1225 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1225 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1225 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10628 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124769000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 124769000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11739.649981 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1382 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1382 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1382 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1382 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1382 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1382 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12297 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12297 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12297 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12297 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12297 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12297 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130905500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130905500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130905500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130905500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130905500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130905500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10645.319997 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 159 # number of replacements -system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use -system.cpu.dcache.total_refs 30399158 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks. +system.cpu.dcache.replacements 158 # number of replacements +system.cpu.dcache.tagsinuse 1455.343539 # Cycle average of tags in use +system.cpu.dcache.total_refs 28184934 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2238 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12593.804290 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1462.507461 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23906051 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23906051 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493055 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 30399106 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 30399106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 30399106 # number of overall hits -system.cpu.dcache.overall_hits::total 30399106 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8048 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8048 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1455.343539 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.355308 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.355308 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21691339 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21691339 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493048 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493048 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 547 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 547 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28184387 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28184387 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28184387 # number of overall hits +system.cpu.dcache.overall_hits::total 28184387 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 946 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 946 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8055 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 8986 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8986 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8986 # number of overall misses -system.cpu.dcache.overall_misses::total 8986 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28163500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28163500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 289889000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 289889000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9001 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9001 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9001 # number of overall misses +system.cpu.dcache.overall_misses::total 9001 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28453500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28453500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289283500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289283500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 38000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 318052500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 318052500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23906989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23906989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 317737000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 317737000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 317737000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 317737000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21692285 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21692285 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 30408092 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 30408092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 30408092 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 30408092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000039 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018868 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000296 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000296 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30025.053305 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36020.004970 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 548 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 548 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28193388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28193388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28193388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28193388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001239 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001825 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000319 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000319 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30077.695560 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35913.531968 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6317 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6317 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6741 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6741 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6741 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6741 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 435 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 435 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6329 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6329 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6764 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6764 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6764 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6764 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1726 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1726 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2245 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2245 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61655000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61655000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2237 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2237 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2237 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2237 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16444500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16444500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61474000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61474000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78124500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78124500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78124500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78124500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018868 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32041.828794 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35618.139804 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 77918500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 77918500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 77918500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 77918500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000265 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001825 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32181.017613 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35616.454229 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34799.331849 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7666 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.155793 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2429.489974 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9270 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3617 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.562897 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.633584 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2000.487710 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 382.154472 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000538 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061050 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011662 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.073251 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7599 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 56 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7655 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 17.697251 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2033.991651 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 377.801072 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.062072 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011530 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.074142 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 9204 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 9258 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7599 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7680 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7599 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits -system.cpu.l2cache.overall_hits::total 7680 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3029 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 459 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3488 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1706 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1706 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3029 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2165 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5194 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3029 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses -system.cpu.l2cache.overall_misses::total 5194 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 103998000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15794500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 119792500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 59244000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 59244000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 103998000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 75038500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179036500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 103998000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 75038500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179036500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10628 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 515 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11143 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 9204 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 80 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 9284 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9204 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 80 # number of overall hits +system.cpu.l2cache.overall_hits::total 9284 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3093 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 458 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3551 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1700 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1700 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3093 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2158 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5251 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3093 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2158 # number of overall misses +system.cpu.l2cache.overall_misses::total 5251 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106153500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15762000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 121915500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 59022000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 59022000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 106153500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 74784000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 180937500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 106153500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 74784000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 180937500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 12297 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 512 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 12809 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10628 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2246 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 12874 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10628 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2246 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 12874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.285002 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.891262 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985557 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.285002 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.963936 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.285002 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.963936 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34334.103665 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34410.675381 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34726.846424 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1726 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1726 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12297 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2238 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 14535 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12297 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2238 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 14535 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.251525 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894531 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984936 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.251525 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964254 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.251525 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964254 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.562561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34414.847162 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34718.823529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 459 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3488 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5194 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5194 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 94144500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14345500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108490000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53828000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53828000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 94144500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68173500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 162318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94144500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68173500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 162318000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.891262 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.049851 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31253.812636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31552.168816 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3093 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3551 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1700 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1700 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3093 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2158 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5251 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3093 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2158 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5251 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96110500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14313000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 110423500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53634000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53634000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96110500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67947000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 164057500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96110500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67947000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 164057500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.553185 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31251.091703 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31549.411765 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |