diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64')
7 files changed, 1075 insertions, 1076 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini index 459f492af..5ec95ce79 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini @@ -125,7 +125,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -548,7 +548,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -597,7 +597,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr index de77515a1..f0a9a7c93 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr @@ -1,3 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout index 4d57fab87..606ce3744 100644..100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:41:53 -gem5 started May 7 2014 15:05:33 -gem5 executing on cz3212c2d7 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2 +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 20:55:41 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -25,4 +24,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 51810251500 because target called exit() +122 123 124 Exiting @ tick 51910606500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index f4338fb5a..5fb393485 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.052057 # Number of seconds simulated -sim_ticks 52057006500 # Number of ticks simulated -final_tick 52057006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.051911 # Number of seconds simulated +sim_ticks 51910606500 # Number of ticks simulated +final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 338250 # Simulator instruction rate (inst/s) -host_op_rate 338250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191596351 # Simulator tick rate (ticks/s) -host_mem_usage 300296 # Number of bytes of host memory used -host_seconds 271.70 # Real time elapsed on the host +host_inst_rate 229005 # Simulator instruction rate (inst/s) +host_op_rate 229005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 129351336 # Simulator tick rate (ticks/s) +host_mem_usage 295204 # Number of bytes of host memory used +host_seconds 401.31 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 202752 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory -system.physmem.bytes_read::total 340480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 340416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202752 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5320 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3896037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2644486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6540522 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3896037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3896037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3896037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2644486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6540522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5320 # Number of read requests accepted +system.physmem.num_reads::total 5319 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3905791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2651944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6557735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3905791 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3905791 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3905791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2651944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6557735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5319 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5320 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5319 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 340480 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 340416 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 340480 # Total read bytes from the system interface side +system.physmem.bytesReadSys 340416 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 469 # Per bank write bursts system.physmem.perBankRdBursts::1 295 # Per bank write bursts -system.physmem.perBankRdBursts::2 307 # Per bank write bursts +system.physmem.perBankRdBursts::2 308 # Per bank write bursts system.physmem.perBankRdBursts::3 524 # Per bank write bursts system.physmem.perBankRdBursts::4 224 # Per bank write bursts system.physmem.perBankRdBursts::5 238 # Per bank write bursts system.physmem.perBankRdBursts::6 222 # Per bank write bursts system.physmem.perBankRdBursts::7 289 # Per bank write bursts -system.physmem.perBankRdBursts::8 252 # Per bank write bursts +system.physmem.perBankRdBursts::8 251 # Per bank write bursts system.physmem.perBankRdBursts::9 282 # Per bank write bursts -system.physmem.perBankRdBursts::10 255 # Per bank write bursts +system.physmem.perBankRdBursts::10 254 # Per bank write bursts system.physmem.perBankRdBursts::11 261 # Per bank write bursts system.physmem.perBankRdBursts::12 410 # Per bank write bursts system.physmem.perBankRdBursts::13 344 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 52056919000 # Total gap between requests +system.physmem.totGap 51910519000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5320 # Read request sizes (log2) +system.physmem.readPktSize::6 5319 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 973 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.809866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.712248 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.458818 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 301 30.94% 30.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 209 21.48% 52.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 98 10.07% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 92 9.46% 71.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 72 7.40% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 45 4.62% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.47% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 1.95% 88.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 113 11.61% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 973 # Bytes accessed per row activation -system.physmem.totQLat 31528250 # Total ticks spent queuing -system.physmem.totMemAccLat 131278250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26600000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5926.36 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 979 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 346.541369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.036393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.369108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 309 31.56% 31.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 207 21.14% 52.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 105 10.73% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 89 9.09% 72.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 7.25% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 31 3.17% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 27 2.76% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 27 2.76% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 113 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 979 # Bytes accessed per row activation +system.physmem.totQLat 35331250 # Total ticks spent queuing +system.physmem.totMemAccLat 135062500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6642.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24676.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25392.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.54 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4340 # Number of row buffer hits during reads +system.physmem.readRowHits 4332 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.58 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9785135.15 # Average gap between requests -system.physmem.pageHitRate 81.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3492720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1905750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9759450.84 # Average gap between requests +system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3507840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1914000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19835400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3399723600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1761174315 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29685915000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34872054585 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.954967 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49382007750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1738100000 # Time in different power states +system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1735578180 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29619604500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34770500880 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.907929 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49271576750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 931384250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 898679500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21231600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3848040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2099625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3399723600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1805818995 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29646744750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34879431555 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.096868 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49317281000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1738100000 # Time in different power states +system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1825261695 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29540934750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34783421070 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.156857 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49142723000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 996955000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1030068000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 11466165 # Number of BP lookups -system.cpu.branchPred.condPredicted 8229222 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 788767 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6698071 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5372970 # Number of BTB hits +system.cpu.branchPred.lookups 11441088 # Number of BP lookups +system.cpu.branchPred.condPredicted 8207826 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765853 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6077536 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5340604 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.216677 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1174312 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.874494 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1173808 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20431374 # DTB read hits -system.cpu.dtb.read_misses 46957 # DTB read misses +system.cpu.dtb.read_hits 20417089 # DTB read hits +system.cpu.dtb.read_misses 43350 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20478331 # DTB read accesses -system.cpu.dtb.write_hits 6580300 # DTB write hits -system.cpu.dtb.write_misses 270 # DTB write misses +system.cpu.dtb.read_accesses 20460439 # DTB read accesses +system.cpu.dtb.write_hits 6579898 # DTB write hits +system.cpu.dtb.write_misses 278 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580570 # DTB write accesses -system.cpu.dtb.data_hits 27011674 # DTB hits -system.cpu.dtb.data_misses 47227 # DTB misses +system.cpu.dtb.write_accesses 6580176 # DTB write accesses +system.cpu.dtb.data_hits 26996987 # DTB hits +system.cpu.dtb.data_misses 43628 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27058901 # DTB accesses -system.cpu.itb.fetch_hits 23067346 # ITB hits -system.cpu.itb.fetch_misses 89 # ITB misses +system.cpu.dtb.data_accesses 27040615 # DTB accesses +system.cpu.itb.fetch_hits 22953519 # ITB hits +system.cpu.itb.fetch_misses 90 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23067435 # ITB accesses +system.cpu.itb.fetch_accesses 22953609 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,67 +293,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 104114013 # number of cpu cycles simulated +system.cpu.numCycles 103821213 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2234090 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2183676 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.132867 # CPI: cycles per instruction -system.cpu.ipc 0.882716 # IPC: instructions per cycle -system.cpu.tickCycles 102384742 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1729271 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.129681 # CPI: cycles per instruction +system.cpu.ipc 0.885205 # IPC: instructions per cycle +system.cpu.tickCycles 102104321 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1716892 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.483845 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26587292 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1447.424804 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26573200 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11922.552466 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11916.233184 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1448.483845 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353634 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353634 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424804 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353375 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353375 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53183674 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53183674 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20089099 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20089099 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 53155492 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53155492 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20075007 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20075007 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6498193 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6498193 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26587292 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26587292 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26587292 # number of overall hits -system.cpu.dcache.overall_hits::total 26587292 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 520 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 520 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 26573200 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26573200 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26573200 # number of overall hits +system.cpu.dcache.overall_hits::total 26573200 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 521 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 521 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2910 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2910 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3430 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses -system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40189000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40189000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 213917000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 213917000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 254106000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 254106000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 254106000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 254106000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20089619 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20089619 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3431 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3431 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3431 # number of overall misses +system.cpu.dcache.overall_misses::total 3431 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40212500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40212500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 214035000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 214035000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 254247500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 254247500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 254247500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 254247500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20075528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20075528 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26590722 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26590722 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26590722 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26590722 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26576631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26576631 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26576631 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26576631 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77286.538462 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77286.538462 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73510.996564 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73510.996564 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74083.381924 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74083.381924 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74083.381924 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74083.381924 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.546392 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.546392 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74103.031186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74103.031186 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,14 +380,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1165 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1165 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1200 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1201 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1201 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1201 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1201 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36729500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36729500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 130660500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 130660500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167390000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 167390000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167390000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 167390000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37107000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37107000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131707500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131707500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168814500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 168814500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168814500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 168814500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -412,69 +412,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75730.927835 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75730.927835 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74877.077364 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74877.077364 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75062.780269 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75062.780269 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75062.780269 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75062.780269 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75477.077364 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75477.077364 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13848 # number of replacements -system.cpu.icache.tags.tagsinuse 1641.495432 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23051532 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15813 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1457.758300 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13850 # number of replacements +system.cpu.icache.tags.tagsinuse 1640.456656 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22937703 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15815 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1450.376415 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.495432 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801511 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801511 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456656 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801004 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801004 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 668 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 950 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 671 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 946 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46150505 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46150505 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23051532 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23051532 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23051532 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23051532 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23051532 # number of overall hits -system.cpu.icache.overall_hits::total 23051532 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15814 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15814 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15814 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15814 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15814 # number of overall misses -system.cpu.icache.overall_misses::total 15814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 406574500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 406574500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 406574500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 406574500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 406574500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 406574500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23067346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23067346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23067346 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23067346 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23067346 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23067346 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25709.782471 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25709.782471 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25709.782471 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25709.782471 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25709.782471 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25709.782471 # average overall miss latency +system.cpu.icache.tags.tag_accesses 45922853 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45922853 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22937703 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22937703 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22937703 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22937703 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22937703 # number of overall hits +system.cpu.icache.overall_hits::total 22937703 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15816 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15816 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15816 # 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average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82035.879630 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73928.526349 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75876.104138 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74715.977444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73928.526349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75876.104138 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74715.977444 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.294763 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74937.172775 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74937.172775 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74684.343434 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74684.343434 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74684.343434 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76538.354254 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75434.104155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74684.343434 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76538.354254 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75434.104155 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -616,106 +616,106 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3169 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3169 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3168 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3168 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 432 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 432 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3168 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5320 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5319 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5320 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110580000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110580000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 202589500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 202589500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31119500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31119500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202589500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 141699500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 344289000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202589500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 141699500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 344289000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 5319 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111627000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111627000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204920000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204920000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31497000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31497000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143124000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 348044000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143124000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 348044000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200405 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200316 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.294851 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.294763 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.294851 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64328.097731 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64328.097731 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63928.526349 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63928.526349 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72035.879630 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72035.879630 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63928.526349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65876.104138 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64715.977444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63928.526349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65876.104138 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64715.977444 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.294763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64937.172775 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64937.172775 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64684.343434 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64684.343434 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 16298 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 13898 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 13900 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15813 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15815 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45474 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45480 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50091 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50097 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1161600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1161728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 32048 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 32052 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32048 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 32052 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 32048 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 16131000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 32052 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 16133000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23719500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 23722500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3601 # Transaction distribution +system.membus.trans_dist::ReadResp 3600 # Transaction distribution system.membus.trans_dist::ReadExReq 1719 # Transaction distribution system.membus.trans_dist::ReadExResp 1719 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3601 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10640 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10640 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 340480 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3600 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10638 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10638 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 340416 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5320 # Request fanout histogram +system.membus.snoop_fanout::samples 5319 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5320 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5319 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5320 # Request fanout histogram -system.membus.reqLayer0.occupancy 6410500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5319 # Request fanout histogram +system.membus.reqLayer0.occupancy 6413000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28166750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28165750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 4e01cb733..1d39a1715 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -150,7 +150,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -497,7 +497,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -546,7 +546,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 462b428af..a140d0429 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,13 +1,13 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 07:55:25 -gem5 started Apr 22 2015 08:19:48 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 21:18:12 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -24,4 +24,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 22228749500 because target called exit() +122 123 124 Exiting @ tick 21919473500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 2afb0af07..f7c0c31d6 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022173 # Number of seconds simulated -sim_ticks 22172615500 # Number of ticks simulated -final_tick 22172615500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021919 # Number of seconds simulated +sim_ticks 21919473500 # Number of ticks simulated +final_tick 21919473500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207826 # Simulator instruction rate (inst/s) -host_op_rate 207826 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54740698 # Simulator tick rate (ticks/s) -host_mem_usage 301824 # Number of bytes of host memory used -host_seconds 405.05 # Real time elapsed on the host +host_inst_rate 134628 # Simulator instruction rate (inst/s) +host_op_rate 134628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35055621 # Simulator tick rate (ticks/s) +host_mem_usage 296224 # Number of bytes of host memory used +host_seconds 625.28 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory -system.physmem.bytes_read::total 334656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196224 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3066 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5229 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8849836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6243377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15093213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8849836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8849836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8849836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6243377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15093213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5229 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 195776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory +system.physmem.bytes_read::total 334272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195776 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3059 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5223 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8931601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6318400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15250001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8931601 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8931601 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8931601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6318400 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15250001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5223 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5229 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5223 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334656 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334272 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334656 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334272 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 472 # Per bank write bursts +system.physmem.perBankRdBursts::0 470 # Per bank write bursts system.physmem.perBankRdBursts::1 290 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts -system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 217 # Per bank write bursts -system.physmem.perBankRdBursts::5 224 # Per bank write bursts -system.physmem.perBankRdBursts::6 217 # Per bank write bursts -system.physmem.perBankRdBursts::7 285 # Per bank write bursts +system.physmem.perBankRdBursts::3 523 # Per bank write bursts +system.physmem.perBankRdBursts::4 220 # Per bank write bursts +system.physmem.perBankRdBursts::5 223 # Per bank write bursts +system.physmem.perBankRdBursts::6 218 # Per bank write bursts +system.physmem.perBankRdBursts::7 288 # Per bank write bursts system.physmem.perBankRdBursts::8 239 # Per bank write bursts system.physmem.perBankRdBursts::9 278 # Per bank write bursts -system.physmem.perBankRdBursts::10 248 # Per bank write bursts -system.physmem.perBankRdBursts::11 253 # Per bank write bursts -system.physmem.perBankRdBursts::12 398 # Per bank write bursts +system.physmem.perBankRdBursts::10 249 # Per bank write bursts +system.physmem.perBankRdBursts::11 251 # Per bank write bursts +system.physmem.perBankRdBursts::12 396 # Per bank write bursts system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 493 # Per bank write bursts +system.physmem.perBankRdBursts::14 489 # Per bank write bursts system.physmem.perBankRdBursts::15 449 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22172520500 # Total gap between requests +system.physmem.totGap 21919378500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5229 # Read request sizes (log2) +system.physmem.readPktSize::6 5223 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 385.112399 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.773233 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 362.004147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 257 29.78% 29.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 196 22.71% 52.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 76 8.81% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.60% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 37 4.29% 72.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 34 3.94% 76.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 3.36% 79.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 50 5.79% 85.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 127 14.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 863 # Bytes accessed per row activation -system.physmem.totQLat 43111750 # Total ticks spent queuing -system.physmem.totMemAccLat 141155500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26145000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8244.74 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.497674 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 231.928894 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.454487 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 254 29.53% 29.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 187 21.74% 51.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 83 9.65% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 58 6.74% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 36 4.19% 71.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 34 3.95% 75.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 4.65% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 50 5.81% 86.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 118 13.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 860 # Bytes accessed per row activation +system.physmem.totQLat 44538500 # Total ticks spent queuing +system.physmem.totMemAccLat 142469750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8527.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26994.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27277.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.09 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.25 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4356 # Number of row buffer hits during reads +system.physmem.readRowHits 4358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.30 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4240298.43 # Average gap between requests -system.physmem.pageHitRate 83.30 # Row buffer hit rate, read and write combined +system.physmem.avgGap 4196702.76 # Average gap between requests +system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 3160080 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 1724250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19492200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 19741800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1447870320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 926205255 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12488167500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14886619605 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.545103 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20772765250 # Time in different power states -system.physmem_0.memoryStateTime::REF 740220000 # Time in different power states +system.physmem_0.refreshEnergy 1431596400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 935708580 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12330335250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14722266360 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.680556 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20510216250 # Time in different power states +system.physmem_0.memoryStateTime::REF 731900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 654868750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 676644750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3311280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1806750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20810400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20872800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1447870320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 909735390 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12502614750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14886148890 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.523868 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20796420250 # Time in different power states -system.physmem_1.memoryStateTime::REF 740220000 # Time in different power states +system.physmem_1.refreshEnergy 1431596400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 913464900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12349847250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14720946120 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.620322 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20542312250 # Time in different power states +system.physmem_1.memoryStateTime::REF 731900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 631087250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 644355250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16296711 # Number of BP lookups -system.cpu.branchPred.condPredicted 11841199 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 977322 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9230824 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7630427 # Number of BTB hits +system.cpu.branchPred.lookups 16112018 # Number of BP lookups +system.cpu.branchPred.condPredicted 11701868 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 926184 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8628002 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7529875 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.662469 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1605836 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 456 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.272523 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1595504 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 407 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24148862 # DTB read hits -system.cpu.dtb.read_misses 238971 # DTB read misses +system.cpu.dtb.read_hits 24062707 # DTB read hits +system.cpu.dtb.read_misses 205786 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 24387833 # DTB read accesses -system.cpu.dtb.write_hits 7164238 # DTB write hits -system.cpu.dtb.write_misses 1251 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 7165489 # DTB write accesses -system.cpu.dtb.data_hits 31313100 # DTB hits -system.cpu.dtb.data_misses 240222 # DTB misses -system.cpu.dtb.data_acv 3 # DTB access violations -system.cpu.dtb.data_accesses 31553322 # DTB accesses -system.cpu.itb.fetch_hits 16134293 # ITB hits -system.cpu.itb.fetch_misses 87 # ITB misses +system.cpu.dtb.read_accesses 24268493 # DTB read accesses +system.cpu.dtb.write_hits 7162407 # DTB write hits +system.cpu.dtb.write_misses 1203 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7163610 # DTB write accesses +system.cpu.dtb.data_hits 31225114 # DTB hits +system.cpu.dtb.data_misses 206989 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 31432103 # DTB accesses +system.cpu.itb.fetch_hits 15925407 # ITB hits +system.cpu.itb.fetch_misses 77 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 16134380 # ITB accesses +system.cpu.itb.fetch_accesses 15925484 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,239 +293,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 44345232 # number of cpu cycles simulated +system.cpu.numCycles 43838948 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16871286 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 139358892 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16296711 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9236263 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26208155 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2034698 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 152 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2379 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 16134293 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 382507 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44099332 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.160113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.432013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16632320 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137954260 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16112018 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9125379 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25989721 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1930958 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2266 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 15925407 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 365179 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43589931 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.164819 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433135 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19660436 44.58% 44.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2660444 6.03% 50.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1334517 3.03% 53.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1958294 4.44% 58.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3041312 6.90% 64.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1304304 2.96% 67.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1378179 3.13% 71.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 896078 2.03% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11865768 26.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19407451 44.52% 44.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2621129 6.01% 50.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1337584 3.07% 53.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1925835 4.42% 58.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3007413 6.90% 64.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1288266 2.96% 67.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1362128 3.12% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 884292 2.03% 73.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11755833 26.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44099332 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367496 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.142590 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13096074 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8205573 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19698619 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2093424 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1005642 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2679978 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12191 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 133453867 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 48806 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1005642 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14231650 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4726220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9532 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20537255 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3589033 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 129931841 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 72505 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1962504 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1321371 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 55153 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 95440121 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 168856219 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 161261081 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7595137 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43589931 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367527 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.146842 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12848398 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8248987 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19437203 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2101434 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 953909 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2651089 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11974 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132128383 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49953 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 953909 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13970899 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4649700 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10898 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20300581 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3703944 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128750721 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69632 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2039237 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1388591 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 55010 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94550726 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167277672 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159796203 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7481468 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27012760 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 775 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8114171 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 27101259 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8744711 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3477099 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1649521 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112647261 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1499 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 100144647 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 120164 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 28469050 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21866284 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1110 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44099332 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.270888 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.097444 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26123365 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 949 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8314647 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26912240 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8709829 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3514186 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1623457 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111857121 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1283 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99743085 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 115820 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27678694 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21106490 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 894 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43589931 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.288214 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099779 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11543505 26.18% 26.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7764590 17.61% 43.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7534716 17.09% 60.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5714671 12.96% 73.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4493321 10.19% 84.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2994712 6.79% 90.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2021459 4.58% 95.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1167850 2.65% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 864508 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11253194 25.82% 25.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7641118 17.53% 43.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7479948 17.16% 60.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5719610 13.12% 73.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4459621 10.23% 83.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2975044 6.83% 90.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2026173 4.65% 95.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1169285 2.68% 98.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 865938 1.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44099332 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43589931 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 476525 19.98% 19.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 437 0.02% 20.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34852 1.46% 21.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 11487 0.48% 21.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1008602 42.30% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 692685 29.05% 93.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159938 6.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 482162 20.24% 20.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 537 0.02% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34275 1.44% 21.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12320 0.52% 22.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1010506 42.41% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 685066 28.75% 93.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 157661 6.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60907964 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 491070 0.49% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2843610 2.84% 64.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115460 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2441189 2.44% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 314170 0.31% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 765827 0.76% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24997693 24.96% 92.74% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7267338 7.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60678292 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 490564 0.49% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2838989 2.85% 64.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115355 0.12% 64.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2438911 2.45% 66.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 313691 0.31% 67.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 766049 0.77% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24838081 24.90% 92.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7262827 7.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 100144647 # Type of FU issued -system.cpu.iq.rate 2.258296 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2384526 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023811 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 231229628 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131456710 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 90023404 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15663688 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9702849 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7180664 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 94162135 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8367031 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1912696 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99743085 # Type of FU issued +system.cpu.iq.rate 2.275216 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2382527 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023887 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229948900 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 130065304 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89786778 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15625548 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9512793 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7169302 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93776538 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8349067 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1917366 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7105061 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11423 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 42083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2243608 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6916042 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11056 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 41363 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2208726 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42789 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42784 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1527 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1005642 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3713444 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 450339 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 123646937 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 273080 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 27101259 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8744711 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1499 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 41770 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 401874 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 42083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 559712 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 524057 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1083769 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98766968 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24388350 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1377679 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 953909 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3616734 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 464700 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122788755 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 239982 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26912240 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8709829 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1283 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38454 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 420547 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 41363 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 525246 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502956 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1028202 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98432500 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24268972 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1310585 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10998177 # number of nop insts executed -system.cpu.iew.exec_refs 31553871 # number of memory reference insts executed -system.cpu.iew.exec_branches 12528994 # Number of branches executed -system.cpu.iew.exec_stores 7165521 # Number of stores executed -system.cpu.iew.exec_rate 2.227229 # Inst execution rate -system.cpu.iew.wb_sent 97952857 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 97204068 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67107593 # num instructions producing a value -system.cpu.iew.wb_consumers 95129025 # num instructions consuming a value +system.cpu.iew.exec_nop 10930351 # number of nop insts executed +system.cpu.iew.exec_refs 31432616 # number of memory reference insts executed +system.cpu.iew.exec_branches 12487704 # Number of branches executed +system.cpu.iew.exec_stores 7163644 # Number of stores executed +system.cpu.iew.exec_rate 2.245321 # Inst execution rate +system.cpu.iew.wb_sent 97645732 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96956080 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66985594 # num instructions producing a value +system.cpu.iew.wb_consumers 95002941 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.191985 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705438 # average fanout of values written-back +system.cpu.iew.wb_rate 2.211642 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705090 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 31745312 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 30887581 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 965615 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39467684 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.328565 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.908680 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 914614 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39095972 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.350704 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.921132 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14970260 37.93% 37.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8589907 21.76% 59.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3909988 9.91% 69.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1952996 4.95% 74.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1374473 3.48% 78.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1034336 2.62% 80.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 694993 1.76% 82.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 731194 1.85% 84.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6209537 15.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14698430 37.60% 37.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8547015 21.86% 59.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3864183 9.88% 69.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1929221 4.93% 74.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1372371 3.51% 77.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1004316 2.57% 80.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 690404 1.77% 82.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 733733 1.88% 84.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6256299 16.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39467684 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39095972 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,350 +570,350 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6209537 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 156905474 # The number of ROB reads -system.cpu.rob.rob_writes 251988235 # The number of ROB writes -system.cpu.timesIdled 4640 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 245900 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6256299 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155629269 # The number of ROB reads +system.cpu.rob.rob_writes 250130763 # The number of ROB writes +system.cpu.timesIdled 4629 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 249017 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.526792 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.526792 # CPI: Total CPI of All Threads -system.cpu.ipc 1.898281 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.898281 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133413106 # number of integer regfile reads -system.cpu.int_regfile_writes 73139309 # number of integer regfile writes -system.cpu.fp_regfile_reads 6258544 # number of floating regfile reads -system.cpu.fp_regfile_writes 6168597 # number of floating regfile writes -system.cpu.misc_regfile_reads 718994 # number of misc regfile reads +system.cpu.cpi 0.520778 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520778 # CPI: Total CPI of All Threads +system.cpu.ipc 1.920204 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.920204 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 132982273 # number of integer regfile reads +system.cpu.int_regfile_writes 72919705 # number of integer regfile writes +system.cpu.fp_regfile_reads 6252521 # number of floating regfile reads +system.cpu.fp_regfile_writes 6155462 # number of floating regfile writes +system.cpu.misc_regfile_reads 719143 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 159 # number of replacements -system.cpu.dcache.tags.tagsinuse 1454.905467 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28683797 # Total number of references to valid blocks. +system.cpu.dcache.tags.replacements 158 # number of replacements +system.cpu.dcache.tags.tagsinuse 1457.350779 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28592916 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2244 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12782.440731 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12741.941176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1454.905467 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355202 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355202 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1386 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57388820 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57388820 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22190893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22190893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492625 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492625 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 279 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 279 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28683518 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28683518 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28683518 # number of overall hits -system.cpu.dcache.overall_hits::total 28683518 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1012 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1012 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8478 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8478 # number of WriteReq misses +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.350779 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355799 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355799 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2086 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509277 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57207152 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57207152 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22099846 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22099846 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492613 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492613 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28592459 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28592459 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28592459 # number of overall hits +system.cpu.dcache.overall_hits::total 28592459 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1047 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1047 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8490 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8490 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9490 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9490 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9490 # number of overall misses -system.cpu.dcache.overall_misses::total 9490 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 67994000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 67994000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 547632747 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 547632747 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9537 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9537 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9537 # number of overall misses +system.cpu.dcache.overall_misses::total 9537 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 69532500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 69532500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 543709251 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 543709251 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 615626747 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 615626747 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 615626747 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 615626747 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22191905 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22191905 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 613241751 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 613241751 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 613241751 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 613241751 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22100893 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22100893 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 280 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 280 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28693008 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28693008 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28693008 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28693008 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003571 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003571 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000331 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000331 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000331 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000331 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67187.747036 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67187.747036 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64594.567941 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64594.567941 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 458 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 458 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28601996 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28601996 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28601996 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28601996 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001306 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002183 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002183 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000333 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000333 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000333 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000333 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66411.174785 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66411.174785 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64041.136749 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64041.136749 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64871.100843 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64871.100843 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64871.100843 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64871.100843 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33428 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 398 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.989950 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64301.326518 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64301.326518 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64301.326518 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64301.326518 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32746 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 127 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 389 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 84.179949 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 63.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109 # number of writebacks -system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 503 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 503 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6744 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6744 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7247 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7247 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7247 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7247 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 509 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 509 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 540 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6754 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6754 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7294 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7294 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7294 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7294 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 507 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 507 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1736 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1736 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39245500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39245500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 137397495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 137397495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39700000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39700000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135151495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 135151495 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176642995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 176642995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176642995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 176642995 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 174851495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 174851495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 174851495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 174851495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003571 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003571 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002183 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002183 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77103.143418 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77103.143418 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79237.309689 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79237.309689 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78303.747535 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78303.747535 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77852.243664 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77852.243664 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78753.007133 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78753.007133 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78753.007133 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78753.007133 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77954.300045 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77954.300045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77954.300045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77954.300045 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 9772 # number of replacements -system.cpu.icache.tags.tagsinuse 1599.606485 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 16119452 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11709 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1376.671962 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9477 # number of replacements +system.cpu.icache.tags.tagsinuse 1601.339074 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15910864 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11414 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1393.977922 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1599.606485 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781058 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1601.339074 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781904 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781904 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 934 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 32280293 # Number of tag accesses -system.cpu.icache.tags.data_accesses 32280293 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 16119452 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 16119452 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 16119452 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 16119452 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 16119452 # number of overall hits -system.cpu.icache.overall_hits::total 16119452 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14840 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14840 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14840 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14840 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14840 # number of overall misses -system.cpu.icache.overall_misses::total 14840 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 447595000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 447595000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 447595000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 447595000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 447595000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 447595000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 16134292 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 16134292 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 16134292 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 16134292 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 16134292 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 16134292 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000920 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000920 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000920 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000920 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000920 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000920 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30161.388140 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30161.388140 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30161.388140 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30161.388140 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30161.388140 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30161.388140 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 223 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 31862226 # Number of tag accesses +system.cpu.icache.tags.data_accesses 31862226 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 15910864 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15910864 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15910864 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15910864 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15910864 # number of overall hits +system.cpu.icache.overall_hits::total 15910864 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14542 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14542 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14542 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14542 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14542 # number of overall misses +system.cpu.icache.overall_misses::total 14542 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 447928500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 447928500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 447928500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 447928500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 447928500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 447928500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15925406 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15925406 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15925406 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15925406 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15925406 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15925406 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000913 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000913 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000913 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000913 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000913 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000913 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30802.399945 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30802.399945 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30802.399945 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30802.399945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30802.399945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30802.399945 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 837 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 209.250000 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76375.776398 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84666.299559 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84666.299559 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76375.776398 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78822.088725 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77389.335631 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76375.776398 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78822.088725 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77389.335631 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -923,108 +922,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1708 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1708 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3066 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3066 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 455 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 455 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3066 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2163 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5229 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3066 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5229 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 117301000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 117301000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200218000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200218000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33419000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33419000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200218000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 150720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 350938000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200218000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 150720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 350938000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.261850 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.261850 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.892157 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.892157 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.261850 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.374758 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.261850 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.374758 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68677.400468 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68677.400468 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65302.674494 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65302.674494 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73448.351648 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73448.351648 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65302.674494 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69680.998613 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67113.788487 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65302.674494 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69680.998613 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67113.788487 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1710 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1710 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3059 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3059 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 454 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 454 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3059 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2164 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5223 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3059 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2164 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5223 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115032500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115032500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 203043500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 203043500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33898500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33898500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 203043500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148931000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 351974500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 203043500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148931000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 351974500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985023 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985023 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.268004 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.893701 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.893701 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.382413 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.382413 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67270.467836 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67270.467836 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66375.776398 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66375.776398 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74666.299559 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74666.299559 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66375.776398 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66375.776398 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 12219 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 9822 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11709 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 510 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33190 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4647 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 37837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 749376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 899968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 11922 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 9527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1736 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1736 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 508 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32305 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4646 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 36951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 881024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23884 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 23293 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 23884 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 23293 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23884 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12051000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23293 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 11754500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17563500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17121000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3366000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3521 # Transaction distribution -system.membus.trans_dist::ReadExReq 1708 # Transaction distribution -system.membus.trans_dist::ReadExResp 1708 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3521 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10458 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10458 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334656 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3513 # Transaction distribution +system.membus.trans_dist::ReadExReq 1710 # Transaction distribution +system.membus.trans_dist::ReadExResp 1710 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3513 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10446 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334272 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5229 # Request fanout histogram +system.membus.snoop_fanout::samples 5223 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5229 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5223 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5229 # Request fanout histogram -system.membus.reqLayer0.occupancy 6267000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5223 # Request fanout histogram +system.membus.reqLayer0.occupancy 6235500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27480000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27428750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |