diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha')
4 files changed, 991 insertions, 884 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 17c346b69..bb082f445 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041684 # Number of seconds simulated -sim_ticks 41683573000 # Number of ticks simulated -final_tick 41683573000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041682 # Number of seconds simulated +sim_ticks 41681685000 # Number of ticks simulated +final_tick 41681685000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119929 # Simulator instruction rate (inst/s) -host_op_rate 119929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54395175 # Simulator tick rate (ticks/s) -host_mem_usage 269084 # Number of bytes of host memory used -host_seconds 766.31 # Real time elapsed on the host +host_inst_rate 117228 # Simulator instruction rate (inst/s) +host_op_rate 117228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53167547 # Simulator tick rate (ticks/s) +host_mem_usage 270132 # Number of bytes of host memory used +host_seconds 783.97 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4289843 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3291848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7581692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4289843 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4289843 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4289843 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3291848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7581692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4290038 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3291997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7582035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4290038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4290038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4290038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3291997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7582035 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 41683192000 # Total gap between requests +system.physmem.totGap 41681611000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 3265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 74 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,28 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 284 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 541.521127 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 335.427822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.351632 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 58 20.42% 20.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 54 19.01% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24 8.45% 47.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12 4.23% 52.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 10 3.52% 55.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9 3.17% 58.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 1.76% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 1.76% 62.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 107 37.68% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 284 # Bytes accessed per row activation -system.physmem.totQLat 37971250 # Total ticks spent queuing -system.physmem.totMemAccLat 131493750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 856 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 367.551402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 223.659981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 343.121338 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 258 30.14% 30.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 183 21.38% 51.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95 11.10% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 7.36% 69.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 46 5.37% 75.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 30 3.50% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 51 5.96% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 22 2.57% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 108 12.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 856 # Bytes accessed per row activation +system.physmem.totQLat 35422000 # Total ticks spent queuing +system.physmem.totMemAccLat 128009500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers -system.physmem.totBankLat 68832500 # Total ticks spent accessing banks -system.physmem.avgQLat 7689.60 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13939.35 # Average bank access latency per DRAM burst +system.physmem.avgQLat 7173.35 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26628.95 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25923.35 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s @@ -218,14 +216,18 @@ system.physmem.busUtilRead 0.06 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4086 # Number of row buffer hits during reads +system.physmem.readRowHits 4077 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.75 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8441310.65 # Average gap between requests -system.physmem.pageHitRate 82.75 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 7581692 # Throughput (bytes/s) +system.physmem.avgGap 8440990.48 # Average gap between requests +system.physmem.pageHitRate 82.56 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 39211333500 # Time in different power states +system.physmem.memoryStateTime::REF 1391780000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1076956500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 7582035 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3216 # Transaction distribution system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution @@ -236,40 +238,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5782000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 45941000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 45945000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 13412627 # Number of BP lookups +system.cpu.branchPred.lookups 13412628 # Number of BP lookups system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 7424479 # Number of BTB lookups -system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits +system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups +system.cpu.branchPred.BTBHits 3768498 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.757730 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 50.757737 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996264 # DTB read hits +system.cpu.dtb.read_hits 19996260 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996274 # DTB read accesses -system.cpu.dtb.write_hits 6501866 # DTB write hits +system.cpu.dtb.read_accesses 19996270 # DTB read accesses +system.cpu.dtb.write_hits 6501862 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501889 # DTB write accesses -system.cpu.dtb.data_hits 26498130 # DTB hits +system.cpu.dtb.write_accesses 6501885 # DTB write accesses +system.cpu.dtb.data_hits 26498122 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498163 # DTB accesses -system.cpu.itb.fetch_hits 9956950 # ITB hits +system.cpu.dtb.data_accesses 26498155 # DTB accesses +system.cpu.itb.fetch_hits 9956951 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9956999 # ITB accesses +system.cpu.itb.fetch_accesses 9957000 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -283,10 +285,10 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83367147 # number of cpu cycles simulated +system.cpu.numCycles 83363371 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 5905663 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 73570553 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File @@ -305,12 +307,12 @@ system.cpu.execution_unit.executions 57404027 # Nu system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82970332 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970271 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10410 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7759392 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607755 # Number of cycles cpu stages are processed. -system.cpu.activity 90.692506 # Percentage of cycles cpu is active +system.cpu.timesIdled 10393 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7755613 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607758 # Number of cycles cpu stages are processed. +system.cpu.activity 90.696618 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -322,36 +324,36 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.907121 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.907079 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.907121 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102389 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.907079 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102439 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.102389 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27686803 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680344 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.789312 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34115467 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251680 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.078044 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33515800 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.102439 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27683021 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680350 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.792345 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34111687 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.080725 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33512024 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 49851347 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.797353 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65340657 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026490 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.623014 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29507392 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 59.800061 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65336871 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026500 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.624006 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29503616 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 53859755 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.605491 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 64.608418 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 7635 # number of replacements -system.cpu.icache.tags.tagsinuse 1492.188372 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1492.194030 # Cycle average of tags in use system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1492.188372 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.728608 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.728608 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1492.194030 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.728610 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.728610 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1885 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id @@ -359,44 +361,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 613 system.cpu.icache.tags.age_task_id_blocks_1024::3 136 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 959 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.920410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 19923420 # Number of tag accesses -system.cpu.icache.tags.data_accesses 19923420 # Number of data accesses +system.cpu.icache.tags.tag_accesses 19923422 # Number of tag accesses +system.cpu.icache.tags.data_accesses 19923422 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits system.cpu.icache.overall_hits::total 9945551 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11399 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11399 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11399 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses -system.cpu.icache.overall_misses::total 11399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 329283500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 329283500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 329283500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 329283500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 329283500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 329283500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9956950 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9956950 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9956950 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 11400 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11400 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11400 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11400 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11400 # number of overall misses +system.cpu.icache.overall_misses::total 11400 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 327908250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 327908250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 327908250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 327908250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 327908250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 327908250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9956951 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9956951 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9956951 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9956951 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9956951 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9956951 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28887.051496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28887.051496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28887.051496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28887.051496 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28763.881579 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28763.881579 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28763.881579 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28763.881579 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28763.881579 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28763.881579 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -405,38 +407,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1880 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1880 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1880 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1880 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1880 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1880 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268822750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 268822750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268822750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 268822750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268822750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 268822750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268503000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 268503000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268503000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 268503000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268503000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 268503000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28237.683824 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28237.683824 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28204.096639 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28204.096639 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28204.096639 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28204.096639 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28204.096639 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28204.096639 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 18194218 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 18195042 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -452,21 +454,21 @@ system.cpu.toL2Bus.data_through_bus 758400 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 14800250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 14805000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3515750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3522500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2189.597840 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2189.603987 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.844631 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.766792 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986416 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.844250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.772066 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 350.987671 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055566 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.066821 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3282 # Occupied blocks per task id @@ -502,17 +504,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191765250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32319750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 224085000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125611500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 125611500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 191765250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 157931250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 349696500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 191765250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 157931250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 349696500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191445500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31242750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 222688250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 121662250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 121662250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 191445500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 152905000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 344350500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 191445500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 152905000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 344350500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -537,17 +539,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68634.663565 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76587.085308 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69678.171642 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72945.121951 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72945.121951 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70817.436209 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70817.436209 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68520.221904 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74034.952607 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69243.858831 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70651.713124 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70651.713124 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68520.221904 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71317.630597 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69734.811665 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68520.221904 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71317.630597 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69734.811665 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -567,17 +569,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156642750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27057250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 183700000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104540000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104540000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156642750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131597250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 288240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156642750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131597250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 288240000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156316500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25982750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 182299250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100579250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100579250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156316500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 126562000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 282878500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156316500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 126562000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 282878500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -589,25 +591,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56063.976378 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64116.706161 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57120.646766 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60708.478513 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60708.478513 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55947.208304 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61570.497630 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56685.090174 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58408.391405 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58408.391405 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55947.208304 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59030.783582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57286.046983 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55947.208304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59030.783582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57286.046983 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.382253 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26488456 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1441.383569 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26488452 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11915.634728 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.632928 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.382253 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.383569 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.351900 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.351900 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id @@ -619,30 +621,30 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492835 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492835 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488456 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488456 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488456 # number of overall hits -system.cpu.dcache.overall_hits::total 26488456 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 577 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 577 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8268 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8268 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8845 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8845 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8845 # number of overall misses -system.cpu.dcache.overall_misses::total 8845 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40979500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40979500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 507652000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 507652000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 548631500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 548631500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 548631500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 548631500 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 19995619 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995619 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492833 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492833 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488452 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488452 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488452 # number of overall hits +system.cpu.dcache.overall_hits::total 26488452 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 579 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 579 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8270 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8270 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8849 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8849 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8849 # number of overall misses +system.cpu.dcache.overall_misses::total 8849 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39903000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39903000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 493053000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 493053000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 532956000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 532956000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 532956000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 532956000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -659,32 +661,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71021.663778 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71021.663778 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61399.612966 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61399.612966 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62027.303561 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62027.303561 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25755 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68917.098446 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68917.098446 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59619.467956 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59619.467956 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60227.822353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60227.822353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60227.822353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60227.822353 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 844 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 836 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.515403 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.770335 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6520 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6520 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6622 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6622 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6622 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6622 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6522 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6522 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6626 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6626 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6626 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6626 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -693,14 +695,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33343250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33343250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127629000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 127629000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160972250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 160972250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160972250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 160972250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32266250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32266250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 123679750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 123679750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155946000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 155946000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155946000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 155946000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -709,14 +711,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70196.315789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70196.315789 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73014.302059 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73014.302059 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67928.947368 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67928.947368 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70755.005721 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70755.005721 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70151.147099 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70151.147099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70151.147099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70151.147099 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index c3a9e9ab9..c2ef654cc 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023455 # Number of seconds simulated -sim_ticks 23455364500 # Number of ticks simulated -final_tick 23455364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023496 # Number of seconds simulated +sim_ticks 23495860500 # Number of ticks simulated +final_tick 23495860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164985 # Simulator instruction rate (inst/s) -host_op_rate 164985 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45970553 # Simulator tick rate (ticks/s) -host_mem_usage 272156 # Number of bytes of host memory used -host_seconds 510.23 # Real time elapsed on the host +host_inst_rate 162171 # Simulator instruction rate (inst/s) +host_op_rate 162171 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45264552 # Simulator tick rate (ticks/s) +host_mem_usage 273204 # Number of bytes of host memory used +host_seconds 519.08 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory -system.physmem.bytes_read::total 334592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8354933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5910119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14265052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8354933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8354933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8354933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5910119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14265052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5228 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory +system.physmem.bytes_read::total 334528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8345981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5891761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14237742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8345981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8345981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8345981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5891761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14237742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5227 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334592 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334592 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 469 # Per bank write bursts -system.physmem.perBankRdBursts::1 290 # Per bank write bursts -system.physmem.perBankRdBursts::2 301 # Per bank write bursts -system.physmem.perBankRdBursts::3 519 # Per bank write bursts +system.physmem.perBankRdBursts::1 291 # Per bank write bursts +system.physmem.perBankRdBursts::2 302 # Per bank write bursts +system.physmem.perBankRdBursts::3 524 # Per bank write bursts system.physmem.perBankRdBursts::4 220 # Per bank write bursts -system.physmem.perBankRdBursts::5 227 # Per bank write bursts +system.physmem.perBankRdBursts::5 226 # Per bank write bursts system.physmem.perBankRdBursts::6 220 # Per bank write bursts -system.physmem.perBankRdBursts::7 288 # Per bank write bursts +system.physmem.perBankRdBursts::7 285 # Per bank write bursts system.physmem.perBankRdBursts::8 236 # Per bank write bursts -system.physmem.perBankRdBursts::9 278 # Per bank write bursts +system.physmem.perBankRdBursts::9 280 # Per bank write bursts system.physmem.perBankRdBursts::10 248 # Per bank write bursts -system.physmem.perBankRdBursts::11 255 # Per bank write bursts -system.physmem.perBankRdBursts::12 401 # Per bank write bursts -system.physmem.perBankRdBursts::13 338 # Per bank write bursts +system.physmem.perBankRdBursts::11 254 # Per bank write bursts +system.physmem.perBankRdBursts::12 398 # Per bank write bursts +system.physmem.perBankRdBursts::13 336 # Per bank write bursts system.physmem.perBankRdBursts::14 491 # Per bank write bursts system.physmem.perBankRdBursts::15 447 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23455237500 # Total gap between requests +system.physmem.totGap 23495733500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5228 # Read request sizes (log2) +system.physmem.readPktSize::6 5227 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,90 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 339 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.348083 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 311.933424 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 425.197716 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 81 23.89% 23.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 64 18.88% 42.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 21 6.19% 48.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 17 5.01% 53.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 9 2.65% 56.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 2.36% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7 2.06% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 0.88% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 129 38.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 339 # Bytes accessed per row activation -system.physmem.totQLat 42838250 # Total ticks spent queuing -system.physmem.totMemAccLat 141220750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers -system.physmem.totBankLat 72242500 # Total ticks spent accessing banks -system.physmem.avgQLat 8194.00 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13818.38 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 383.188005 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 230.923786 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 354.572905 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 252 29.07% 29.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 197 22.72% 51.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 79 9.11% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 6.57% 67.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 42 4.84% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 41 4.73% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 51 5.88% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 24 2.77% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 124 14.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 867 # Bytes accessed per row activation +system.physmem.totQLat 41053500 # Total ticks spent queuing +system.physmem.totMemAccLat 139059750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7854.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27012.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26604.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.11 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4346 # Number of row buffer hits during reads +system.physmem.readRowHits 4351 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.13 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.24 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4486464.71 # Average gap between requests -system.physmem.pageHitRate 83.13 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.10 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 14265052 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3523 # Transaction distribution -system.membus.trans_dist::ReadResp 3523 # Transaction distribution +system.physmem.avgGap 4495070.50 # Average gap between requests +system.physmem.pageHitRate 83.24 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 21787630000 # Time in different power states +system.physmem.memoryStateTime::REF 784420000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 919340000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 14237742 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3522 # Transaction distribution +system.membus.trans_dist::ReadResp 3522 # Transaction distribution system.membus.trans_dist::ReadExReq 1705 # Transaction distribution system.membus.trans_dist::ReadExResp 1705 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10456 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10456 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 334592 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6760500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6755000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48963750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 48973500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14848335 # Number of BP lookups -system.cpu.branchPred.condPredicted 10770516 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 922016 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8296689 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6955595 # Number of BTB hits +system.cpu.branchPred.lookups 14867597 # Number of BP lookups +system.cpu.branchPred.condPredicted 10786733 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 927657 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8507235 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6975722 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.835793 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1468520 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3112 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.997523 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1468896 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3134 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23116922 # DTB read hits -system.cpu.dtb.read_misses 193562 # DTB read misses -system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 23310484 # DTB read accesses -system.cpu.dtb.write_hits 7068693 # DTB write hits -system.cpu.dtb.write_misses 1118 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 7069811 # DTB write accesses -system.cpu.dtb.data_hits 30185615 # DTB hits -system.cpu.dtb.data_misses 194680 # DTB misses -system.cpu.dtb.data_acv 6 # DTB access violations -system.cpu.dtb.data_accesses 30380295 # DTB accesses -system.cpu.itb.fetch_hits 14732180 # ITB hits -system.cpu.itb.fetch_misses 100 # ITB misses +system.cpu.dtb.read_hits 23141508 # DTB read hits +system.cpu.dtb.read_misses 194908 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 23336416 # DTB read accesses +system.cpu.dtb.write_hits 7073051 # DTB write hits +system.cpu.dtb.write_misses 1111 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 7074162 # DTB write accesses +system.cpu.dtb.data_hits 30214559 # DTB hits +system.cpu.dtb.data_misses 196019 # DTB misses +system.cpu.dtb.data_acv 3 # DTB access violations +system.cpu.dtb.data_accesses 30410578 # DTB accesses +system.cpu.itb.fetch_hits 14761442 # ITB hits +system.cpu.itb.fetch_misses 106 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14732280 # ITB accesses +system.cpu.itb.fetch_accesses 14761548 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -283,238 +285,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46910730 # number of cpu cycles simulated +system.cpu.numCycles 46991722 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15458006 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126949517 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14848335 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8424115 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22129467 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4471319 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5547804 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2176 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 15493602 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127144789 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14867597 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8444618 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22164191 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4494518 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5543985 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 114 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2326 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14732180 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 325492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46652781 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.721156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376288 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 14761442 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 326314 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46736650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.720451 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.375825 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24523314 52.57% 52.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2362460 5.06% 57.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1191709 2.55% 60.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1744531 3.74% 63.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2756035 5.91% 69.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1149513 2.46% 72.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1216156 2.61% 74.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 771099 1.65% 76.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10937964 23.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24572459 52.58% 52.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2364267 5.06% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1190852 2.55% 60.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1750659 3.75% 63.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2760354 5.91% 69.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1155374 2.47% 72.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1219764 2.61% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 773397 1.65% 76.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10949524 23.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46652781 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316523 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.706194 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17279755 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4249359 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20525557 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1094653 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3503457 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2516236 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12079 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123971467 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3503457 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18421615 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 960025 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8092 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20456033 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3303559 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121144333 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 76 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 398869 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2427038 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88958437 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157404324 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150359413 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7044910 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46736650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316388 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.705685 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17320813 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4244089 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20558459 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1092640 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3520649 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2518881 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12242 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 124135665 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32164 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3520649 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18467014 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 956444 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7682 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20482522 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3302339 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121292511 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 405307 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2418029 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89077183 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157604141 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 150534696 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7069444 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20531076 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 753 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 746 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8762869 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25364686 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8245053 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2579677 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 916866 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105436349 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1901 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96572685 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 177506 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20788885 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15603704 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1512 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46652781 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.070031 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.877189 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20649822 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 718 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 707 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8775432 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25394818 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8253633 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2570331 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 907077 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105549830 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2075 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96657653 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 179218 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20902238 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15662437 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1686 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46736650 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.068134 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876130 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12130850 26.00% 26.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9330795 20.00% 46.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8389374 17.98% 63.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6281972 13.47% 77.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4924466 10.56% 88.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2864469 6.14% 94.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1724344 3.70% 97.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 801135 1.72% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 205376 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12165151 26.03% 26.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9350062 20.01% 46.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8404811 17.98% 64.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6298333 13.48% 77.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4922419 10.53% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2869013 6.14% 94.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1725015 3.69% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 796629 1.70% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 205217 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46652781 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46736650 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 187827 11.99% 11.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 195 0.01% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7087 0.45% 12.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5615 0.36% 12.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 842803 53.78% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445934 28.46% 95.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77665 4.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 189767 12.10% 12.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 186 0.01% 12.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7209 0.46% 12.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5897 0.38% 12.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843167 53.74% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445094 28.37% 95.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77619 4.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58739096 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479860 0.50% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2798014 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115391 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386555 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 310970 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759904 0.79% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23830824 24.68% 92.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7151745 7.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58783696 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479813 0.50% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2802274 2.90% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115457 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387860 2.47% 66.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311147 0.32% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 760157 0.79% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23859982 24.69% 92.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7156941 7.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96572685 # Type of FU issued -system.cpu.iq.rate 2.058648 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1567126 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016227 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226432918 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117523015 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87074868 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15109865 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8738386 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7061397 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90154911 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7984893 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1517468 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96657653 # Type of FU issued +system.cpu.iq.rate 2.056908 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1568939 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226667825 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117702286 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87133167 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15132288 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8786528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7070448 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90230128 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7996457 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1520956 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5368488 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18513 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34393 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1743950 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5398620 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18484 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34785 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1752530 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10556 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2089 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10530 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2127 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3503457 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 134155 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17977 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115673905 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 371989 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25364686 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8245053 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1901 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2671 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34393 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 533358 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 495038 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1028396 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95341973 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23310954 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1230712 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3520649 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133897 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18217 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115793083 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 374761 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25394818 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8253633 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2075 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2932 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 43 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34785 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 541104 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 495336 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1036440 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95417746 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23336859 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1239907 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10235655 # number of nop insts executed -system.cpu.iew.exec_refs 30380968 # number of memory reference insts executed -system.cpu.iew.exec_branches 12023807 # Number of branches executed -system.cpu.iew.exec_stores 7070014 # Number of stores executed -system.cpu.iew.exec_rate 2.032413 # Inst execution rate -system.cpu.iew.wb_sent 94656410 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94136265 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64475750 # num instructions producing a value -system.cpu.iew.wb_consumers 89852391 # num instructions consuming a value +system.cpu.iew.exec_nop 10241178 # number of nop insts executed +system.cpu.iew.exec_refs 30411225 # number of memory reference insts executed +system.cpu.iew.exec_branches 12030179 # Number of branches executed +system.cpu.iew.exec_stores 7074366 # Number of stores executed +system.cpu.iew.exec_rate 2.030522 # Inst execution rate +system.cpu.iew.wb_sent 94727613 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94203615 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64511907 # num instructions producing a value +system.cpu.iew.wb_consumers 89904657 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.006711 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717574 # average fanout of values written-back +system.cpu.iew.wb_rate 2.004685 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717559 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23771863 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23891142 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 910264 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43149324 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.129884 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.746526 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 915882 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43216001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.126598 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.743951 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16704227 38.71% 38.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9920088 22.99% 61.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4481212 10.39% 72.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2253745 5.22% 77.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1606057 3.72% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1123881 2.60% 83.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722151 1.67% 85.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 820935 1.90% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5517028 12.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16755601 38.77% 38.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9919008 22.95% 61.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4484606 10.38% 72.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2269127 5.25% 77.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1610437 3.73% 81.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1128955 2.61% 83.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722092 1.67% 85.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 821021 1.90% 87.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5505154 12.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43149324 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43216001 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -525,230 +527,264 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5517028 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 51001542 55.49% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2732464 2.97% 67.37% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 19996198 21.76% 92.93% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction +system.cpu.commit.bw_lim_events 5505154 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153306174 # The number of ROB reads -system.cpu.rob.rob_writes 234877097 # The number of ROB writes -system.cpu.timesIdled 5272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 257949 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153504004 # The number of ROB reads +system.cpu.rob.rob_writes 235133069 # The number of ROB writes +system.cpu.timesIdled 5418 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 255072 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.557269 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.557269 # CPI: Total CPI of All Threads -system.cpu.ipc 1.794466 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.794466 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129050731 # number of integer regfile reads -system.cpu.int_regfile_writes 70522819 # number of integer regfile writes -system.cpu.fp_regfile_reads 6187407 # number of floating regfile reads -system.cpu.fp_regfile_writes 6043154 # number of floating regfile writes -system.cpu.misc_regfile_reads 714454 # number of misc regfile reads +system.cpu.cpi 0.558231 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.558231 # CPI: Total CPI of All Threads +system.cpu.ipc 1.791373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.791373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129151691 # number of integer regfile reads +system.cpu.int_regfile_writes 70572840 # number of integer regfile writes +system.cpu.fp_regfile_reads 6193374 # number of floating regfile reads +system.cpu.fp_regfile_writes 6052358 # number of floating regfile writes +system.cpu.misc_regfile_reads 714605 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37351626 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 11849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 11849 # Transaction distribution +system.cpu.toL2Bus.throughput 37684936 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 11995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 11995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27269 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 876096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 876096 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22964 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4597 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27561 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 885440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 885440 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 6953500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 7026500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17562000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17802750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3539750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3545000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9398 # number of replacements -system.cpu.icache.tags.tagsinuse 1599.250917 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14718111 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11333 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1298.695050 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9548 # number of replacements +system.cpu.icache.tags.tagsinuse 1597.278061 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14747183 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11482 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1284.374064 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1599.250917 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.780884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.780884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1935 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1597.278061 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.779921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.779921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1934 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 760 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 929 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.944824 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 29475691 # Number of tag accesses -system.cpu.icache.tags.data_accesses 29475691 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 14718111 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14718111 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14718111 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14718111 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14718111 # number of overall hits -system.cpu.icache.overall_hits::total 14718111 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14068 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14068 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14068 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14068 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14068 # number of overall misses -system.cpu.icache.overall_misses::total 14068 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413989500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413989500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413989500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413989500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413989500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413989500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14732179 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14732179 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14732179 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14732179 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14732179 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14732179 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000955 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000955 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000955 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000955 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000955 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000955 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29427.743816 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29427.743816 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29427.743816 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29427.743816 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29427.743816 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29427.743816 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 165 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.944336 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 29534364 # Number of tag accesses +system.cpu.icache.tags.data_accesses 29534364 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 14747183 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14747183 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14747183 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14747183 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14747183 # number of overall hits +system.cpu.icache.overall_hits::total 14747183 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14258 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14258 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14258 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14258 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14258 # number of overall misses +system.cpu.icache.overall_misses::total 14258 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 414157250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 414157250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 414157250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 414157250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 414157250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 414157250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14761441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14761441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14761441 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14761441 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14761441 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14761441 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000966 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000966 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000966 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000966 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73264.216366 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70609.814425 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -757,187 +793,186 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3062 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3523 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3064 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3522 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1705 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1705 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3062 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2166 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5228 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 172480500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30915000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 203395500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104707750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104707750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172480500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 135622750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 308103250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172480500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 135622750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 308103250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.297325 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3064 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2163 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5227 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3064 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171789000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30123000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201912000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101752000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101752000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171789000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131875000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 303664000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171789000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131875000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 303664000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266852 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293622 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.384978 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.384978 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56329.359895 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67060.737527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.607721 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61412.170088 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61412.170088 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56329.359895 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62614.381348 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.291890 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56329.359895 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62614.381348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.291890 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266852 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.380810 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266852 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.380810 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56066.906005 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65770.742358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57328.790460 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59678.592375 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59678.592375 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56066.906005 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60968.562182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58095.274536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56066.906005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60968.562182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58095.274536 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 159 # number of replacements -system.cpu.dcache.tags.tagsinuse 1460.308394 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28078942 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12496.191366 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1456.991941 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28100018 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2244 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12522.289661 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1460.308394 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.356521 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.356521 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1456.991941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355711 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355711 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1391 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 56178581 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 56178581 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21585827 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21585827 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492868 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492868 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 247 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 247 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28078695 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28078695 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28078695 # number of overall hits -system.cpu.dcache.overall_hits::total 28078695 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 989 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 989 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8235 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8235 # number of WriteReq misses +system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 56220748 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 56220748 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21606921 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21606921 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492872 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492872 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 225 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 225 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28099793 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28099793 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28099793 # number of overall hits +system.cpu.dcache.overall_hits::total 28099793 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1002 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1002 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8231 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8231 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9224 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9224 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9224 # number of overall misses -system.cpu.dcache.overall_misses::total 9224 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64012750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64012750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 517866286 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 517866286 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9233 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9233 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9233 # number of overall misses +system.cpu.dcache.overall_misses::total 9233 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 62924000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 62924000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 508720531 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 508720531 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 581879036 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 581879036 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 581879036 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 581879036 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21586816 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21586816 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 571644531 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 571644531 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 571644531 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 571644531 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21607923 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21607923 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28087919 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28087919 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28087919 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28087919 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 226 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 226 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28109026 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28109026 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28109026 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28109026 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001267 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001267 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004032 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004032 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001266 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001266 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004425 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004425 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64724.721941 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64724.721941 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62886.009229 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62886.009229 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62798.403194 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62798.403194 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61805.434455 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61805.434455 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63083.156548 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63083.156548 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63083.156548 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63083.156548 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24818 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61913.195170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61913.195170 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23691 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 346 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 343 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.728324 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.069971 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109 # number of writebacks system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 474 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 474 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6504 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6504 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6978 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6978 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6978 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6978 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 490 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6500 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6500 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6990 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6990 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6990 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6990 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37612750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37612750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127737997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 127737997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36779750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36779750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124808747 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 124808747 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165350747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 165350747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 165350747 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 165350747 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161588497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161588497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161588497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161588497 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004032 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004032 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004425 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004425 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73034.466019 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73034.466019 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73794.336800 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73794.336800 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71835.449219 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71835.449219 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72102.106875 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72102.106875 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73620.101069 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73620.101069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73620.101069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73620.101069 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 632b87104..5bf6c1d3d 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1649677 # Simulator instruction rate (inst/s) -host_op_rate 1649676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 824838449 # Simulator tick rate (ticks/s) -host_mem_usage 275016 # Number of bytes of host memory used -host_seconds 55.71 # Real time elapsed on the host +host_inst_rate 2663178 # Simulator instruction rate (inst/s) +host_op_rate 2663177 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1331588953 # Simulator tick rate (ticks/s) +host_mem_usage 260384 # Number of bytes of host memory used +host_seconds 34.51 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 91903136 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched +system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 51001543 55.49% 63.90% # Class of executed instruction +system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction +system.cpu.op_class::FloatAdd 2732464 2.97% 67.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction +system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction +system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction +system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91903089 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index bb6abdd34..88e7e1e1c 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu sim_ticks 118729316000 # Number of ticks simulated final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1382014 # Simulator instruction rate (inst/s) -host_op_rate 1382013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1785419086 # Simulator tick rate (ticks/s) -host_mem_usage 233256 # Number of bytes of host memory used -host_seconds 66.50 # Real time elapsed on the host +host_inst_rate 1199929 # Simulator instruction rate (inst/s) +host_op_rate 1199929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1550185026 # Simulator tick rate (ticks/s) +host_mem_usage 269088 # Number of bytes of host memory used +host_seconds 76.59 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 237458632 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched +system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 51001543 55.49% 63.90% # Class of executed instruction +system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction +system.cpu.op_class::FloatAdd 2732464 2.97% 67.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction +system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction +system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction +system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91903089 # Class of executed instruction system.cpu.icache.tags.replacements 6681 # number of replacements system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. |